/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
D | dce120_resource.c | 677 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
D | dcn201_resource.c | 843 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
D | dcn302_resource.c | 933 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
D | dcn10_resource.c | 817 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
D | dcn303_resource.c | 879 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
D | dcn301_resource.c | 937 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
D | dcn21_resource.c | 1084 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_6_0_d.h | 2465 #define mmDC_PINSTRAPS 0x1917 macro
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D | dce_8_0_d.h | 1279 #define mmDC_PINSTRAPS 0x1917 macro
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D | dce_10_0_d.h | 1566 #define mmDC_PINSTRAPS 0x4818 macro
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D | dce_11_0_d.h | 1391 #define mmDC_PINSTRAPS 0x4818 macro
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D | dce_11_2_d.h | 1471 #define mmDC_PINSTRAPS 0x4818 macro
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D | dce_12_0_offset.h | 1844 #define mmDC_PINSTRAPS … macro
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
D | dcn30_resource.c | 966 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
D | dcn20_resource.c | 986 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), in read_dce_straps()
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
D | dcn_2_0_3_offset.h | 5938 #define mmDC_PINSTRAPS … macro
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D | dcn_3_0_3_offset.h | 5477 #define mmDC_PINSTRAPS … macro
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D | dcn_3_0_1_offset.h | 9124 #define mmDC_PINSTRAPS … macro
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D | dcn_1_0_offset.h | 10389 #define mmDC_PINSTRAPS … macro
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D | dcn_2_1_0_offset.h | 11349 #define mmDC_PINSTRAPS … macro
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D | dcn_3_0_2_offset.h | 11449 #define mmDC_PINSTRAPS … macro
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D | dcn_2_0_0_offset.h | 12766 #define mmDC_PINSTRAPS … macro
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D | dcn_3_0_0_offset.h | 12605 #define mmDC_PINSTRAPS … macro
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