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Searched refs:mmDC_I2C_INTERRUPT_CONTROL (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1336 #define mmDC_I2C_INTERRUPT_CONTROL 0x181B macro
Ddce_8_0_d.h3544 #define mmDC_I2C_INTERRUPT_CONTROL 0x181b macro
Ddce_10_0_d.h7158 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 macro
Ddce_11_0_d.h7348 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 macro
Ddce_11_2_d.h8740 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 macro
Ddce_12_0_offset.h1640 #define mmDC_I2C_INTERRUPT_CONTROL … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5115 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_3_0_3_offset.h4563 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_3_0_1_offset.h7404 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_1_0_offset.h7671 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_2_1_0_offset.h9265 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_3_0_2_offset.h8971 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_2_0_0_offset.h10296 #define mmDC_I2C_INTERRUPT_CONTROL … macro
Ddcn_3_0_0_offset.h10053 #define mmDC_I2C_INTERRUPT_CONTROL … macro