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Searched refs:mmDCCG_AUDIO_DTO1_PHASE (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1137 #define mmDCCG_AUDIO_DTO1_PHASE 0x0170 macro
Ddce_8_0_d.h1079 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e macro
Ddce_10_0_d.h1228 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e macro
Ddce_11_0_d.h1039 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e macro
Ddce_11_2_d.h1117 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e macro
Ddce_12_0_offset.h846 #define mmDCCG_AUDIO_DTO1_PHASE … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1536 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); in dce_v6_0_audio_set_dto()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h130 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_3_0_3_offset.h217 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_3_0_1_offset.h330 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_1_0_offset.h648 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_2_1_0_offset.h286 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_3_0_2_offset.h280 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_2_0_0_offset.h296 #define mmDCCG_AUDIO_DTO1_PHASE … macro
Ddcn_3_0_0_offset.h278 #define mmDCCG_AUDIO_DTO1_PHASE … macro