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Searched refs:mmCRTC_CONTROL (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_timing_generator.c133 uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL); in dce60_timing_generator_enable_advanced_request()
186 addr = CRTC_REG(mmCRTC_CONTROL); in dce60_is_tg_enabled()
Ddce60_resource.c114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce100/
Ddce100_resource.c109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
129 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/
Ddce112_resource.c119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce80/
Ddce80_resource.c113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/
Ddce110_resource.c118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator_v.c595 uint32_t address = mmCRTC_CONTROL; in dce110_timing_generator_v_set_early_control()
Ddce110_timing_generator.c111 uint32_t address = CRTC_REG(mmCRTC_CONTROL); in dce110_timing_generator_set_early_control()
2109 addr = CRTC_REG(mmCRTC_CONTROL); in dce110_is_tg_enabled()
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c372 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
449 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce()
453 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce()
455 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_disable_dce()
Ddce_v10_0.c420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce()
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce()
Ddce_v11_0.c442 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce()
527 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
529 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_disable_dce()
Ddce_v6_0.c407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce()
411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce()
413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h964 #define mmCRTC_CONTROL 0x1B9C macro
Ddce_8_0_d.h333 #define mmCRTC_CONTROL 0x1b9c macro
Ddce_10_0_d.h388 #define mmCRTC_CONTROL 0x1b9c macro
Ddce_11_0_d.h315 #define mmCRTC_CONTROL 0x1b9c macro
Ddce_11_2_d.h322 #define mmCRTC_CONTROL 0x1b9c macro