/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/ |
D | dce60_timing_generator.c | 133 uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL); in dce60_timing_generator_enable_advanced_request() 186 addr = CRTC_REG(mmCRTC_CONTROL); in dce60_is_tg_enabled()
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D | dce60_resource.c | 114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
D | dce100_resource.c | 109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 129 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
D | dce112_resource.c | 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
D | dce80_resource.c | 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
D | dce110_resource.c | 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce110/ |
D | dce110_timing_generator_v.c | 595 uint32_t address = mmCRTC_CONTROL; in dce110_timing_generator_v_set_early_control()
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D | dce110_timing_generator.c | 111 uint32_t address = CRTC_REG(mmCRTC_CONTROL); in dce110_timing_generator_set_early_control() 2109 addr = CRTC_REG(mmCRTC_CONTROL); in dce110_is_tg_enabled()
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v8_0.c | 372 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung() 449 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce() 453 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce() 455 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_disable_dce()
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D | dce_v10_0.c | 420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung() 491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce() 495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce() 497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce()
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D | dce_v11_0.c | 442 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung() 523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce() 527 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce() 529 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_disable_dce()
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D | dce_v6_0.c | 407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce() 411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce() 413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_6_0_d.h | 964 #define mmCRTC_CONTROL 0x1B9C macro
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D | dce_8_0_d.h | 333 #define mmCRTC_CONTROL 0x1b9c macro
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D | dce_10_0_d.h | 388 #define mmCRTC_CONTROL 0x1b9c macro
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D | dce_11_0_d.h | 315 #define mmCRTC_CONTROL 0x1b9c macro
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D | dce_11_2_d.h | 322 #define mmCRTC_CONTROL 0x1b9c macro
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