Home
last modified time | relevance | path

Searched refs:mmCP_RB1_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h501 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_7_2_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_7_0_d.h203 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_8_0_d.h227 #define mmCP_RB1_CNTL 0x3061 macro
Dgfx_8_1_d.h228 #define mmCP_RB1_CNTL 0x3061 macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2161 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
2163 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
2172 WREG32(mmCP_RB1_CNTL, tmp); in gfx_v6_0_cp_compute_resume()
Dgfx_v10_0.c6410 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
6427 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2450 #define mmCP_RB1_CNTL … macro
Dgc_9_1_offset.h2727 #define mmCP_RB1_CNTL … macro
Dgc_9_2_1_offset.h2665 #define mmCP_RB1_CNTL … macro
Dgc_10_1_0_offset.h4791 #define mmCP_RB1_CNTL … macro
Dgc_10_3_0_offset.h4444 #define mmCP_RB1_CNTL … macro