Searched refs:mmCP_RB1_BASE (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 500 #define mmCP_RB1_BASE 0x3060 macro
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| D | gfx_7_2_d.h | 198 #define mmCP_RB1_BASE 0x3060 macro
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| D | gfx_7_0_d.h | 198 #define mmCP_RB1_BASE 0x3060 macro
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| D | gfx_8_0_d.h | 222 #define mmCP_RB1_BASE 0x3060 macro
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| D | gfx_8_1_d.h | 223 #define mmCP_RB1_BASE 0x3060 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2173 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_compute_resume()
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| D | gfx_v10_0.c | 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
6430 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 171 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2448 #define mmCP_RB1_BASE … macro
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| D | gc_9_1_offset.h | 2725 #define mmCP_RB1_BASE … macro
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| D | gc_9_2_1_offset.h | 2663 #define mmCP_RB1_BASE … macro
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| D | gc_10_1_0_offset.h | 4789 #define mmCP_RB1_BASE … macro
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| D | gc_10_3_0_offset.h | 4442 #define mmCP_RB1_BASE … macro
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