Searched refs:mmCP_RB0_WPTR_HI (Results 1 – 7 of 7) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 3347 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
5324 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v9_0_ring_get_wptr_gfx()
5340 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
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| D | gfx_v10_0.c | 6375 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
8449 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v10_0_ring_get_wptr_gfx()
8467 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, in gfx_v10_0_ring_set_wptr_gfx()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2424 #define mmCP_RB0_WPTR_HI … macro
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| D | gc_9_1_offset.h | 2701 #define mmCP_RB0_WPTR_HI … macro
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| D | gc_9_2_1_offset.h | 2639 #define mmCP_RB0_WPTR_HI … macro
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| D | gc_10_1_0_offset.h | 4765 #define mmCP_RB0_WPTR_HI … macro
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| D | gc_10_3_0_offset.h | 4418 #define mmCP_RB0_WPTR_HI … macro
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