Searched refs:mmCP_RB0_CNTL (Results 1 – 16 of 16) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | polaris10_pwrvirus.h | 54 { 0x0840800a, mmCP_RB0_CNTL },
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 495 #define mmCP_RB0_CNTL 0x3041 macro
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| D | gfx_7_2_d.h | 201 #define mmCP_RB0_CNTL 0x3041 macro
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| D | gfx_7_0_d.h | 201 #define mmCP_RB0_CNTL 0x3041 macro
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| D | gfx_8_0_d.h | 225 #define mmCP_RB0_CNTL 0x3041 macro
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| D | gfx_8_1_d.h | 226 #define mmCP_RB0_CNTL 0x3041 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2073 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
2076 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_gfx_resume()
2088 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
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| D | gfx_v7_0.c | 2555 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
2558 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v7_0_cp_gfx_resume()
2571 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
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| D | gfx_v8_0.c | 4256 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v8_0_cp_gfx_resume()
4259 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v8_0_cp_gfx_resume()
4272 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v8_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 3342 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3359 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
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| D | gfx_v10_0.c | 6370 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
6390 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2366 #define mmCP_RB0_CNTL … macro
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| D | gc_9_1_offset.h | 2643 #define mmCP_RB0_CNTL … macro
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| D | gc_9_2_1_offset.h | 2581 #define mmCP_RB0_CNTL … macro
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| D | gc_10_1_0_offset.h | 4711 #define mmCP_RB0_CNTL … macro
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| D | gc_10_3_0_offset.h | 4366 #define mmCP_RB0_CNTL … macro
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