Searched refs:mmCP_RB0_BASE (Results 1 – 15 of 15) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 494 #define mmCP_RB0_BASE 0x3040 macro
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| D | gfx_7_2_d.h | 195 #define mmCP_RB0_BASE 0x3040 macro
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| D | gfx_7_0_d.h | 195 #define mmCP_RB0_BASE 0x3040 macro
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| D | gfx_8_0_d.h | 219 #define mmCP_RB0_BASE 0x3040 macro
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| D | gfx_8_1_d.h | 220 #define mmCP_RB0_BASE 0x3040 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2090 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_gfx_resume()
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| D | gfx_v9_0.c | 168 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
3362 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v9_0_cp_gfx_resume()
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| D | gfx_v7_0.c | 2574 WREG32(mmCP_RB0_BASE, rb_addr); in gfx_v7_0_cp_gfx_resume()
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| D | gfx_v10_0.c | 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
6393 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
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| D | gfx_v8_0.c | 4275 WREG32(mmCP_RB0_BASE, rb_addr); in gfx_v8_0_cp_gfx_resume()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2362 #define mmCP_RB0_BASE … macro
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| D | gc_9_1_offset.h | 2639 #define mmCP_RB0_BASE … macro
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| D | gc_9_2_1_offset.h | 2577 #define mmCP_RB0_BASE … macro
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| D | gc_10_1_0_offset.h | 4707 #define mmCP_RB0_BASE … macro
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| D | gc_10_3_0_offset.h | 4362 #define mmCP_RB0_BASE … macro
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