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Searched refs:mmCP_PWR_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h492 #define mmCP_PWR_CNTL 0x3078 macro
Dgfx_7_2_d.h256 #define mmCP_PWR_CNTL 0x3078 macro
Dgfx_7_0_d.h254 #define mmCP_PWR_CNTL 0x3078 macro
Dgfx_8_0_d.h288 #define mmCP_PWR_CNTL 0x3078 macro
Dgfx_8_1_d.h288 #define mmCP_PWR_CNTL 0x3078 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2480 #define mmCP_PWR_CNTL … macro
Dgc_9_1_offset.h2757 #define mmCP_PWR_CNTL … macro
Dgc_9_2_1_offset.h2695 #define mmCP_PWR_CNTL … macro
Dgc_10_1_0_offset.h4819 #define mmCP_PWR_CNTL … macro
Dgc_10_3_0_offset.h4482 #define mmCP_PWR_CNTL … macro