| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | mxgpu_vi.c | 93 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
224 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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| D | si.c | 551 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
648 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
748 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
828 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
905 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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| D | gfx_v6_0.c | 2576 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2579 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2600 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2603 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
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| D | gfx_v8_0.c | 305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5470 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5691 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5694 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
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| D | gfx_v7_0.c | 3531 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3534 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
3584 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3587 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
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| D | gfx_v9_0.c | 4949 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4952 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4978 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4981 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5293 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
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| D | gfx_v10_0.c | 7856 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7859 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7875 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7878 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
8419 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 455 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_7_2_d.h | 257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_7_0_d.h | 255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_8_0_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| D | gfx_8_1_d.h | 289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2482 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_9_1_offset.h | 2759 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_9_2_1_offset.h | 2697 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_10_1_0_offset.h | 4821 #define mmCP_MEM_SLP_CNTL … macro
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| D | gc_10_3_0_offset.h | 4484 #define mmCP_MEM_SLP_CNTL … macro
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