Searched refs:mmCP_ME1_PIPE0_INT_CNTL (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_2_d.h | 267 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
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| D | gfx_7_0_d.h | 265 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
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| D | gfx_8_0_d.h | 298 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
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| D | gfx_8_1_d.h | 298 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 5971 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6022 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_get_cpc_int_cntl()
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| D | gfx_v10_0.c | 5252 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_get_cpc_int_cntl()
9014 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9327 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
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| D | gfx_v7_0.c | 4658 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
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| D | gfx_v8_0.c | 6447 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2501 #define mmCP_ME1_PIPE0_INT_CNTL … macro
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| D | gc_9_1_offset.h | 2775 #define mmCP_ME1_PIPE0_INT_CNTL … macro
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| D | gc_9_2_1_offset.h | 2711 #define mmCP_ME1_PIPE0_INT_CNTL … macro
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| D | gc_10_1_0_offset.h | 4841 #define mmCP_ME1_PIPE0_INT_CNTL … macro
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| D | gc_10_3_0_offset.h | 4500 #define mmCP_ME1_PIPE0_INT_CNTL … macro
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