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Searched refs:mmCP_INT_CNTL_RING1 (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c3227 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3229 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
3240 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3242 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c5233 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); in gfx_v10_0_get_cpg_int_cntl()
8970 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); in gfx_v10_0_set_gfx_eop_interrupt_state()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h439 #define mmCP_INT_CNTL_RING1 0x306B macro
Dgfx_7_2_d.h223 #define mmCP_INT_CNTL_RING1 0x306b macro
Dgfx_7_0_d.h223 #define mmCP_INT_CNTL_RING1 0x306b macro
Dgfx_8_0_d.h247 #define mmCP_INT_CNTL_RING1 0x306b macro
Dgfx_8_1_d.h248 #define mmCP_INT_CNTL_RING1 0x306b macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2470 #define mmCP_INT_CNTL_RING1 macro
Dgc_9_1_offset.h2747 #define mmCP_INT_CNTL_RING1 macro
Dgc_9_2_1_offset.h2685 #define mmCP_INT_CNTL_RING1 macro
Dgc_10_1_0_offset.h4809 #define mmCP_INT_CNTL_RING1 macro
Dgc_10_3_0_offset.h4462 #define mmCP_INT_CNTL_RING1 macro