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Searched refs:mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_1_offset.h11927 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
Ddcn_3_0_2_offset.h14729 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro
Ddcn_3_0_0_offset.h16355 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … macro