| /linux-6.12.1/drivers/clocksource/ |
| D | timer-sp.h | 42 int mis; member
58 void __iomem *mis; member
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| /linux-6.12.1/drivers/pinctrl/starfive/ |
| D | pinctrl-starfive-jh7110-aon.c | 100 unsigned long mis; in jh7110_aon_irq_handler() local
105 mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); in jh7110_aon_irq_handler()
106 for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) in jh7110_aon_irq_handler()
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| D | pinctrl-starfive-jh7110-sys.c | 367 unsigned long mis; in jh7110_sys_irq_handler() local
372 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); in jh7110_sys_irq_handler()
373 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
376 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); in jh7110_sys_irq_handler()
377 for_each_set_bit(pin, &mis, 32) in jh7110_sys_irq_handler()
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| D | pinctrl-starfive-jh7100.c | 1177 unsigned long mis; in starfive_gpio_irq_handler() local
1182 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1183 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1186 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1187 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 811 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
812 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
813 pool->base.mis[i] = NULL; in dce60_resource_destruct()
1044 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce60_construct()
1045 if (pool->base.mis[i] == NULL) { in dce60_construct()
1242 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce61_construct()
1243 if (pool->base.mis[i] == NULL) { in dce61_construct()
1436 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce64_construct()
1437 if (pool->base.mis[i] == NULL) { in dce64_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| D | dce80_resource.c | 817 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
818 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
819 pool->base.mis[i] = NULL; in dce80_resource_destruct()
1057 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1058 if (pool->base.mis[i] == NULL) { in dce80_construct()
1257 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1258 if (pool->base.mis[i] == NULL) { in dce81_construct()
1454 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1455 if (pool->base.mis[i] == NULL) { in dce83_construct()
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| /linux-6.12.1/fs/ceph/ |
| D | metric.h | 68 __le64 mis; member
103 __le64 mis; member
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| D | metric.c | 69 cap->mis = cpu_to_le64(percpu_counter_sum(&m->i_caps_mis)); in ceph_mdsc_send_metrics()
119 dlease->mis = cpu_to_le64(percpu_counter_sum(&m->d_lease_mis)); in ceph_mdsc_send_metrics()
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| /linux-6.12.1/drivers/pinctrl/spear/ |
| D | pinctrl-plgpio.c | 49 u32 mis; /* mask interrupt status register */ member
383 regmap_read(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
389 regmap_write(plgpio->regmap, plgpio->regs.mis + in plgpio_irq_handler()
509 plgpio->regs.mis = val; in plgpio_probe_dt()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| D | dce100_resource.c | 770 if (pool->base.mis[i] != NULL) { in dce100_resource_destruct()
771 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce100_resource_destruct()
772 pool->base.mis[i] = NULL; in dce100_resource_destruct()
1092 pool->base.mis[i] = dce100_mem_input_create(ctx, i); in dce100_resource_construct()
1093 if (pool->base.mis[i] == NULL) { in dce100_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| D | dce110_resource.c | 826 if (pool->base.mis[i] != NULL) { in dce110_resource_destruct()
827 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce110_resource_destruct()
828 pool->base.mis[i] = NULL; in dce110_resource_destruct()
1138 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1272 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1453 pool->base.mis[i] = dce110_mem_input_create(ctx, i); in dce110_resource_construct()
1454 if (pool->base.mis[i] == NULL) { in dce110_resource_construct()
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| /linux-6.12.1/arch/x86/events/intel/ |
| D | lbr.c | 781 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; in intel_pmu_lbr_read_64() local
799 mis = !!(info & LBR_INFO_MISPRED); in intel_pmu_lbr_read_64()
800 pred = !mis; in intel_pmu_lbr_read_64()
811 mis = !!(from & LBR_FROM_FLAG_MISPRED); in intel_pmu_lbr_read_64()
812 pred = !mis; in intel_pmu_lbr_read_64()
842 br[out].mispred = mis; in intel_pmu_lbr_read_64()
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| /linux-6.12.1/drivers/net/ethernet/realtek/rtase/ |
| D | rtase_main.c | 214 u32 len = ring->mis.len[entry]; in rtase_tx_clear_range()
221 ring->mis.len[entry] = 0; in rtase_tx_clear_range()
285 rtase_unmap_tx_skb(tp->pdev, ring->mis.len[entry], desc); in tx_handler()
286 ring->mis.len[entry] = 0; in tx_handler()
332 ring->mis.len[i] = 0; in rtase_tx_desc_init()
408 &ring->mis.data_phy_addr[i]); in rtase_rx_ring_fill()
543 ring->mis.data_phy_addr[entry], in rx_handler()
596 ring->mis.data_phy_addr[i] = 0; in rtase_rx_desc_init()
1281 ring->mis.len[entry] = len; in rtase_xmit_frags()
1380 ring->mis.len[entry] = len; in rtase_start_xmit()
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| D | rtase.h | 286 } mis; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| D | dce120_resource.c | 610 if (pool->base.mis[i] != NULL) { in dce120_resource_destruct()
611 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce120_resource_destruct()
612 pool->base.mis[i] = NULL; in dce120_resource_destruct()
1179 pool->base.mis[j] = dce120_mem_input_create(ctx, i); in dce120_resource_construct()
1181 if (pool->base.mis[j] == NULL) { in dce120_resource_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| D | dce112_resource.c | 791 if (pool->base.mis[i] != NULL) { in dce112_resource_destruct()
792 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce112_resource_destruct()
793 pool->base.mis[i] = NULL; in dce112_resource_destruct()
1340 pool->base.mis[i] = dce112_mem_input_create(ctx, i); in dce112_resource_construct()
1341 if (pool->base.mis[i] == NULL) { in dce112_resource_construct()
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| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | spear310.dtsi | 109 st-plgpio,mis-reg = <0x60>;
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| D | spear320.dtsi | 137 st-plgpio,mis-reg = <0x84>;
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| D | spear1340.dtsi | 162 st-plgpio,mis-reg = <0xa0>;
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| D | spear1310.dtsi | 302 st-plgpio,mis-reg = <0x10>;
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| /linux-6.12.1/Documentation/staging/ |
| D | speculation.rst | 42 It is possible that a CPU mis-predicts the conditional branch, and
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| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | stv0900_core.c | 1544 enum fe_stv0900_demod_num demod, int mis) in stv0900_set_mis() argument
1548 if (mis < 0 || mis > 255) { in stv0900_set_mis()
1552 dprintk("Enable MIS filtering - %d\n", mis); in stv0900_set_mis()
1554 stv0900_write_reg(intp, ISIENTRY, mis); in stv0900_set_mis()
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| /linux-6.12.1/Documentation/networking/ |
| D | tls.rst | 283 ``TLS_RX_EXPECT_NO_PAD`` mis-prediction. Note that this counter will
288 ``TLS_RX_EXPECT_NO_PAD`` mis-prediction.
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| /linux-6.12.1/drivers/crypto/stm32/ |
| D | stm32-cryp.c | 168 u32 mis; member
2220 cryp->irq_status = stm32_cryp_read(cryp, cryp->caps->mis); in stm32_cryp_irq()
2507 .mis = UX500_CRYP_MIS,
2530 .mis = CRYP_MISR,
2553 .mis = CRYP_MISR,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 229 struct mem_input *mis[MAX_PIPES]; member
|