Searched refs:me_hdr (Results 1 – 8 of 8) sorted by relevance
2563 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_me_cache_rs64() local2565 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_me_cache_rs64()2620 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_me_cache_rs64()2621 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_me_cache_rs64()2623 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_me_cache_rs64()2767 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_gfx_rs64() local2773 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_gfx_rs64()2804 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_gfx_rs64()2805 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_gfx_rs64()2807 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_gfx_rs64()[all …]
1971 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_config_gfx_rs64() local1977 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2008 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v12_0_config_gfx_rs64()2009 (me_hdr->ucode_start_addr_lo >> 2)); in gfx_v12_0_config_gfx_rs64()2011 me_hdr->ucode_start_addr_hi>>2); in gfx_v12_0_config_gfx_rs64()2359 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_cp_gfx_load_me_microcode_rs64() local2365 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2368 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2372 le32_to_cpu(me_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2373 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()[all …]
2386 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v7_0_cp_gfx_load_microcode() local2395 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()2399 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v7_0_cp_gfx_load_microcode()2402 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()2403 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()2432 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_cp_gfx_load_microcode()2433 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v7_0_cp_gfx_load_microcode()
1932 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v6_0_cp_gfx_load_microcode() local1942 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_cp_gfx_load_microcode()1946 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v6_0_cp_gfx_load_microcode()1968 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()1969 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v6_0_cp_gfx_load_microcode()
6105 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v10_0_cp_gfx_load_me_microcode() local6111 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v10_0_cp_gfx_load_me_microcode()6114 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v10_0_cp_gfx_load_me_microcode()6117 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_gfx_load_me_microcode()6118 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); in gfx_v10_0_cp_gfx_load_me_microcode()6120 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, in gfx_v10_0_cp_gfx_load_me_microcode()6170 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v10_0_cp_gfx_load_me_microcode()6172 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_me_microcode()
3198 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v9_0_cp_gfx_load_microcode() local3209 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v9_0_cp_gfx_load_microcode()3214 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v9_0_cp_gfx_load_microcode()3241 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_cp_gfx_load_microcode()3242 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v9_0_cp_gfx_load_microcode()
3898 const struct gfx_firmware_header_v1_0 *me_hdr = in cik_cp_gfx_load_microcode() local3905 radeon_ucode_print_gfx_hdr(&me_hdr->header); in cik_cp_gfx_load_microcode()3927 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in cik_cp_gfx_load_microcode()3928 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in cik_cp_gfx_load_microcode()3932 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()3933 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3470 const struct gfx_firmware_header_v1_0 *me_hdr = in si_cp_load_microcode() local3477 radeon_ucode_print_gfx_hdr(&me_hdr->header); in si_cp_load_microcode()3499 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()3500 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()