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Searched refs:mci_readl (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/mmc/host/
Ddw_mmc-exynos.c89 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; in dw_mci_exynos_get_ciu_div()
91 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; in dw_mci_exynos_get_ciu_div()
120 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); in dw_mci_exynos_priv_init()
121 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); in dw_mci_exynos_priv_init()
147 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
149 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
226 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
228 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
413 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); in dw_mci_exynos_get_clksmpl()
415 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); in dw_mci_exynos_get_clksmpl()
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Ddw_mmc.c155 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); in dw_mci_regs_show()
156 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); in dw_mci_regs_show()
157 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); in dw_mci_regs_show()
158 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); in dw_mci_regs_show()
159 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); in dw_mci_regs_show()
160 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); in dw_mci_regs_show()
195 ctrl = mci_readl(host, CTRL); in dw_mci_ctrl_reset()
291 clk_en_a = mci_readl(host, CLKENA); in dw_mci_prepare_command()
366 cto_clks = mci_readl(host, TMOUT) & 0xff; in dw_mci_set_cto()
367 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; in dw_mci_set_cto()
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Ddw_mmc-hi3798cv200.c31 val = mci_readl(host, UHS_REG); in dw_mci_hi3798cv200_set_ios()
39 val = mci_readl(host, ENABLE_SHIFT); in dw_mci_hi3798cv200_set_ios()
46 val = mci_readl(host, DDR_REG); in dw_mci_hi3798cv200_set_ios()
Ddw_mmc-hi3798mv200.c42 val = mci_readl(host, ENABLE_SHIFT); in dw_mci_hi3798mv200_set_ios()
50 val = mci_readl(host, DDR_REG); in dw_mci_hi3798mv200_set_ios()
119 regval = mci_readl(host, TUNING_CTRL); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
Ddw_mmc-bluefield.c32 reg = mci_readl(host, UHS_REG_EXT); in dw_mci_bluefield_set_ios()
Ddw_mmc-starfive.c45 u32 reg_value = mci_readl(host, UHS_REG_EXT); in dw_mci_starfive_set_sample_phase()
Ddw_mmc-rockchip.c56 raw_value = mci_readl(host, TIMING_CON1); in rockchip_mmc_get_internal_phase()
58 raw_value = mci_readl(host, TIMING_CON0); in rockchip_mmc_get_internal_phase()
Ddw_mmc.h476 #define mci_readl(dev, reg) \ macro