| /linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/ |
| D | ethtool_lanes.sh | 56 local max_lanes=$1; shift
60 local unsupported_lanes=$((max_lanes *= 2))
74 local max_lanes
111 local max_lanes
116 max_lanes=${max_values[1]}
118 lanes=$max_lanes
136 check_unsupported_lanes $swp1 $max_speed $max_lanes 1
149 local max_lanes
154 max_lanes=${max_values[1]}
156 lanes=$max_lanes
[all …]
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| /linux-6.12.1/tools/testing/selftests/drivers/net/hw/ |
| D | devlink_port_split.py | 158 max_lanes = get_max_lanes(port)
162 if max_lanes != lanes:
164 % (port, lanes, max_lanes))
280 max_lanes = get_max_lanes(port.name)
283 if max_lanes == 0:
287 elif max_lanes == 1:
290 split_unsplittable_port(port, max_lanes)
294 lane = max_lanes
298 split_splittable_port(port, lane, max_lanes, dev)
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| /linux-6.12.1/drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 59 u32 max_lanes; member
78 unsigned int max_lanes; member
218 if (pcie->max_lanes == 4) in j721e_pcie_set_lane_count()
338 .max_lanes = 2,
344 .max_lanes = 2,
352 .max_lanes = 2,
359 .max_lanes = 2,
366 .max_lanes = 1,
372 .max_lanes = 1,
380 .max_lanes = 4,
[all …]
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| /linux-6.12.1/drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 95 u8 max_lanes; member
233 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
235 csi2rx->max_lanes); in csi2rx_start()
562 csi2rx->max_lanes = dev_cfg & 7; in csi2rx_get_resources()
563 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { in csi2rx_get_resources()
565 csi2rx->max_lanes); in csi2rx_get_resources()
638 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
716 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
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| D | cdns-csi2tx.c | 117 unsigned int max_lanes; member
465 csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK; in csi2tx_get_resources()
466 if (csi2tx->max_lanes > CSI2TX_LANES_MAX) { in csi2tx_get_resources()
468 csi2tx->max_lanes); in csi2tx_get_resources()
520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /linux-6.12.1/drivers/gpu/drm/rockchip/ |
| D | cdn-dp-reg.c | 539 dp->max_lanes = status[1]; in cdn_dp_get_training_status()
564 dp->max_lanes); in cdn_dp_train_link()
662 do_div(symbol, dp->max_lanes * link_rate * 8); in cdn_dp_config_video()
668 mode->clock, dp->max_lanes, link_rate); in cdn_dp_config_video()
682 val /= (dp->max_lanes * link_rate); in cdn_dp_config_video()
835 if (dp->max_lanes == 1) in cdn_dp_audio_config_i2s()
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| D | cdn-dp-core.h | 98 u8 max_lanes; member
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| D | cdn-dp-core.c | 489 dp->max_lanes = 0; in cdn_dp_disable()
582 if (!port || !dp->max_rate || !dp->max_lanes) in cdn_dp_check_link_status()
988 unsigned int lanes = dp->max_lanes; in cdn_dp_pd_event_work()
1001 (rate != dp->max_rate || lanes != dp->max_lanes)) { in cdn_dp_pd_event_work()
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| /linux-6.12.1/drivers/gpu/drm/tegra/ |
| D | dp.c | 43 link->max_lanes = 0; in drm_dp_link_reset()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
402 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
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| D | dp.h | 125 unsigned int max_lanes; member
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| /linux-6.12.1/drivers/gpu/drm/xlnx/ |
| D | zynqmp_dp.c | 248 u8 max_lanes; member
559 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_mode_configure() local
581 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { in zynqmp_dp_mode_configure()
1390 dp->link_config.max_lanes, dp->config.bpp); in zynqmp_dp_bridge_mode_valid()
1436 dp->link_config.max_lanes, dp->config.bpp); in zynqmp_dp_bridge_atomic_enable()
1558 link_config->max_lanes = min_t(u8, in zynqmp_dp_bridge_detect()
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| /linux-6.12.1/include/drm/ |
| D | drm_connector.h | 286 u8 max_lanes; member
328 u8 max_lanes; member
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_tc.c | 622 int max_lanes; in tc_phy_verify_legacy_or_dp_alt_mode() local
624 max_lanes = intel_tc_port_max_lane_count(dig_port); in tc_phy_verify_legacy_or_dp_alt_mode()
626 drm_WARN_ON(&i915->drm, max_lanes != 4); in tc_phy_verify_legacy_or_dp_alt_mode()
642 if (max_lanes < required_lanes) { in tc_phy_verify_legacy_or_dp_alt_mode()
646 max_lanes, required_lanes); in tc_phy_verify_legacy_or_dp_alt_mode()
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| D | intel_dp.c | 350 int max_lanes = dig_port->max_lanes; in intel_dp_max_source_lane_count() local
353 max_lanes = min(max_lanes, vbt_max_lanes); in intel_dp_max_source_lane_count()
355 return max_lanes; in intel_dp_max_source_lane_count()
1315 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mode_valid() local
1353 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mode_valid()
1355 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); in intel_dp_mode_valid()
1386 max_lanes, in intel_dp_mode_valid()
3585 int max_lanes, rate_per_lane; in intel_dp_hdmi_sink_max_frl() local
3588 max_lanes = connector->display_info.hdmi.max_lanes; in intel_dp_hdmi_sink_max_frl()
3590 max_frl_rate = max_lanes * rate_per_lane; in intel_dp_hdmi_sink_max_frl()
[all …]
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| D | intel_dp_mst.c | 1443 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mst_mode_valid_ctx() local
1470 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_mode_valid_ctx()
1473 max_link_clock, max_lanes); in intel_dp_mst_mode_valid_ctx()
1515 max_lanes, in intel_dp_mst_mode_valid_ctx()
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| D | intel_ddi.c | 1072 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
4666 int max_lanes = 4; in intel_ddi_max_lanes() local
4669 return max_lanes; in intel_ddi_max_lanes()
4673 max_lanes = port == PORT_A ? 4 : 0; in intel_ddi_max_lanes()
4676 max_lanes = 2; in intel_ddi_max_lanes()
4688 max_lanes = 4; in intel_ddi_max_lanes()
4691 return max_lanes; in intel_ddi_max_lanes()
5128 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
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| D | g4x_hdmi.c | 787 dig_port->max_lanes = 4; in g4x_hdmi_init()
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| D | intel_display_types.h | 1936 u8 max_lanes; member
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| D | g4x_dp.c | 1394 dig_port->max_lanes = 4; in g4x_dp_init()
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| /linux-6.12.1/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 371 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) in cdv_intel_dp_max_data_rate() argument
373 return (max_link_clock * max_lanes * 19) / 20; in cdv_intel_dp_max_data_rate()
513 int max_lanes = cdv_intel_dp_max_lane_count(encoder); in cdv_intel_dp_mode_valid() local
527 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) in cdv_intel_dp_mode_valid()
532 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) in cdv_intel_dp_mode_valid()
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| /linux-6.12.1/drivers/gpu/drm/mediatek/ |
| D | mtk_dp.c | 105 u8 max_lanes; member
1405 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1800 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
2072 mtk_dp->max_lanes = len; in mtk_dp_dt_parse()
2414 mtk_dp->max_lanes); in mtk_dp_bridge_mode_valid()
2460 mtk_dp->max_lanes); in mtk_dp_bridge_atomic_get_input_bus_fmts()
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| /linux-6.12.1/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 553 u32 max_lanes, u32 max_rate) in analogix_dp_full_link_train() argument
577 if (dp->link_train.lane_count > max_lanes) in analogix_dp_full_link_train()
578 dp->link_train.lane_count = max_lanes; in analogix_dp_full_link_train()
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| /linux-6.12.1/drivers/gpu/drm/display/ |
| D | drm_dp_helper.c | 2705 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); in drm_dp_lttpr_max_lane_count() local
2707 return max_lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_lttpr_max_lane_count()
3418 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
4303 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes) in drm_dp_max_dprx_data_rate() argument
4308 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes, in drm_dp_max_dprx_data_rate()
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| /linux-6.12.1/drivers/gpu/drm/ |
| D | drm_edid.c | 6080 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) in drm_get_max_frl_rate() argument
6084 *max_lanes = 3; in drm_get_max_frl_rate()
6088 *max_lanes = 3; in drm_get_max_frl_rate()
6092 *max_lanes = 4; in drm_get_max_frl_rate()
6096 *max_lanes = 4; in drm_get_max_frl_rate()
6100 *max_lanes = 4; in drm_get_max_frl_rate()
6104 *max_lanes = 4; in drm_get_max_frl_rate()
6109 *max_lanes = 0; in drm_get_max_frl_rate()
6150 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, in drm_parse_dsc_info()
6244 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, in drm_parse_hdmi_forum_scds()
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| /linux-6.12.1/include/drm/display/ |
| D | drm_dp_helper.h | 873 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
|