Searched refs:max_clocks_khz (Results 1 – 5 of 5) sorted by relevance
107 if (min_table->dram_bw_table.entries[i].min_dcfclk_khz > min_table->max_clocks_khz.dcfclk || in build_min_clk_table_fine_grained()108 min_table->dram_bw_table.entries[i].min_fclk_khz > min_table->max_clocks_khz.fclk) { in build_min_clk_table_fine_grained()179 …min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dis… in build_min_clock_table()180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()181 …min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dsccl… in build_min_clock_table()182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()185 …min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfcl… in build_min_clock_table()186 …min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_… in build_min_clock_table()
39 } max_clocks_khz; member
574 dispclk_khz = math_min2(dispclk_khz, in_out->min_clk_table->max_clocks_khz.dispclk); in map_mode_to_soc_dpm()
7049 mode_lib->ms.MaxDCFCLK = (double)min_clk_table->max_clocks_khz.dcfclk / 1000; in dml_core_mode_support()7050 mode_lib->ms.MaxFabricClock = (double)min_clk_table->max_clocks_khz.fclk / 1000; in dml_core_mode_support()7051 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dispclk / 1000; in dml_core_mode_support()7052 mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; in dml_core_mode_support()7053 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dppclk / 1000; in dml_core_mode_support()7821 if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_clocks_khz.dtbclk / 1000)) { in dml_core_mode_support()9991 const double max_fclk_mhz = min_clk_table->max_clocks_khz.fclk / 1000.0; in dml_core_mode_programming()
775 mode_lib->ms.MaxDCFCLK = (double)min_clk_table->max_clocks_khz.dcfclk / 1000; in dml2_core_shared_mode_support()776 mode_lib->ms.MaxFabricClock = (double)min_clk_table->max_clocks_khz.fclk / 1000; in dml2_core_shared_mode_support()777 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dispclk / 1000; in dml2_core_shared_mode_support()778 mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; in dml2_core_shared_mode_support()779 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dppclk / 1000; in dml2_core_shared_mode_support()11387 double max_fclk_mhz = min_clk_table->max_clocks_khz.fclk / 1000.0; in dml2_core_shared_mode_programming()