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Searched refs:lb_interrupt_mask (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c2994 u32 lb_interrupt_mask; in dce_v10_0_set_crtc_vblank_interrupt_state() local
3003 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3004 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vblank_interrupt_state()
3006 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3009 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3010 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vblank_interrupt_state()
3012 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3023 u32 lb_interrupt_mask; in dce_v10_0_set_crtc_vline_interrupt_state() local
3032 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3033 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vline_interrupt_state()
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Ddce_v11_0.c3125 u32 lb_interrupt_mask; in dce_v11_0_set_crtc_vblank_interrupt_state() local
3134 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3135 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vblank_interrupt_state()
3137 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3140 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3141 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vblank_interrupt_state()
3143 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3154 u32 lb_interrupt_mask; in dce_v11_0_set_crtc_vline_interrupt_state() local
3163 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3164 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vline_interrupt_state()
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Ddce_v8_0.c2905 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vblank_interrupt_state() local
2938 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2939 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vblank_interrupt_state()
2940 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2943 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2944 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vblank_interrupt_state()
2945 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2956 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vline_interrupt_state() local
2989 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vline_interrupt_state()
2990 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vline_interrupt_state()
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