Searched refs:lane_reversal (Results 1 – 9 of 9) sorted by relevance
261 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument266 drm_WARN_ON(&dev_priv->drm, lane_reversal); in intel_combo_phy_power_up_lanes()288 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : in intel_combo_phy_power_up_lanes()292 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : in intel_combo_phy_power_up_lanes()
18 int lane_count, bool lane_reversal);
2679 bool lane_reversal) in intel_program_port_clock_ctl() argument2686 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()2688 if (lane_reversal) in intel_program_port_clock_ctl()2808 bool lane_reversal) in intel_cx0_phy_lane_reset() argument2814 u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; in intel_cx0_phy_lane_reset()2865 bool lane_reversal) in intel_cx0_program_phy_lane() argument2878 if (lane_reversal) in intel_cx0_program_phy_lane()2936 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_cx0pll_enable() local2937 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : in intel_cx0pll_enable()2945 intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); in intel_cx0pll_enable()[all …]
393 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_tc_port_set_fia_lane_count() local400 lane_reversal && tc->mode != TC_PORT_LEGACY); in intel_tc_port_set_fia_lane_count()409 val |= lane_reversal ? in intel_tc_port_set_fia_lane_count()414 val |= lane_reversal ? in intel_tc_port_set_fia_lane_count()
510 u8 lane_reversal:1; /* 184+ */ member
2343 bool lane_reversal = in intel_ddi_power_up_lanes() local2348 lane_reversal); in intel_ddi_power_up_lanes()
3769 return devdata && devdata->child.lane_reversal; in intel_bios_encoder_lane_reversal()
94 u8 lane_reversal:1; /* 184 */ member
10164 u8 lane_reversal[0x1]; member