/linux-6.12.1/drivers/gpu/drm/tests/ |
D | drm_dp_mst_helper_test.c | 73 int lane_count; member 94 .lane_count = 4, 99 .lane_count = 2, 104 .lane_count = 1, 109 .lane_count = 4, 114 .lane_count = 2, 119 .lane_count = 1, 124 .lane_count = 4, 129 .lane_count = 2, 134 .lane_count = 1, [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/ |
D | link_dp_capability.c | 66 enum dc_lane_count lane_count; member 101 .lane_count = LANE_COUNT_ONE, 451 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument 453 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count() 461 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument 463 switch (lane_count) { in reduce_lane_count() 510 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument 512 switch (lane_count) { in increase_lane_count() 582 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy() 592 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy() [all …]
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D | link_dp_training_fixed_vs_pe_retimer.c | 75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument 82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings() 254 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() 295 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence() 304 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence() 325 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local 376 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence() 414 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence() 447 status = dp_get_cr_failure(lane_count, dpcd_lane_status); in dp_perform_fixed_vs_pe_training_sequence() 455 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local [all …]
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D | link_dp_training_8b_10b.c | 103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings() 164 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local 232 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence() 271 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence() 284 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local 337 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence() 343 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence() 344 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
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D | link_dp_training_dpia.c | 295 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local 400 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent() 406 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent() 461 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local 504 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent() 510 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_transparent() 590 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local 684 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent() 689 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent() 690 dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent() [all …]
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D | link_dp_training.c | 172 lt_settings->link_settings.lane_count, in dp_log_training_result() 313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings() 467 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached() 570 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_check_link_loss_status() 631 (uint32_t)(link_training_setting->link_settings.lane_count); in dp_get_lane_status_and_lane_adjust() 1096 lt_settings->link_settings.lane_count; in dpcd_set_link_settings() 1142 lt_settings->link_settings.lane_count, in dpcd_set_link_settings() 1152 lt_settings->link_settings.lane_count, in dpcd_set_link_settings() 1177 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings() 1253 size_in_bytes = lt_settings->link_settings.lane_count * in dpcd_set_lt_pattern_and_lane_settings() [all …]
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D | link_dp_irq_handler.c | 59 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status() 65 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status() 283 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss() 284 link->verified_link_cap.lane_count; in dp_handle_link_loss() 375 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
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/linux-6.12.1/drivers/gpu/drm/i915/display/ |
D | intel_dp_link_training.c | 406 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset() 409 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset() 429 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph() 434 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph() 502 crtc_state->lane_count, in intel_dp_get_adjust_train() 509 crtc_state->lane_count, in intel_dp_get_adjust_train() 543 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train() 544 len = crtc_state->lane_count + 1; in intel_dp_set_link_train() 614 crtc_state->lane_count, in intel_dp_set_signal_levels() 621 crtc_state->lane_count, in intel_dp_set_signal_levels() [all …]
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D | intel_dpio_phy.c | 315 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels() 324 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels() 339 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels() 598 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_dpio_phy_calc_lane_lat_optim_mask() argument 600 switch (lane_count) { in bxt_dpio_phy_calc_lane_lat_optim_mask() 608 MISSING_CASE(lane_count); in bxt_dpio_phy_calc_lane_lat_optim_mask() 737 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level() 750 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level() 758 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level() 766 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level() [all …]
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D | intel_dp.h | 56 int link_rate, int lane_count); 110 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); 111 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); 143 u32 link_clock, u32 lane_count, 160 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument 162 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
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D | vlv_dsi.c | 53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument 57 8 * 100), lane_count); in txbyteclkhs() 61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument 64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs() 1023 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local 1075 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config() 1077 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config() 1079 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config() 1128 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config() 1130 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config() [all …]
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D | intel_combo_phy.c | 261 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument 268 switch (lane_count) { in intel_combo_phy_power_up_lanes() 279 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes() 286 switch (lane_count) { in intel_combo_phy_power_up_lanes() 296 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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D | vlv_dsi_pll.c | 48 int lane_count) in dsi_clk_from_pclk() argument 55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk() 168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk() 183 intel_dsi->lane_count); in vlv_dsi_pll_compute() 349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk() 488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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D | intel_dp_mst.c | 106 overhead = drm_dp_bw_overhead(crtc_state->lane_count, in intel_dp_mst_bw_overhead() 129 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n() 190 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_find_vcpi_slots_for_bpp() 202 crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp() 271 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp() 678 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_dp_mst_compute_config() 1138 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument 1141 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid() 1145 int link_rate, int lane_count) in intel_mst_set_probed_link_params() argument 1148 intel_dp->link.mst_probed_lane_count = lane_count; in intel_mst_set_probed_link_params() [all …]
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D | intel_dp.c | 380 int lane_count; in intel_dp_max_lane_count() local 383 lane_count = forced_lane_count(intel_dp); in intel_dp_max_lane_count() 385 lane_count = intel_dp->link.max_lane_count; in intel_dp_max_lane_count() 387 switch (lane_count) { in intel_dp_max_lane_count() 391 return lane_count; in intel_dp_max_lane_count() 393 MISSING_CASE(lane_count); in intel_dp_max_lane_count() 719 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) in intel_dp_link_config_get() argument 730 *lane_count = intel_dp_link_config_lane_count(lc); in intel_dp_link_config_get() 733 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) in intel_dp_link_config_index() argument 737 int lane_count_exp = ilog2(lane_count); in intel_dp_link_config_index() [all …]
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/linux-6.12.1/drivers/gpu/drm/bridge/analogix/ |
D | analogix_dp_core.c | 229 int lane, lane_count, retval; in analogix_dp_link_start() local 231 lane_count = dp->link_train.lane_count; in analogix_dp_link_start() 236 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start() 251 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start() 255 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start() 267 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start() 283 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start() 288 lane_count); in analogix_dp_link_start() 303 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument 308 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok() [all …]
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/linux-6.12.1/drivers/gpu/drm/msm/dp/ |
D | dp_panel.h | 88 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument 90 return (lane_count == 1 || in is_lane_count_valid() 91 lane_count == 2 || in is_lane_count_valid() 92 lane_count == 4); in is_lane_count_valid()
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/linux-6.12.1/drivers/gpu/drm/gma500/ |
D | cdv_intel_dp.c | 262 uint8_t lane_count; member 897 int lane_count, clock; in cdv_intel_dp_mode_fixup() local 910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup() 912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup() 916 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup() 920 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup() 928 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup() 933 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup() 990 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local 1007 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n() [all …]
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/linux-6.12.1/drivers/gpu/drm/bridge/ |
D | parade-ps8622.c | 54 u32 lane_count; member 184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config() 490 &ps8622->lane_count)) { in ps8622_probe() 491 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe() 492 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe() 495 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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D | ite-it6505.c | 429 u8 lane_count; member 822 switch (it6505->lane_count) { in it6505_lane_termination_on() 834 switch (it6505->lane_count) { in it6505_lane_termination_on() 866 GENMASK(7, 8 - it6505->lane_count) : in it6505_lane_power_on() 867 GENMASK(3 + it6505->lane_count, 4)) | in it6505_lane_power_on() 1184 it6505->lane_count = MAX_LANE_COUNT; in it6505_variable_config() 1488 it6505->lane_count = link->num_lanes; in it6505_parse_link_capabilities() 1490 it6505->lane_count); in it6505_parse_link_capabilities() 1491 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities() 1564 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
D | dcn31_dio_link_encoder.c | 475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output() 522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output() 658 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap() 680 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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/linux-6.12.1/drivers/gpu/drm/mediatek/ |
D | mtk_dp.c | 74 int lane_count; member 1234 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument 1241 .lanes = lane_count, in mtk_dp_phy_configure() 1405 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data() 1427 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init() 1460 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank() 1498 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu() 1795 u8 lane_count, link_rate, train_limit, max_link_rate; in mtk_dp_training() local 1800 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training() 1813 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count); in mtk_dp_training() [all …]
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/linux-6.12.1/drivers/gpu/drm/display/ |
D | drm_dp_helper.c | 90 int lane_count) in drm_dp_channel_eq_ok() argument 100 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok() 110 int lane_count) in drm_dp_clock_recovery_ok() argument 115 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok() 166 int lane_count) in drm_dp_128b132b_lane_channel_eq_done() argument 175 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_channel_eq_done() 186 int lane_count) in drm_dp_128b132b_lane_symbol_locked() argument 191 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_symbol_locked() 4146 static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, in drm_dp_link_symbol_cycles() argument 4149 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); in drm_dp_link_symbol_cycles() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/hwss/ |
D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern() 114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern() 201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
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/linux-6.12.1/include/drm/display/ |
D | drm_dp_helper.h | 37 int lane_count); 39 int lane_count); 62 int lane_count); 64 int lane_count); 869 int drm_dp_bw_overhead(int lane_count, int hactive,
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