| /linux-6.12.1/drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
74 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40) argument
81 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44) argument
91 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) argument
93 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50) argument
94 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) argument
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| D | phy-fsl-imx8qm-hsio.c | 96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
132 if (lane->idx == 0) in imx_hsio_init()
133 lane->clks[i].id = lan0_pcie_clks[i]; in imx_hsio_init()
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| /linux-6.12.1/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
397 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_set() argument
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
407 lane->priv->lane1_phy_regs : in comphy_lane_reg_set()
408 lane->priv->lane0_phy_regs; in comphy_lane_reg_set()
415 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_poll() argument
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| D | phy-mvebu-cp110-comphy.c | 182 unsigned lane; member
190 .lane = _lane, \
200 .lane = _lane, \
277 unsigned long lane, unsigned long mode) in mvebu_comphy_smc() argument
282 arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); in mvebu_comphy_smc()
295 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, in mvebu_comphy_get_mode() argument
309 if (conf->lane == lane && in mvebu_comphy_get_mode()
325 static inline int mvebu_comphy_get_mux(int lane, int port, in mvebu_comphy_get_mux() argument
328 return mvebu_comphy_get_mode(false, lane, port, mode, submode); in mvebu_comphy_get_mux()
331 static inline int mvebu_comphy_get_fw_mode(int lane, int port, in mvebu_comphy_get_fw_mode() argument
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| D | phy-armada38x-comphy.c | 47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
84 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
85 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
91 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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| /linux-6.12.1/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training_fixed_vs_pe_retimer.c | 52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
84 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
86 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
106 uint8_t lane = 0; in perform_fixed_vs_pe_nontransparent_training_sequence() local
168 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
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| D | link_dp_training.c | 305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane].FFE_PRESET.settings.level; in maximize_lane_settings()
347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
348 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING; in maximize_lane_settings()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | vlv_dpio_phy_regs.h | 19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
181 #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) argument
184 #define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) argument
290 #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) argument
291 #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) argument
292 #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
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| D | intel_cx0_phy_regs.h | 34 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
38 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
39 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ argument
41 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
42 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
54 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
58 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
59 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ argument
61 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
62 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
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| D | bxt_dpio_phy_regs.h | 28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
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| D | intel_cx0_phy.c | 78 int lane; in intel_cx0_program_msgbus_timer() local
81 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
120 int lane) in intel_clear_response_ready_flag() argument
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
128 static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane) in intel_cx0_bus_reset() argument
134 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in intel_cx0_bus_reset()
137 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in intel_cx0_bus_reset()
144 intel_clear_response_ready_flag(encoder, lane); in intel_cx0_bus_reset()
148 int command, int lane, u32 *val) in intel_cx0_wait_for_ack() argument
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| D | intel_dp_link_training.c | 401 int lane) in intel_dp_get_lane_adjust_tx_ffe_preset() argument
406 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
407 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); in intel_dp_get_lane_adjust_tx_ffe_preset()
409 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
410 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); in intel_dp_get_lane_adjust_tx_ffe_preset()
421 int lane) in intel_dp_get_lane_adjust_vswing_preemph() argument
429 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
431 v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
432 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
434 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
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| /linux-6.12.1/drivers/phy/tegra/ |
| D | xusb.c | 115 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
118 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
126 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
133 lane->function = err; in tegra_xusb_lane_parse_dt()
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
191 struct phy *lane; in tegra_xusb_pad_register() local
199 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
208 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
223 lane = pad->ops->probe(pad, np, i); in tegra_xusb_pad_register()
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| D | xusb.h | 55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
107 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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| D | xusb-tegra210.c | 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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| D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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| D | xusb-tegra186.c | 321 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
323 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
328 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
331 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
333 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
477 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
479 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
481 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
525 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
527 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
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| /linux-6.12.1/drivers/phy/ |
| D | phy-xgene.c | 658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
699 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
701 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
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| /linux-6.12.1/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.c | 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
39 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
244 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
251 lane = MV88E6341_PORT5_LANE; in mv88e6341_serdes_get_lane()
255 return lane; in mv88e6341_serdes_get_lane()
261 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
268 lane = MV88E6390_PORT9_LANE0; in mv88e6390_serdes_get_lane()
274 lane = MV88E6390_PORT10_LANE0; in mv88e6390_serdes_get_lane()
278 return lane; in mv88e6390_serdes_get_lane()
286 int lane = -ENODEV; in mv88e6390x_serdes_get_lane() local
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| /linux-6.12.1/sound/soc/tegra/ |
| D | tegra186_asrc.c | 109 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
116 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
121 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
173 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
196 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
206 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
225 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
227 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
230 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
233 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 505 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
511 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
512 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
515 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 229 int lane, lane_count, retval; in analogix_dp_link_start() local
236 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
237 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
267 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
268 dp->link_train.training_lane[lane] = in analogix_dp_link_start()
283 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
284 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
295 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
297 int shift = (lane & 1) * 4; in analogix_dp_get_lane_status()
298 u8 link_value = link_status[lane >> 1]; in analogix_dp_get_lane_status()
[all …]
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| /linux-6.12.1/drivers/phy/mediatek/ |
| D | phy-mtk-pcie.c | 81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
146 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); in mtk_pcie_efuse_read_for_lane()
151 snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); in mtk_pcie_efuse_read_for_lane()
159 lane); in mtk_pcie_efuse_read_for_lane()
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| /linux-6.12.1/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-errata.c | 51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
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