1  // SPDX-License-Identifier: GPL-2.0-only
2  /*
3   * Ingenic SoCs pinctrl driver
4   *
5   * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6   * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
7   * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
8   */
9  
10  #include <linux/compiler.h>
11  #include <linux/gpio/driver.h>
12  #include <linux/interrupt.h>
13  #include <linux/io.h>
14  #include <linux/kernel.h>
15  #include <linux/mod_devicetable.h>
16  #include <linux/of.h>
17  #include <linux/platform_device.h>
18  #include <linux/property.h>
19  #include <linux/regmap.h>
20  #include <linux/seq_file.h>
21  #include <linux/slab.h>
22  
23  #include <linux/pinctrl/consumer.h>
24  #include <linux/pinctrl/pinconf-generic.h>
25  #include <linux/pinctrl/pinconf.h>
26  #include <linux/pinctrl/pinctrl.h>
27  #include <linux/pinctrl/pinmux.h>
28  
29  #include "core.h"
30  #include "pinconf.h"
31  #include "pinmux.h"
32  
33  #define GPIO_PIN					0x00
34  #define GPIO_MSK					0x20
35  
36  #define JZ4730_GPIO_DATA			0x00
37  #define JZ4730_GPIO_GPDIR			0x04
38  #define JZ4730_GPIO_GPPUR			0x0c
39  #define JZ4730_GPIO_GPALR			0x10
40  #define JZ4730_GPIO_GPAUR			0x14
41  #define JZ4730_GPIO_GPIDLR			0x18
42  #define JZ4730_GPIO_GPIDUR			0x1c
43  #define JZ4730_GPIO_GPIER			0x20
44  #define JZ4730_GPIO_GPIMR			0x24
45  #define JZ4730_GPIO_GPFR			0x28
46  
47  #define JZ4740_GPIO_DATA			0x10
48  #define JZ4740_GPIO_PULL_DIS		0x30
49  #define JZ4740_GPIO_FUNC			0x40
50  #define JZ4740_GPIO_SELECT			0x50
51  #define JZ4740_GPIO_DIR				0x60
52  #define JZ4740_GPIO_TRIG			0x70
53  #define JZ4740_GPIO_FLAG			0x80
54  
55  #define JZ4770_GPIO_INT				0x10
56  #define JZ4770_GPIO_PAT1			0x30
57  #define JZ4770_GPIO_PAT0			0x40
58  #define JZ4770_GPIO_FLAG			0x50
59  #define JZ4770_GPIO_PEN				0x70
60  
61  #define X1830_GPIO_PEL				0x110
62  #define X1830_GPIO_PEH				0x120
63  #define X1830_GPIO_SR				0x150
64  #define X1830_GPIO_SMT				0x160
65  
66  #define X2000_GPIO_EDG				0x70
67  #define X2000_GPIO_PEPU				0x80
68  #define X2000_GPIO_PEPD				0x90
69  #define X2000_GPIO_SR				0xd0
70  #define X2000_GPIO_SMT				0xe0
71  
72  #define REG_SET(x)					((x) + 0x4)
73  #define REG_CLEAR(x)				((x) + 0x8)
74  
75  #define REG_PZ_BASE(x)				((x) * 7)
76  #define REG_PZ_GID2LD(x)			((x) * 7 + 0xf0)
77  
78  #define GPIO_PULL_DIS				0
79  #define GPIO_PULL_UP				1
80  #define GPIO_PULL_DOWN				2
81  
82  #define PINS_PER_GPIO_CHIP			32
83  #define JZ4730_PINS_PER_PAIRED_REG	16
84  
85  #define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs)					\
86  	{										\
87  		.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)),	\
88  		.data = funcs,								\
89  	}
90  
91  #define INGENIC_PIN_GROUP(_name_, id, func)						\
92  	{										\
93  		.grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)),	\
94  		.data = (void *)func,							\
95  	}
96  
97  #define INGENIC_PIN_FUNCTION(_name_, id)							\
98  	{											\
99  		.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)),	\
100  		.data = NULL,									\
101  	}
102  
103  enum jz_version {
104  	ID_JZ4730,
105  	ID_JZ4740,
106  	ID_JZ4725B,
107  	ID_JZ4750,
108  	ID_JZ4755,
109  	ID_JZ4760,
110  	ID_JZ4770,
111  	ID_JZ4775,
112  	ID_JZ4780,
113  	ID_X1000,
114  	ID_X1500,
115  	ID_X1830,
116  	ID_X2000,
117  	ID_X2100,
118  };
119  
120  struct ingenic_chip_info {
121  	unsigned int num_chips;
122  	unsigned int reg_offset;
123  	enum jz_version version;
124  
125  	const struct group_desc *groups;
126  	unsigned int num_groups;
127  
128  	const struct function_desc *functions;
129  	unsigned int num_functions;
130  
131  	const u32 *pull_ups, *pull_downs;
132  
133  	const struct regmap_access_table *access_table;
134  };
135  
136  struct ingenic_pinctrl {
137  	struct device *dev;
138  	struct regmap *map;
139  	struct pinctrl_dev *pctl;
140  	struct pinctrl_pin_desc *pdesc;
141  
142  	const struct ingenic_chip_info *info;
143  
144  	struct gpio_chip *gc;
145  };
146  
147  struct ingenic_gpio_chip {
148  	struct ingenic_pinctrl *jzpc;
149  	struct gpio_chip gc;
150  	unsigned int irq, reg_base;
151  };
152  
153  static const unsigned long enabled_socs =
154  	IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
155  	IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
156  	IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
157  	IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
158  	IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
159  	IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
160  	IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
161  	IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
162  	IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
163  	IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
164  	IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
165  	IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
166  	IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
167  	IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
168  
169  static bool
is_soc_or_above(const struct ingenic_pinctrl * jzpc,enum jz_version version)170  is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
171  {
172  	return (enabled_socs >> version) &&
173  		(!(enabled_socs & GENMASK(version - 1, 0))
174  		 || jzpc->info->version >= version);
175  }
176  
177  static const u32 jz4730_pull_ups[4] = {
178  	0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
179  };
180  
181  static const u32 jz4730_pull_downs[4] = {
182  	0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
183  };
184  
185  static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
186  static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
187  static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
188  static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
189  static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
190  static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
191  static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
192  static int jz4730_lcd_8bit_pins[] = {
193  	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
194  	0x3a, 0x39, 0x38,
195  };
196  static int jz4730_lcd_16bit_pins[] = {
197  	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
198  };
199  static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
200  static int jz4730_lcd_generic_pins[] = { 0x3b, };
201  static int jz4730_nand_cs1_pins[] = { 0x53, };
202  static int jz4730_nand_cs2_pins[] = { 0x54, };
203  static int jz4730_nand_cs3_pins[] = { 0x55, };
204  static int jz4730_nand_cs4_pins[] = { 0x56, };
205  static int jz4730_nand_cs5_pins[] = { 0x57, };
206  static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
207  static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
208  
209  static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
210  
211  static const struct group_desc jz4730_groups[] = {
212  	INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
213  	INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
214  	INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
215  	INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
216  	INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
217  	INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
218  	INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
219  	INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
220  	INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
221  	INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
222  	INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
223  	INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
224  	INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
225  	INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
226  	INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
227  	INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
228  	INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
229  	INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
230  };
231  
232  static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
233  static const char *jz4730_uart0_groups[] = { "uart0-data", };
234  static const char *jz4730_uart1_groups[] = { "uart1-data", };
235  static const char *jz4730_uart2_groups[] = { "uart2-data", };
236  static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
237  static const char *jz4730_lcd_groups[] = {
238  	"lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
239  };
240  static const char *jz4730_nand_groups[] = {
241  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
242  };
243  static const char *jz4730_pwm0_groups[] = { "pwm0", };
244  static const char *jz4730_pwm1_groups[] = { "pwm1", };
245  
246  static const struct function_desc jz4730_functions[] = {
247  	INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),
248  	INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),
249  	INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),
250  	INGENIC_PIN_FUNCTION("uart2", jz4730_uart2),
251  	INGENIC_PIN_FUNCTION("uart3", jz4730_uart3),
252  	INGENIC_PIN_FUNCTION("lcd", jz4730_lcd),
253  	INGENIC_PIN_FUNCTION("nand", jz4730_nand),
254  	INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0),
255  	INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1),
256  };
257  
258  static const struct ingenic_chip_info jz4730_chip_info = {
259  	.num_chips = 4,
260  	.reg_offset = 0x30,
261  	.version = ID_JZ4730,
262  	.groups = jz4730_groups,
263  	.num_groups = ARRAY_SIZE(jz4730_groups),
264  	.functions = jz4730_functions,
265  	.num_functions = ARRAY_SIZE(jz4730_functions),
266  	.pull_ups = jz4730_pull_ups,
267  	.pull_downs = jz4730_pull_downs,
268  };
269  
270  static const u32 jz4740_pull_ups[4] = {
271  	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
272  };
273  
274  static const u32 jz4740_pull_downs[4] = {
275  	0x00000000, 0x00000000, 0x00000000, 0x00000000,
276  };
277  
278  static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
279  static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
280  static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
281  static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
282  static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
283  static int jz4740_lcd_8bit_pins[] = {
284  	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
285  	0x52, 0x53, 0x54,
286  };
287  static int jz4740_lcd_16bit_pins[] = {
288  	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
289  };
290  static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
291  static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
292  static int jz4740_lcd_generic_pins[] = { 0x55, };
293  static int jz4740_nand_cs1_pins[] = { 0x39, };
294  static int jz4740_nand_cs2_pins[] = { 0x3a, };
295  static int jz4740_nand_cs3_pins[] = { 0x3b, };
296  static int jz4740_nand_cs4_pins[] = { 0x3c, };
297  static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
298  static int jz4740_pwm_pwm0_pins[] = { 0x77, };
299  static int jz4740_pwm_pwm1_pins[] = { 0x78, };
300  static int jz4740_pwm_pwm2_pins[] = { 0x79, };
301  static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
302  static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
303  static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
304  static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
305  static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
306  
307  static const struct group_desc jz4740_groups[] = {
308  	INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
309  	INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
310  	INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
311  	INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
312  	INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
313  	INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
314  	INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
315  	INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
316  	INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
317  	INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
318  	INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
319  	INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
320  	INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
321  	INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
322  	INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
323  	INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
324  	INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
325  	INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
326  	INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
327  	INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
328  	INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
329  	INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
330  	INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
331  };
332  
333  static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
334  static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
335  static const char *jz4740_uart1_groups[] = { "uart1-data", };
336  static const char *jz4740_lcd_groups[] = {
337  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
338  };
339  static const char *jz4740_nand_groups[] = {
340  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
341  };
342  static const char *jz4740_pwm0_groups[] = { "pwm0", };
343  static const char *jz4740_pwm1_groups[] = { "pwm1", };
344  static const char *jz4740_pwm2_groups[] = { "pwm2", };
345  static const char *jz4740_pwm3_groups[] = { "pwm3", };
346  static const char *jz4740_pwm4_groups[] = { "pwm4", };
347  static const char *jz4740_pwm5_groups[] = { "pwm5", };
348  static const char *jz4740_pwm6_groups[] = { "pwm6", };
349  static const char *jz4740_pwm7_groups[] = { "pwm7", };
350  
351  static const struct function_desc jz4740_functions[] = {
352  	INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),
353  	INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),
354  	INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),
355  	INGENIC_PIN_FUNCTION("lcd", jz4740_lcd),
356  	INGENIC_PIN_FUNCTION("nand", jz4740_nand),
357  	INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0),
358  	INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1),
359  	INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2),
360  	INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3),
361  	INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4),
362  	INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5),
363  	INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6),
364  	INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7),
365  };
366  
367  static const struct ingenic_chip_info jz4740_chip_info = {
368  	.num_chips = 4,
369  	.reg_offset = 0x100,
370  	.version = ID_JZ4740,
371  	.groups = jz4740_groups,
372  	.num_groups = ARRAY_SIZE(jz4740_groups),
373  	.functions = jz4740_functions,
374  	.num_functions = ARRAY_SIZE(jz4740_functions),
375  	.pull_ups = jz4740_pull_ups,
376  	.pull_downs = jz4740_pull_downs,
377  };
378  
379  static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
380  static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
381  static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
382  static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
383  static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
384  static int jz4725b_lcd_8bit_pins[] = {
385  	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
386  	0x72, 0x73, 0x74,
387  };
388  static int jz4725b_lcd_16bit_pins[] = {
389  	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
390  };
391  static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
392  static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
393  static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
394  static int jz4725b_lcd_generic_pins[] = { 0x75, };
395  static int jz4725b_nand_cs1_pins[] = { 0x55, };
396  static int jz4725b_nand_cs2_pins[] = { 0x56, };
397  static int jz4725b_nand_cs3_pins[] = { 0x57, };
398  static int jz4725b_nand_cs4_pins[] = { 0x58, };
399  static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
400  static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
401  static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
402  static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
403  static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
404  static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
405  static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
406  static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
407  
408  static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
409  
410  static const struct group_desc jz4725b_groups[] = {
411  	INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
412  	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
413  				jz4725b_mmc0_4bit_funcs),
414  	INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
415  	INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
416  	INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
417  	INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
418  	INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
419  	INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
420  	INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
421  	INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
422  	INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
423  	INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
424  	INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
425  	INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
426  	INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
427  	INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
428  	INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
429  	INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
430  	INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
431  	INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
432  	INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
433  	INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
434  	INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
435  };
436  
437  static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
438  static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
439  static const char *jz4725b_uart_groups[] = { "uart-data", };
440  static const char *jz4725b_lcd_groups[] = {
441  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
442  	"lcd-special", "lcd-generic",
443  };
444  static const char *jz4725b_nand_groups[] = {
445  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
446  	"nand-cle-ale", "nand-fre-fwe",
447  };
448  static const char *jz4725b_pwm0_groups[] = { "pwm0", };
449  static const char *jz4725b_pwm1_groups[] = { "pwm1", };
450  static const char *jz4725b_pwm2_groups[] = { "pwm2", };
451  static const char *jz4725b_pwm3_groups[] = { "pwm3", };
452  static const char *jz4725b_pwm4_groups[] = { "pwm4", };
453  static const char *jz4725b_pwm5_groups[] = { "pwm5", };
454  
455  static const struct function_desc jz4725b_functions[] = {
456  	INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),
457  	INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),
458  	INGENIC_PIN_FUNCTION("uart", jz4725b_uart),
459  	INGENIC_PIN_FUNCTION("nand", jz4725b_nand),
460  	INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0),
461  	INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1),
462  	INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2),
463  	INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3),
464  	INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4),
465  	INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5),
466  	INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd),
467  };
468  
469  static const struct ingenic_chip_info jz4725b_chip_info = {
470  	.num_chips = 4,
471  	.reg_offset = 0x100,
472  	.version = ID_JZ4725B,
473  	.groups = jz4725b_groups,
474  	.num_groups = ARRAY_SIZE(jz4725b_groups),
475  	.functions = jz4725b_functions,
476  	.num_functions = ARRAY_SIZE(jz4725b_functions),
477  	.pull_ups = jz4740_pull_ups,
478  	.pull_downs = jz4740_pull_downs,
479  };
480  
481  static const u32 jz4750_pull_ups[6] = {
482  	0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
483  };
484  
485  static const u32 jz4750_pull_downs[6] = {
486  	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
487  };
488  
489  static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
490  static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
491  static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
492  static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
493  static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
494  static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
495  static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
496  static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
497  static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
498  static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
499  static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
500  static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
501  static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
502  static int jz4750_cim_pins[] = {
503  	0x89, 0x8b, 0x8a, 0x88,
504  	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
505  };
506  static int jz4750_lcd_8bit_pins[] = {
507  	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
508  	0x72, 0x73, 0x74,
509  };
510  static int jz4750_lcd_16bit_pins[] = {
511  	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
512  };
513  static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
514  static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
515  static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
516  static int jz4750_lcd_generic_pins[] = { 0x75, };
517  static int jz4750_nand_cs1_pins[] = { 0x55, };
518  static int jz4750_nand_cs2_pins[] = { 0x56, };
519  static int jz4750_nand_cs3_pins[] = { 0x57, };
520  static int jz4750_nand_cs4_pins[] = { 0x58, };
521  static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
522  static int jz4750_pwm_pwm0_pins[] = { 0x94, };
523  static int jz4750_pwm_pwm1_pins[] = { 0x95, };
524  static int jz4750_pwm_pwm2_pins[] = { 0x96, };
525  static int jz4750_pwm_pwm3_pins[] = { 0x97, };
526  static int jz4750_pwm_pwm4_pins[] = { 0x98, };
527  static int jz4750_pwm_pwm5_pins[] = { 0x99, };
528  
529  static const struct group_desc jz4750_groups[] = {
530  	INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
531  	INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
532  	INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
533  	INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
534  	INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
535  	INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
536  	INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
537  	INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
538  	INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
539  	INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
540  	INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
541  	INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
542  	INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
543  	INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
544  	INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
545  	INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
546  	INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
547  	INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
548  	INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
549  	INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
550  	INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
551  	INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
552  	INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
553  	INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
554  	INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
555  	INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
556  	INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
557  	INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
558  	INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
559  	INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
560  	INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
561  };
562  
563  static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
564  static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
565  static const char *jz4750_uart2_groups[] = { "uart2-data", };
566  static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
567  static const char *jz4750_mmc0_groups[] = {
568  	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
569  };
570  static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
571  static const char *jz4750_i2c_groups[] = { "i2c-data", };
572  static const char *jz4750_cim_groups[] = { "cim-data", };
573  static const char *jz4750_lcd_groups[] = {
574  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
575  	"lcd-special", "lcd-generic",
576  };
577  static const char *jz4750_nand_groups[] = {
578  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
579  };
580  static const char *jz4750_pwm0_groups[] = { "pwm0", };
581  static const char *jz4750_pwm1_groups[] = { "pwm1", };
582  static const char *jz4750_pwm2_groups[] = { "pwm2", };
583  static const char *jz4750_pwm3_groups[] = { "pwm3", };
584  static const char *jz4750_pwm4_groups[] = { "pwm4", };
585  static const char *jz4750_pwm5_groups[] = { "pwm5", };
586  
587  static const struct function_desc jz4750_functions[] = {
588  	INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),
589  	INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),
590  	INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),
591  	INGENIC_PIN_FUNCTION("uart3", jz4750_uart3),
592  	INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0),
593  	INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1),
594  	INGENIC_PIN_FUNCTION("i2c", jz4750_i2c),
595  	INGENIC_PIN_FUNCTION("cim", jz4750_cim),
596  	INGENIC_PIN_FUNCTION("lcd", jz4750_lcd),
597  	INGENIC_PIN_FUNCTION("nand", jz4750_nand),
598  	INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0),
599  	INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1),
600  	INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2),
601  	INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3),
602  	INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4),
603  	INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5),
604  };
605  
606  static const struct ingenic_chip_info jz4750_chip_info = {
607  	.num_chips = 6,
608  	.reg_offset = 0x100,
609  	.version = ID_JZ4750,
610  	.groups = jz4750_groups,
611  	.num_groups = ARRAY_SIZE(jz4750_groups),
612  	.functions = jz4750_functions,
613  	.num_functions = ARRAY_SIZE(jz4750_functions),
614  	.pull_ups = jz4750_pull_ups,
615  	.pull_downs = jz4750_pull_downs,
616  };
617  
618  static const u32 jz4755_pull_ups[6] = {
619  	0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
620  };
621  
622  static const u32 jz4755_pull_downs[6] = {
623  	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
624  };
625  
626  static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
627  static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
628  static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
629  static int jz4755_uart2_data_pins[] = { 0x9f, };
630  static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
631  static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
632  static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
633  static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
634  static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
635  static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
636  static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
637  static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
638  static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
639  static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
640  static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
641  static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
642  static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
643  static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
644  static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
645  static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
646  static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
647  static int jz4755_cim_pins[] = {
648  	0x89, 0x8b, 0x8a, 0x88,
649  	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
650  };
651  static int jz4755_lcd_8bit_pins[] = {
652  	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
653  	0x72, 0x73, 0x74,
654  };
655  static int jz4755_lcd_16bit_pins[] = {
656  	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
657  };
658  static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
659  static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
660  static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
661  static int jz4755_lcd_generic_pins[] = { 0x75, };
662  static int jz4755_nand_cs1_pins[] = { 0x55, };
663  static int jz4755_nand_cs2_pins[] = { 0x56, };
664  static int jz4755_nand_cs3_pins[] = { 0x57, };
665  static int jz4755_nand_cs4_pins[] = { 0x58, };
666  static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
667  static int jz4755_pwm_pwm0_pins[] = { 0x94, };
668  static int jz4755_pwm_pwm1_pins[] = { 0xab, };
669  static int jz4755_pwm_pwm2_pins[] = { 0x96, };
670  static int jz4755_pwm_pwm3_pins[] = { 0x97, };
671  static int jz4755_pwm_pwm4_pins[] = { 0x98, };
672  static int jz4755_pwm_pwm5_pins[] = { 0x99, };
673  
674  static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
675  static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
676  static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
677  
678  static const struct group_desc jz4755_groups[] = {
679  	INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
680  	INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
681  	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
682  	INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
683  	INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
684  	INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
685  	INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
686  	INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
687  	INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
688  	INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
689  	INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
690  	INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
691  	INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
692  	INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
693  	INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
694  	INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
695  	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
696  				jz4755_mmc0_1bit_funcs),
697  	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
698  				jz4755_mmc0_4bit_funcs),
699  	INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
700  	INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
701  	INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
702  	INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
703  	INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
704  	INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
705  	INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
706  	INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
707  				jz4755_lcd_24bit_funcs),
708  	INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
709  	INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
710  	INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
711  	INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
712  	INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
713  	INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
714  	INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
715  	INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
716  	INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
717  	INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
718  	INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
719  	INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
720  	INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
721  };
722  
723  static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
724  static const char *jz4755_uart1_groups[] = { "uart1-data", };
725  static const char *jz4755_uart2_groups[] = { "uart2-data", };
726  static const char *jz4755_ssi_groups[] = {
727  	"ssi-dt-b", "ssi-dt-f",
728  	"ssi-dr-b", "ssi-dr-f",
729  	"ssi-clk-b", "ssi-clk-f",
730  	"ssi-gpc-b", "ssi-gpc-f",
731  	"ssi-ce0-b", "ssi-ce0-f",
732  	"ssi-ce1-b", "ssi-ce1-f",
733  };
734  static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
735  static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
736  static const char *jz4755_i2c_groups[] = { "i2c-data", };
737  static const char *jz4755_cim_groups[] = { "cim-data", };
738  static const char *jz4755_lcd_groups[] = {
739  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
740  	"lcd-special", "lcd-generic",
741  };
742  static const char *jz4755_nand_groups[] = {
743  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
744  };
745  static const char *jz4755_pwm0_groups[] = { "pwm0", };
746  static const char *jz4755_pwm1_groups[] = { "pwm1", };
747  static const char *jz4755_pwm2_groups[] = { "pwm2", };
748  static const char *jz4755_pwm3_groups[] = { "pwm3", };
749  static const char *jz4755_pwm4_groups[] = { "pwm4", };
750  static const char *jz4755_pwm5_groups[] = { "pwm5", };
751  
752  static const struct function_desc jz4755_functions[] = {
753  	INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),
754  	INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),
755  	INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),
756  	INGENIC_PIN_FUNCTION("ssi", jz4755_ssi),
757  	INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0),
758  	INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1),
759  	INGENIC_PIN_FUNCTION("i2c", jz4755_i2c),
760  	INGENIC_PIN_FUNCTION("cim", jz4755_cim),
761  	INGENIC_PIN_FUNCTION("lcd", jz4755_lcd),
762  	INGENIC_PIN_FUNCTION("nand", jz4755_nand),
763  	INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0),
764  	INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1),
765  	INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2),
766  	INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3),
767  	INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4),
768  	INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5),
769  };
770  
771  static const struct ingenic_chip_info jz4755_chip_info = {
772  	.num_chips = 6,
773  	.reg_offset = 0x100,
774  	.version = ID_JZ4755,
775  	.groups = jz4755_groups,
776  	.num_groups = ARRAY_SIZE(jz4755_groups),
777  	.functions = jz4755_functions,
778  	.num_functions = ARRAY_SIZE(jz4755_functions),
779  	.pull_ups = jz4755_pull_ups,
780  	.pull_downs = jz4755_pull_downs,
781  };
782  
783  static const u32 jz4760_pull_ups[6] = {
784  	0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
785  };
786  
787  static const u32 jz4760_pull_downs[6] = {
788  	0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
789  };
790  
791  static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
792  static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
793  static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
794  static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
795  static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
796  static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
797  static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
798  static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
799  static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
800  static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
801  static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
802  static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
803  static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
804  static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
805  static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
806  static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
807  static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
808  static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
809  static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
810  static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
811  static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
812  static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
813  static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
814  static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
815  static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
816  static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
817  static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
818  static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
819  static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
820  static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
821  static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
822  static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
823  static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
824  static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
825  static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
826  static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
827  static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
828  static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
829  static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
830  static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
831  static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
832  static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
833  static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
834  static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
835  static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
836  static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
837  static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
838  static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
839  static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
840  static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
841  static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
842  static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
843  static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
844  static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
845  static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
846  static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
847  static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
848  static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
849  static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
850  static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
851  static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
852  static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
853  static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
854  static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
855  static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
856  static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
857  static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
858  static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
859  static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
860  static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
861  static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
862  static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
863  static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
864  static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
865  static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
866  static int jz4760_nemc_8bit_data_pins[] = {
867  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
868  };
869  static int jz4760_nemc_16bit_data_pins[] = {
870  	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
871  };
872  static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
873  static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
874  static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
875  static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
876  static int jz4760_nemc_wait_pins[] = { 0x1b, };
877  static int jz4760_nemc_cs1_pins[] = { 0x15, };
878  static int jz4760_nemc_cs2_pins[] = { 0x16, };
879  static int jz4760_nemc_cs3_pins[] = { 0x17, };
880  static int jz4760_nemc_cs4_pins[] = { 0x18, };
881  static int jz4760_nemc_cs5_pins[] = { 0x19, };
882  static int jz4760_nemc_cs6_pins[] = { 0x1a, };
883  static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
884  static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
885  static int jz4760_cim_pins[] = {
886  	0x26, 0x27, 0x28, 0x29,
887  	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
888  };
889  static int jz4760_lcd_8bit_pins[] = {
890  	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
891  	0x4d, 0x52, 0x53,
892  };
893  static int jz4760_lcd_16bit_pins[] = {
894  	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
895  };
896  static int jz4760_lcd_18bit_pins[] = {
897  	0x5a, 0x5b,
898  };
899  static int jz4760_lcd_24bit_pins[] = {
900  	0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
901  };
902  static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
903  static int jz4760_lcd_generic_pins[] = { 0x49, };
904  static int jz4760_pwm_pwm0_pins[] = { 0x80, };
905  static int jz4760_pwm_pwm1_pins[] = { 0x81, };
906  static int jz4760_pwm_pwm2_pins[] = { 0x82, };
907  static int jz4760_pwm_pwm3_pins[] = { 0x83, };
908  static int jz4760_pwm_pwm4_pins[] = { 0x84, };
909  static int jz4760_pwm_pwm5_pins[] = { 0x85, };
910  static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
911  static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
912  static int jz4760_otg_pins[] = { 0x8a, };
913  
914  static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
915  static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
916  
917  static const struct group_desc jz4760_groups[] = {
918  	INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
919  	INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
920  	INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
921  	INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
922  	INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
923  	INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
924  	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
925  				jz4760_uart3_data_funcs),
926  	INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
927  	INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
928  	INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
929  	INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
930  	INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
931  	INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
932  	INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
933  	INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
934  	INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
935  	INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
936  	INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
937  	INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
938  	INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
939  	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
940  	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
941  	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
942  	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
943  	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
944  	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
945  	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
946  	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
947  	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
948  	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
949  	INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
950  	INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
951  	INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
952  	INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
953  	INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
954  	INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
955  	INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
956  	INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
957  	INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
958  	INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
959  	INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
960  	INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
961  	INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
962  	INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
963  	INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
964  	INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
965  	INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
966  	INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
967  	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
968  	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
969  	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
970  	INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
971  	INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
972  	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
973  	INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
974  	INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
975  	INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
976  	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
977  	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
978  	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
979  	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
980  				jz4760_mmc0_1bit_a_funcs),
981  	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
982  	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
983  	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
984  	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
985  	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
986  	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
987  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
988  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
989  	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
990  	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
991  	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
992  	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
993  	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
994  	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
995  	INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
996  	INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
997  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
998  	INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
999  	INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
1000  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
1001  	INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
1002  	INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
1003  	INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
1004  	INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
1005  	INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
1006  	INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
1007  	INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
1008  	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1009  	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1010  	INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1011  	INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1012  	INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1013  	INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1014  	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1015  	INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1016  	INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1017  	INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
1018  	INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
1019  	INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
1020  	INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
1021  	INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
1022  	INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
1023  	INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
1024  	INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
1025  	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1026  };
1027  
1028  static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1029  static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1030  static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1031  static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1032  static const char *jz4760_ssi0_groups[] = {
1033  	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1034  	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1035  	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1036  	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1037  	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1038  	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1039  };
1040  static const char *jz4760_ssi1_groups[] = {
1041  	"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1042  	"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1043  	"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1044  	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1045  	"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1046  	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1047  };
1048  static const char *jz4760_mmc0_groups[] = {
1049  	"mmc0-1bit-a", "mmc0-4bit-a",
1050  	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1051  };
1052  static const char *jz4760_mmc1_groups[] = {
1053  	"mmc1-1bit-d", "mmc1-4bit-d",
1054  	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1055  };
1056  static const char *jz4760_mmc2_groups[] = {
1057  	"mmc2-1bit-b", "mmc2-4bit-b",
1058  	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1059  };
1060  static const char *jz4760_nemc_groups[] = {
1061  	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1062  	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1063  };
1064  static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1065  static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1066  static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1067  static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1068  static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1069  static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1070  static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1071  static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1072  static const char *jz4760_cim_groups[] = { "cim-data", };
1073  static const char *jz4760_lcd_groups[] = {
1074  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1075  	"lcd-special", "lcd-generic",
1076  };
1077  static const char *jz4760_pwm0_groups[] = { "pwm0", };
1078  static const char *jz4760_pwm1_groups[] = { "pwm1", };
1079  static const char *jz4760_pwm2_groups[] = { "pwm2", };
1080  static const char *jz4760_pwm3_groups[] = { "pwm3", };
1081  static const char *jz4760_pwm4_groups[] = { "pwm4", };
1082  static const char *jz4760_pwm5_groups[] = { "pwm5", };
1083  static const char *jz4760_pwm6_groups[] = { "pwm6", };
1084  static const char *jz4760_pwm7_groups[] = { "pwm7", };
1085  static const char *jz4760_otg_groups[] = { "otg-vbus", };
1086  
1087  static const struct function_desc jz4760_functions[] = {
1088  	INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),
1089  	INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),
1090  	INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),
1091  	INGENIC_PIN_FUNCTION("uart3", jz4760_uart3),
1092  	INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0),
1093  	INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1),
1094  	INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0),
1095  	INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1),
1096  	INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2),
1097  	INGENIC_PIN_FUNCTION("nemc", jz4760_nemc),
1098  	INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
1099  	INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
1100  	INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
1101  	INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
1102  	INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
1103  	INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
1104  	INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0),
1105  	INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1),
1106  	INGENIC_PIN_FUNCTION("cim", jz4760_cim),
1107  	INGENIC_PIN_FUNCTION("lcd", jz4760_lcd),
1108  	INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0),
1109  	INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1),
1110  	INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2),
1111  	INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3),
1112  	INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4),
1113  	INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5),
1114  	INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6),
1115  	INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7),
1116  	INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1117  };
1118  
1119  static const struct ingenic_chip_info jz4760_chip_info = {
1120  	.num_chips = 6,
1121  	.reg_offset = 0x100,
1122  	.version = ID_JZ4760,
1123  	.groups = jz4760_groups,
1124  	.num_groups = ARRAY_SIZE(jz4760_groups),
1125  	.functions = jz4760_functions,
1126  	.num_functions = ARRAY_SIZE(jz4760_functions),
1127  	.pull_ups = jz4760_pull_ups,
1128  	.pull_downs = jz4760_pull_downs,
1129  };
1130  
1131  static const u32 jz4770_pull_ups[6] = {
1132  	0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
1133  };
1134  
1135  static const u32 jz4770_pull_downs[6] = {
1136  	0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
1137  };
1138  
1139  static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
1140  static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1141  static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
1142  static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1143  static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
1144  static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
1145  static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
1146  static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
1147  static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
1148  static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
1149  static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
1150  static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
1151  static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
1152  static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
1153  static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
1154  static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
1155  static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
1156  static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
1157  static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
1158  static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
1159  static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
1160  static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
1161  static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
1162  static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
1163  static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
1164  static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
1165  static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
1166  static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
1167  static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
1168  static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
1169  static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
1170  static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
1171  static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
1172  static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
1173  static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
1174  static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
1175  static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
1176  static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
1177  static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
1178  static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
1179  static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
1180  static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
1181  static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
1182  static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
1183  static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
1184  static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
1185  static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
1186  static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
1187  static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1188  static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1189  static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1190  static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1191  static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1192  static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1193  static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1194  static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1195  static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1196  static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1197  static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1198  static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1199  static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1200  static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1201  static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1202  static int jz4770_nemc_8bit_data_pins[] = {
1203  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1204  };
1205  static int jz4770_nemc_16bit_data_pins[] = {
1206  	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1207  };
1208  static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1209  static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1210  static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
1211  static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1212  static int jz4770_nemc_wait_pins[] = { 0x1b, };
1213  static int jz4770_nemc_cs1_pins[] = { 0x15, };
1214  static int jz4770_nemc_cs2_pins[] = { 0x16, };
1215  static int jz4770_nemc_cs3_pins[] = { 0x17, };
1216  static int jz4770_nemc_cs4_pins[] = { 0x18, };
1217  static int jz4770_nemc_cs5_pins[] = { 0x19, };
1218  static int jz4770_nemc_cs6_pins[] = { 0x1a, };
1219  static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
1220  static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
1221  static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
1222  static int jz4770_cim_8bit_pins[] = {
1223  	0x26, 0x27, 0x28, 0x29,
1224  	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1225  };
1226  static int jz4770_cim_12bit_pins[] = {
1227  	0x32, 0x33, 0xb0, 0xb1,
1228  };
1229  static int jz4770_lcd_8bit_pins[] = {
1230  	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1231  	0x48, 0x52, 0x53,
1232  };
1233  static int jz4770_lcd_16bit_pins[] = {
1234  	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1235  };
1236  static int jz4770_lcd_18bit_pins[] = {
1237  	0x5a, 0x5b,
1238  };
1239  static int jz4770_lcd_24bit_pins[] = {
1240  	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
1241  	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
1242  	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
1243  	0x58, 0x59, 0x5a, 0x5b,
1244  };
1245  static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1246  static int jz4770_lcd_generic_pins[] = { 0x49, };
1247  static int jz4770_pwm_pwm0_pins[] = { 0x80, };
1248  static int jz4770_pwm_pwm1_pins[] = { 0x81, };
1249  static int jz4770_pwm_pwm2_pins[] = { 0x82, };
1250  static int jz4770_pwm_pwm3_pins[] = { 0x83, };
1251  static int jz4770_pwm_pwm4_pins[] = { 0x84, };
1252  static int jz4770_pwm_pwm5_pins[] = { 0x85, };
1253  static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
1254  static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
1255  static int jz4770_mac_rmii_pins[] = {
1256  	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1257  };
1258  static int jz4770_mac_mii_pins[] = {
1259  	0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1260  };
1261  
1262  static const struct group_desc jz4770_groups[] = {
1263  	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1264  	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1265  	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1266  	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1267  	INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1268  	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1269  	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1270  				jz4760_uart3_data_funcs),
1271  	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1272  	INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1273  	INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1274  	INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1275  	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1276  	INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1277  	INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1278  	INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1279  	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1280  	INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1281  	INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1282  	INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1283  	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1284  	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1285  	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1286  	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1287  	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1288  	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1289  	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1290  	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1291  	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1292  	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1293  	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1294  	INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1295  	INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1296  	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1297  	INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1298  	INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1299  	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1300  	INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1301  	INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1302  	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1303  	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1304  	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1305  	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1306  	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1307  	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1308  	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1309  	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1310  	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1311  	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1312  	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1313  				jz4760_mmc0_1bit_a_funcs),
1314  	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1315  	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1316  	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1317  	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1318  	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1319  	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1320  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1321  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1322  	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1323  	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1324  	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1325  	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1326  	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1327  	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1328  	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1329  	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1330  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1331  	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1332  	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1333  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1334  	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1335  	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1336  	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1337  	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1338  	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1339  	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1340  	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1341  	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1342  	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1343  	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1344  	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1345  	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1346  	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1347  	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1348  	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1349  	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1350  	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1351  	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1352  	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1353  	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1354  	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1355  	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1356  	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1357  	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1358  	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1359  	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1360  	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1361  	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1362  	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1363  };
1364  
1365  static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1366  static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1367  static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1368  static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1369  static const char *jz4770_ssi0_groups[] = {
1370  	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1371  	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1372  	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1373  	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1374  	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1375  	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1376  };
1377  static const char *jz4770_ssi1_groups[] = {
1378  	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1379  	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1380  	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1381  	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1382  	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1383  	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1384  };
1385  static const char *jz4770_mmc0_groups[] = {
1386  	"mmc0-1bit-a", "mmc0-4bit-a",
1387  	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1388  };
1389  static const char *jz4770_mmc1_groups[] = {
1390  	"mmc1-1bit-d", "mmc1-4bit-d",
1391  	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1392  };
1393  static const char *jz4770_mmc2_groups[] = {
1394  	"mmc2-1bit-b", "mmc2-4bit-b",
1395  	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1396  };
1397  static const char *jz4770_nemc_groups[] = {
1398  	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1399  	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1400  };
1401  static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1402  static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1403  static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1404  static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1405  static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1406  static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1407  static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1408  static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1409  static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1410  static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1411  static const char *jz4770_lcd_groups[] = {
1412  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1413  	"lcd-special", "lcd-generic",
1414  };
1415  static const char *jz4770_pwm0_groups[] = { "pwm0", };
1416  static const char *jz4770_pwm1_groups[] = { "pwm1", };
1417  static const char *jz4770_pwm2_groups[] = { "pwm2", };
1418  static const char *jz4770_pwm3_groups[] = { "pwm3", };
1419  static const char *jz4770_pwm4_groups[] = { "pwm4", };
1420  static const char *jz4770_pwm5_groups[] = { "pwm5", };
1421  static const char *jz4770_pwm6_groups[] = { "pwm6", };
1422  static const char *jz4770_pwm7_groups[] = { "pwm7", };
1423  static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1424  
1425  static const struct function_desc jz4770_functions[] = {
1426  	INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1427  	INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1428  	INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),
1429  	INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1430  	INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0),
1431  	INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1),
1432  	INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0),
1433  	INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1),
1434  	INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2),
1435  	INGENIC_PIN_FUNCTION("nemc", jz4770_nemc),
1436  	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1437  	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1438  	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1439  	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1440  	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1441  	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1442  	INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1443  	INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1444  	INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
1445  	INGENIC_PIN_FUNCTION("cim", jz4770_cim),
1446  	INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
1447  	INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
1448  	INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
1449  	INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
1450  	INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
1451  	INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
1452  	INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
1453  	INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
1454  	INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
1455  	INGENIC_PIN_FUNCTION("mac", jz4770_mac),
1456  	INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1457  };
1458  
1459  static const struct ingenic_chip_info jz4770_chip_info = {
1460  	.num_chips = 6,
1461  	.reg_offset = 0x100,
1462  	.version = ID_JZ4770,
1463  	.groups = jz4770_groups,
1464  	.num_groups = ARRAY_SIZE(jz4770_groups),
1465  	.functions = jz4770_functions,
1466  	.num_functions = ARRAY_SIZE(jz4770_functions),
1467  	.pull_ups = jz4770_pull_ups,
1468  	.pull_downs = jz4770_pull_downs,
1469  };
1470  
1471  static const u32 jz4775_pull_ups[7] = {
1472  	0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
1473  };
1474  
1475  static const u32 jz4775_pull_downs[7] = {
1476  	0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
1477  };
1478  
1479  static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
1480  static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1481  static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
1482  static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1483  static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
1484  static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
1485  static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
1486  static int jz4775_ssi_dt_a_pins[] = { 0x13, };
1487  static int jz4775_ssi_dt_d_pins[] = { 0x75, };
1488  static int jz4775_ssi_dr_a_pins[] = { 0x14, };
1489  static int jz4775_ssi_dr_d_pins[] = { 0x74, };
1490  static int jz4775_ssi_clk_a_pins[] = { 0x12, };
1491  static int jz4775_ssi_clk_d_pins[] = { 0x78, };
1492  static int jz4775_ssi_gpc_pins[] = { 0x76, };
1493  static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
1494  static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
1495  static int jz4775_ssi_ce1_pins[] = { 0x77, };
1496  static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1497  static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1498  static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
1499  static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1500  static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1501  static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1502  static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1503  static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1504  static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1505  static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1506  static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1507  static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1508  static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1509  static int jz4775_nemc_8bit_data_pins[] = {
1510  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1511  };
1512  static int jz4775_nemc_16bit_data_pins[] = {
1513  	0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
1514  };
1515  static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1516  static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1517  static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
1518  static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1519  static int jz4775_nemc_wait_pins[] = { 0x1b, };
1520  static int jz4775_nemc_cs1_pins[] = { 0x15, };
1521  static int jz4775_nemc_cs2_pins[] = { 0x16, };
1522  static int jz4775_nemc_cs3_pins[] = { 0x17, };
1523  static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
1524  static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
1525  static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
1526  static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
1527  static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
1528  static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
1529  static int jz4775_i2s_sysclk_pins[] = { 0x83, };
1530  static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
1531  static int jz4775_cim_pins[] = {
1532  	0x26, 0x27, 0x28, 0x29,
1533  	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1534  };
1535  static int jz4775_lcd_8bit_pins[] = {
1536  	0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1537  	0x48, 0x52, 0x53,
1538  };
1539  static int jz4775_lcd_16bit_pins[] = {
1540  	0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1541  };
1542  static int jz4775_lcd_18bit_pins[] = {
1543  	0x5a, 0x5b,
1544  };
1545  static int jz4775_lcd_24bit_pins[] = {
1546  	0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
1547  };
1548  static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1549  static int jz4775_lcd_generic_pins[] = { 0x49, };
1550  static int jz4775_pwm_pwm0_pins[] = { 0x80, };
1551  static int jz4775_pwm_pwm1_pins[] = { 0x81, };
1552  static int jz4775_pwm_pwm2_pins[] = { 0x82, };
1553  static int jz4775_pwm_pwm3_pins[] = { 0x83, };
1554  static int jz4775_mac_rmii_pins[] = {
1555  	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1556  };
1557  static int jz4775_mac_mii_pins[] = {
1558  	0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1559  };
1560  static int jz4775_mac_rgmii_pins[] = {
1561  	0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
1562  	0xad, 0xae, 0xa7, 0xa6,
1563  };
1564  static int jz4775_mac_gmii_pins[] = {
1565  	0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
1566  	0xa8, 0x28, 0x24, 0xaf,
1567  };
1568  static int jz4775_otg_pins[] = { 0x8a, };
1569  
1570  static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
1571  static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
1572  static u8 jz4775_mac_rgmii_funcs[] = {
1573  	0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
1574  	0, 0, 0, 0,
1575  };
1576  static u8 jz4775_mac_gmii_funcs[] = {
1577  	1, 1, 1, 1, 1, 1, 1, 1,
1578  	0, 1, 1, 0,
1579  };
1580  
1581  static const struct group_desc jz4775_groups[] = {
1582  	INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1583  	INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1584  	INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1585  	INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1586  	INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1587  	INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1588  	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1589  				jz4775_uart3_data_funcs),
1590  	INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1591  	INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1592  	INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1593  	INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1594  	INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1595  	INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1596  	INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1597  	INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1598  	INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1599  	INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1600  	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1601  	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1602  	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1603  	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1604  	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1605  	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1606  	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1607  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1608  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1609  	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1610  	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1611  	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1612  	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1613  	INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1614  	INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1615  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1616  	INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1617  	INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1618  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1619  	INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1620  	INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1621  	INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1622  	INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1623  	INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1624  	INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1625  	INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1626  	INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1627  	INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1628  	INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1629  	INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1630  	INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
1631  	INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1632  	INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1633  	INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1634  	INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1635  	INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1636  	INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1637  	INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1638  	INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
1639  	INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
1640  	INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
1641  	INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
1642  	INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1643  	INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1644  				jz4775_mac_mii_funcs),
1645  	INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1646  				jz4775_mac_rgmii_funcs),
1647  	INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1648  				jz4775_mac_gmii_funcs),
1649  	INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1650  };
1651  
1652  static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1653  static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1654  static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1655  static const char *jz4775_uart3_groups[] = { "uart3-data", };
1656  static const char *jz4775_ssi_groups[] = {
1657  	"ssi-dt-a", "ssi-dt-d",
1658  	"ssi-dr-a", "ssi-dr-d",
1659  	"ssi-clk-a", "ssi-clk-d",
1660  	"ssi-gpc",
1661  	"ssi-ce0-a", "ssi-ce0-d",
1662  	"ssi-ce1",
1663  };
1664  static const char *jz4775_mmc0_groups[] = {
1665  	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1666  	"mmc0-1bit-e", "mmc0-4bit-e",
1667  };
1668  static const char *jz4775_mmc1_groups[] = {
1669  	"mmc1-1bit-d", "mmc1-4bit-d",
1670  	"mmc1-1bit-e", "mmc1-4bit-e",
1671  };
1672  static const char *jz4775_mmc2_groups[] = {
1673  	"mmc2-1bit-b", "mmc2-4bit-b",
1674  	"mmc2-1bit-e", "mmc2-4bit-e",
1675  };
1676  static const char *jz4775_nemc_groups[] = {
1677  	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1678  	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1679  };
1680  static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1681  static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1682  static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1683  static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1684  static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1685  static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1686  static const char *jz4775_i2s_groups[] = {
1687  	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1688  };
1689  static const char *jz4775_dmic_groups[] = { "dmic", };
1690  static const char *jz4775_cim_groups[] = { "cim-data", };
1691  static const char *jz4775_lcd_groups[] = {
1692  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1693  	"lcd-special", "lcd-generic",
1694  };
1695  static const char *jz4775_pwm0_groups[] = { "pwm0", };
1696  static const char *jz4775_pwm1_groups[] = { "pwm1", };
1697  static const char *jz4775_pwm2_groups[] = { "pwm2", };
1698  static const char *jz4775_pwm3_groups[] = { "pwm3", };
1699  static const char *jz4775_mac_groups[] = {
1700  	"mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1701  };
1702  static const char *jz4775_otg_groups[] = { "otg-vbus", };
1703  
1704  static const struct function_desc jz4775_functions[] = {
1705  	INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),
1706  	INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),
1707  	INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),
1708  	INGENIC_PIN_FUNCTION("uart3", jz4775_uart3),
1709  	INGENIC_PIN_FUNCTION("ssi", jz4775_ssi),
1710  	INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0),
1711  	INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1),
1712  	INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2),
1713  	INGENIC_PIN_FUNCTION("nemc", jz4775_nemc),
1714  	INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
1715  	INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
1716  	INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
1717  	INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0),
1718  	INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1),
1719  	INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2),
1720  	INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),
1721  	INGENIC_PIN_FUNCTION("dmic", jz4775_dmic),
1722  	INGENIC_PIN_FUNCTION("cim", jz4775_cim),
1723  	INGENIC_PIN_FUNCTION("lcd", jz4775_lcd),
1724  	INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0),
1725  	INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1),
1726  	INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2),
1727  	INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3),
1728  	INGENIC_PIN_FUNCTION("mac", jz4775_mac),
1729  	INGENIC_PIN_FUNCTION("otg", jz4775_otg),
1730  };
1731  
1732  static const struct ingenic_chip_info jz4775_chip_info = {
1733  	.num_chips = 7,
1734  	.reg_offset = 0x100,
1735  	.version = ID_JZ4775,
1736  	.groups = jz4775_groups,
1737  	.num_groups = ARRAY_SIZE(jz4775_groups),
1738  	.functions = jz4775_functions,
1739  	.num_functions = ARRAY_SIZE(jz4775_functions),
1740  	.pull_ups = jz4775_pull_ups,
1741  	.pull_downs = jz4775_pull_downs,
1742  };
1743  
1744  static const u32 jz4780_pull_ups[6] = {
1745  	0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1746  };
1747  
1748  static const u32 jz4780_pull_downs[6] = {
1749  	0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1750  };
1751  
1752  static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1753  static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1754  static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
1755  static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1756  static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1757  static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1758  static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
1759  static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
1760  static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1761  static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1762  static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
1763  static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
1764  static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1765  static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1766  static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
1767  static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
1768  static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
1769  static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
1770  static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1771  static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1772  static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
1773  static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
1774  static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
1775  static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
1776  static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
1777  static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
1778  static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
1779  static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
1780  static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
1781  static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
1782  static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
1783  static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
1784  static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
1785  static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
1786  static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
1787  static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
1788  static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1789  static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1790  static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1791  static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
1792  static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1793  static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1794  static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1795  static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1796  static int jz4780_i2s_sysclk_pins[] = { 0x85, };
1797  static int jz4780_dmic_pins[] = { 0x32, 0x33, };
1798  static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
1799  
1800  static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
1801  
1802  static const struct group_desc jz4780_groups[] = {
1803  	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1804  	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1805  	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1806  	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1807  	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1808  	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1809  	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1810  				jz4760_uart3_data_funcs),
1811  	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1812  	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1813  	INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1814  	INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1815  	INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1816  	INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1817  	INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1818  	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1819  	INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1820  	INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1821  	INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1822  	INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1823  	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1824  	INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1825  	INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1826  	INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1827  	INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1828  	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1829  	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1830  	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1831  	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1832  	INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1833  	INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1834  	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1835  	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1836  	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1837  	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1838  	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1839  	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1840  	INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1841  	INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1842  	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1843  	INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1844  	INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1845  	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1846  	INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1847  	INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1848  	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1849  	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1850  	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1851  	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1852  	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1853  	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1854  	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1855  	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1856  	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1857  	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1858  	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1859  				jz4760_mmc0_1bit_a_funcs),
1860  	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1861  	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1862  	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1863  	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1864  	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1865  	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1866  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1867  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1868  	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1869  	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1870  	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1871  	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1872  	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1873  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1874  	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1875  	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1876  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1877  	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1878  	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1879  	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1880  	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1881  	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1882  	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1883  	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1884  	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1885  	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1886  	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1887  	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1888  	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1889  	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1890  	INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1891  	INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1892  	INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1893  				jz4780_i2s_clk_txrx_funcs),
1894  	INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1895  	INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1896  	INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
1897  	INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1898  	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1899  	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1900  	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1901  	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1902  	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1903  	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1904  	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1905  	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1906  	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1907  	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1908  	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1909  	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1910  	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1911  	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1912  	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1913  	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1914  };
1915  
1916  static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1917  static const char *jz4780_uart4_groups[] = { "uart4-data", };
1918  static const char *jz4780_ssi0_groups[] = {
1919  	"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1920  	"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1921  	"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1922  	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1923  	"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1924  	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1925  };
1926  static const char *jz4780_ssi1_groups[] = {
1927  	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1928  	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1929  	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1930  	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1931  	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1932  	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1933  };
1934  static const char *jz4780_mmc0_groups[] = {
1935  	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1936  	"mmc0-1bit-e", "mmc0-4bit-e",
1937  };
1938  static const char *jz4780_mmc1_groups[] = {
1939  	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1940  };
1941  static const char *jz4780_mmc2_groups[] = {
1942  	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1943  };
1944  static const char *jz4780_nemc_groups[] = {
1945  	"nemc-data", "nemc-cle-ale", "nemc-addr",
1946  	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1947  };
1948  static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1949  static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1950  static const char *jz4780_i2s_groups[] = {
1951  	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1952  };
1953  static const char *jz4780_dmic_groups[] = { "dmic", };
1954  static const char *jz4780_cim_groups[] = { "cim-data", };
1955  static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1956  
1957  static const struct function_desc jz4780_functions[] = {
1958  	INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1959  	INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1960  	INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),
1961  	INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1962  	INGENIC_PIN_FUNCTION("uart4", jz4780_uart4),
1963  	INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0),
1964  	INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1),
1965  	INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0),
1966  	INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1),
1967  	INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2),
1968  	INGENIC_PIN_FUNCTION("nemc", jz4780_nemc),
1969  	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1970  	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1971  	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1972  	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1973  	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1974  	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1975  	INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1976  	INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1977  	INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
1978  	INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3),
1979  	INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4),
1980  	INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),
1981  	INGENIC_PIN_FUNCTION("dmic", jz4780_dmic),
1982  	INGENIC_PIN_FUNCTION("cim", jz4780_cim),
1983  	INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
1984  	INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
1985  	INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
1986  	INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
1987  	INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
1988  	INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
1989  	INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
1990  	INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
1991  	INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
1992  	INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
1993  };
1994  
1995  static const struct ingenic_chip_info jz4780_chip_info = {
1996  	.num_chips = 6,
1997  	.reg_offset = 0x100,
1998  	.version = ID_JZ4780,
1999  	.groups = jz4780_groups,
2000  	.num_groups = ARRAY_SIZE(jz4780_groups),
2001  	.functions = jz4780_functions,
2002  	.num_functions = ARRAY_SIZE(jz4780_functions),
2003  	.pull_ups = jz4780_pull_ups,
2004  	.pull_downs = jz4780_pull_downs,
2005  };
2006  
2007  static const u32 x1000_pull_ups[4] = {
2008  	0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
2009  };
2010  
2011  static const u32 x1000_pull_downs[4] = {
2012  	0x00000000, 0x02000000, 0x02000000, 0x00000000,
2013  };
2014  
2015  static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
2016  static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2017  static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
2018  static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
2019  static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
2020  static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
2021  static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
2022  static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
2023  static int x1000_sfc_clk_pins[] = { 0x1a, };
2024  static int x1000_sfc_ce_pins[] = { 0x1b, };
2025  static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
2026  static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
2027  static int x1000_ssi_dt_d_pins[] = { 0x62, };
2028  static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
2029  static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
2030  static int x1000_ssi_dr_d_pins[] = { 0x63, };
2031  static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
2032  static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
2033  static int x1000_ssi_clk_d_pins[] = { 0x60, };
2034  static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
2035  static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
2036  static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
2037  static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
2038  static int x1000_ssi_ce0_d_pins[] = { 0x61, };
2039  static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
2040  static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
2041  static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
2042  static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
2043  static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
2044  static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
2045  static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
2046  static int x1000_emc_8bit_data_pins[] = {
2047  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2048  };
2049  static int x1000_emc_16bit_data_pins[] = {
2050  	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2051  };
2052  static int x1000_emc_addr_pins[] = {
2053  	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2054  	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2055  };
2056  static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
2057  static int x1000_emc_wait_pins[] = { 0x34, };
2058  static int x1000_emc_cs1_pins[] = { 0x32, };
2059  static int x1000_emc_cs2_pins[] = { 0x33, };
2060  static int x1000_i2c0_pins[] = { 0x38, 0x37, };
2061  static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
2062  static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
2063  static int x1000_i2c2_pins[] = { 0x61, 0x60, };
2064  static int x1000_i2s_data_tx_pins[] = { 0x24, };
2065  static int x1000_i2s_data_rx_pins[] = { 0x23, };
2066  static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2067  static int x1000_i2s_sysclk_pins[] = { 0x20, };
2068  static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
2069  static int x1000_dmic_if1_pins[] = { 0x25, };
2070  static int x1000_cim_pins[] = {
2071  	0x08, 0x09, 0x0a, 0x0b,
2072  	0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2073  };
2074  static int x1000_lcd_8bit_pins[] = {
2075  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2076  	0x30, 0x31, 0x32, 0x33, 0x34,
2077  };
2078  static int x1000_lcd_16bit_pins[] = {
2079  	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2080  };
2081  static int x1000_pwm_pwm0_pins[] = { 0x59, };
2082  static int x1000_pwm_pwm1_pins[] = { 0x5a, };
2083  static int x1000_pwm_pwm2_pins[] = { 0x5b, };
2084  static int x1000_pwm_pwm3_pins[] = { 0x26, };
2085  static int x1000_pwm_pwm4_pins[] = { 0x58, };
2086  static int x1000_mac_pins[] = {
2087  	0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
2088  };
2089  
2090  static const struct group_desc x1000_groups[] = {
2091  	INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2092  	INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2093  	INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2094  	INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2095  	INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2096  	INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2097  	INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2098  	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2099  	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2100  	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2101  	INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2102  	INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2103  	INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2104  	INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2105  	INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2106  	INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2107  	INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2108  	INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2109  	INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2110  	INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2111  	INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2112  	INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2113  	INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2114  	INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2115  	INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2116  	INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2117  	INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2118  	INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2119  	INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2120  	INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2121  	INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2122  	INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2123  	INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2124  	INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2125  	INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2126  	INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2127  	INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2128  	INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2129  	INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2130  	INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2131  	INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2132  	INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2133  	INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2134  	INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2135  	INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2136  	INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2137  	INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2138  	INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2139  	INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2140  	INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2141  	INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2142  	INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
2143  	INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
2144  	INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
2145  	INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2146  	INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
2147  	INGENIC_PIN_GROUP("mac", x1000_mac, 1),
2148  };
2149  
2150  static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2151  static const char *x1000_uart1_groups[] = {
2152  	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2153  };
2154  static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2155  static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2156  static const char *x1000_ssi_groups[] = {
2157  	"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2158  	"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2159  	"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2160  	"ssi-gpc-a-20", "ssi-gpc-a-31",
2161  	"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2162  	"ssi-ce1-a-21", "ssi-ce1-a-30",
2163  };
2164  static const char *x1000_mmc0_groups[] = {
2165  	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2166  };
2167  static const char *x1000_mmc1_groups[] = {
2168  	"mmc1-1bit", "mmc1-4bit",
2169  };
2170  static const char *x1000_emc_groups[] = {
2171  	"emc-8bit-data", "emc-16bit-data",
2172  	"emc-addr", "emc-rd-we", "emc-wait",
2173  };
2174  static const char *x1000_cs1_groups[] = { "emc-cs1", };
2175  static const char *x1000_cs2_groups[] = { "emc-cs2", };
2176  static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2177  static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2178  static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2179  static const char *x1000_i2s_groups[] = {
2180  	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2181  };
2182  static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2183  static const char *x1000_cim_groups[] = { "cim-data", };
2184  static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2185  static const char *x1000_pwm0_groups[] = { "pwm0", };
2186  static const char *x1000_pwm1_groups[] = { "pwm1", };
2187  static const char *x1000_pwm2_groups[] = { "pwm2", };
2188  static const char *x1000_pwm3_groups[] = { "pwm3", };
2189  static const char *x1000_pwm4_groups[] = { "pwm4", };
2190  static const char *x1000_mac_groups[] = { "mac", };
2191  
2192  static const struct function_desc x1000_functions[] = {
2193  	INGENIC_PIN_FUNCTION("uart0", x1000_uart0),
2194  	INGENIC_PIN_FUNCTION("uart1", x1000_uart1),
2195  	INGENIC_PIN_FUNCTION("uart2", x1000_uart2),
2196  	INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2197  	INGENIC_PIN_FUNCTION("ssi", x1000_ssi),
2198  	INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0),
2199  	INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1),
2200  	INGENIC_PIN_FUNCTION("emc", x1000_emc),
2201  	INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
2202  	INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
2203  	INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0),
2204  	INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1),
2205  	INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2),
2206  	INGENIC_PIN_FUNCTION("i2s", x1000_i2s),
2207  	INGENIC_PIN_FUNCTION("dmic", x1000_dmic),
2208  	INGENIC_PIN_FUNCTION("cim", x1000_cim),
2209  	INGENIC_PIN_FUNCTION("lcd", x1000_lcd),
2210  	INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0),
2211  	INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1),
2212  	INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2),
2213  	INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3),
2214  	INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4),
2215  	INGENIC_PIN_FUNCTION("mac", x1000_mac),
2216  };
2217  
2218  static const struct regmap_range x1000_access_ranges[] = {
2219  	regmap_reg_range(0x000, 0x400 - 4),
2220  	regmap_reg_range(0x700, 0x800 - 4),
2221  };
2222  
2223  /* shared with X1500 */
2224  static const struct regmap_access_table x1000_access_table = {
2225  	.yes_ranges = x1000_access_ranges,
2226  	.n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
2227  };
2228  
2229  static const struct ingenic_chip_info x1000_chip_info = {
2230  	.num_chips = 4,
2231  	.reg_offset = 0x100,
2232  	.version = ID_X1000,
2233  	.groups = x1000_groups,
2234  	.num_groups = ARRAY_SIZE(x1000_groups),
2235  	.functions = x1000_functions,
2236  	.num_functions = ARRAY_SIZE(x1000_functions),
2237  	.pull_ups = x1000_pull_ups,
2238  	.pull_downs = x1000_pull_downs,
2239  	.access_table = &x1000_access_table,
2240  };
2241  
2242  static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
2243  static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2244  static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
2245  static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
2246  static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
2247  static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
2248  static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
2249  static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
2250  static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
2251  static int x1500_i2c0_pins[] = { 0x38, 0x37, };
2252  static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
2253  static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
2254  static int x1500_i2c2_pins[] = { 0x61, 0x60, };
2255  static int x1500_i2s_data_tx_pins[] = { 0x24, };
2256  static int x1500_i2s_data_rx_pins[] = { 0x23, };
2257  static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2258  static int x1500_i2s_sysclk_pins[] = { 0x20, };
2259  static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
2260  static int x1500_dmic_if1_pins[] = { 0x25, };
2261  static int x1500_cim_pins[] = {
2262  	0x08, 0x09, 0x0a, 0x0b,
2263  	0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2264  };
2265  static int x1500_pwm_pwm0_pins[] = { 0x59, };
2266  static int x1500_pwm_pwm1_pins[] = { 0x5a, };
2267  static int x1500_pwm_pwm2_pins[] = { 0x5b, };
2268  static int x1500_pwm_pwm3_pins[] = { 0x26, };
2269  static int x1500_pwm_pwm4_pins[] = { 0x58, };
2270  
2271  static const struct group_desc x1500_groups[] = {
2272  	INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2273  	INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2274  	INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2275  	INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2276  	INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2277  	INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2278  	INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2279  	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2280  	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2281  	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2282  	INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2283  	INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2284  	INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2285  	INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2286  	INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2287  	INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2288  	INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2289  	INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2290  	INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2291  	INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2292  	INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2293  	INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2294  	INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2295  	INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
2296  	INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
2297  	INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
2298  	INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2299  	INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
2300  };
2301  
2302  static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2303  static const char *x1500_uart1_groups[] = {
2304  	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2305  };
2306  static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2307  static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2308  static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2309  static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2310  static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2311  static const char *x1500_i2s_groups[] = {
2312  	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2313  };
2314  static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2315  static const char *x1500_cim_groups[] = { "cim-data", };
2316  static const char *x1500_pwm0_groups[] = { "pwm0", };
2317  static const char *x1500_pwm1_groups[] = { "pwm1", };
2318  static const char *x1500_pwm2_groups[] = { "pwm2", };
2319  static const char *x1500_pwm3_groups[] = { "pwm3", };
2320  static const char *x1500_pwm4_groups[] = { "pwm4", };
2321  
2322  static const struct function_desc x1500_functions[] = {
2323  	INGENIC_PIN_FUNCTION("uart0", x1500_uart0),
2324  	INGENIC_PIN_FUNCTION("uart1", x1500_uart1),
2325  	INGENIC_PIN_FUNCTION("uart2", x1500_uart2),
2326  	INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2327  	INGENIC_PIN_FUNCTION("mmc", x1500_mmc),
2328  	INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0),
2329  	INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1),
2330  	INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2),
2331  	INGENIC_PIN_FUNCTION("i2s", x1500_i2s),
2332  	INGENIC_PIN_FUNCTION("dmic", x1500_dmic),
2333  	INGENIC_PIN_FUNCTION("cim", x1500_cim),
2334  	INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0),
2335  	INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1),
2336  	INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2),
2337  	INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3),
2338  	INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4),
2339  };
2340  
2341  static const struct ingenic_chip_info x1500_chip_info = {
2342  	.num_chips = 4,
2343  	.reg_offset = 0x100,
2344  	.version = ID_X1500,
2345  	.groups = x1500_groups,
2346  	.num_groups = ARRAY_SIZE(x1500_groups),
2347  	.functions = x1500_functions,
2348  	.num_functions = ARRAY_SIZE(x1500_functions),
2349  	.pull_ups = x1000_pull_ups,
2350  	.pull_downs = x1000_pull_downs,
2351  	.access_table = &x1000_access_table,
2352  };
2353  
2354  static const u32 x1830_pull_ups[4] = {
2355  	0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2356  };
2357  
2358  static const u32 x1830_pull_downs[4] = {
2359  	0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2360  };
2361  
2362  static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
2363  static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
2364  static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
2365  static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
2366  static int x1830_sfc_clk_pins[] = { 0x1b, };
2367  static int x1830_sfc_ce_pins[] = { 0x1c, };
2368  static int x1830_ssi0_dt_pins[] = { 0x4c, };
2369  static int x1830_ssi0_dr_pins[] = { 0x4b, };
2370  static int x1830_ssi0_clk_pins[] = { 0x4f, };
2371  static int x1830_ssi0_gpc_pins[] = { 0x4d, };
2372  static int x1830_ssi0_ce0_pins[] = { 0x50, };
2373  static int x1830_ssi0_ce1_pins[] = { 0x4e, };
2374  static int x1830_ssi1_dt_c_pins[] = { 0x53, };
2375  static int x1830_ssi1_dt_d_pins[] = { 0x62, };
2376  static int x1830_ssi1_dr_c_pins[] = { 0x54, };
2377  static int x1830_ssi1_dr_d_pins[] = { 0x63, };
2378  static int x1830_ssi1_clk_c_pins[] = { 0x57, };
2379  static int x1830_ssi1_clk_d_pins[] = { 0x66, };
2380  static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
2381  static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
2382  static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
2383  static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
2384  static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
2385  static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
2386  static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
2387  static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
2388  static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
2389  static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
2390  static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
2391  static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
2392  static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
2393  static int x1830_i2s_data_tx_pins[] = { 0x53, };
2394  static int x1830_i2s_data_rx_pins[] = { 0x54, };
2395  static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
2396  static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
2397  static int x1830_i2s_sysclk_pins[] = { 0x57, };
2398  static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
2399  static int x1830_dmic_if1_pins[] = { 0x5a, };
2400  static int x1830_lcd_tft_8bit_pins[] = {
2401  	0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
2402  	0x68, 0x73, 0x72, 0x69,
2403  };
2404  static int x1830_lcd_tft_24bit_pins[] = {
2405  	0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
2406  	0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
2407  };
2408  static int x1830_lcd_slcd_8bit_pins[] = {
2409  	0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
2410  	0x69, 0x72, 0x73, 0x7b, 0x7a,
2411  };
2412  static int x1830_lcd_slcd_16bit_pins[] = {
2413  	0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
2414  };
2415  static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
2416  static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
2417  static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
2418  static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
2419  static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
2420  static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
2421  static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
2422  static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
2423  static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
2424  static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
2425  static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
2426  static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
2427  static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
2428  static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
2429  static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
2430  static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
2431  static int x1830_mac_pins[] = {
2432  	0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
2433  };
2434  
2435  static const struct group_desc x1830_groups[] = {
2436  	INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2437  	INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2438  	INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2439  	INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2440  	INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2441  	INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2442  	INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2443  	INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2444  	INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2445  	INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2446  	INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2447  	INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2448  	INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2449  	INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2450  	INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2451  	INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2452  	INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2453  	INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2454  	INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2455  	INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2456  	INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2457  	INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2458  	INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2459  	INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2460  	INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2461  	INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2462  	INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2463  	INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2464  	INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2465  	INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2466  	INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2467  	INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2468  	INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2469  	INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2470  	INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2471  	INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2472  	INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2473  	INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2474  	INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2475  	INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2476  	INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2477  	INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2478  	INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2479  	INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2480  	INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2481  	INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2482  	INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2483  	INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2484  	INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2485  	INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2486  	INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2487  	INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2488  	INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2489  	INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2490  	INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2491  	INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2492  	INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2493  	INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2494  	INGENIC_PIN_GROUP("mac", x1830_mac, 0),
2495  };
2496  
2497  static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2498  static const char *x1830_uart1_groups[] = { "uart1-data", };
2499  static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2500  static const char *x1830_ssi0_groups[] = {
2501  	"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2502  };
2503  static const char *x1830_ssi1_groups[] = {
2504  	"ssi1-dt-c", "ssi1-dt-d",
2505  	"ssi1-dr-c", "ssi1-dr-d",
2506  	"ssi1-clk-c", "ssi1-clk-d",
2507  	"ssi1-gpc-c", "ssi1-gpc-d",
2508  	"ssi1-ce0-c", "ssi1-ce0-d",
2509  	"ssi1-ce1-c", "ssi1-ce1-d",
2510  };
2511  static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2512  static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2513  static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2514  static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2515  static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2516  static const char *x1830_i2s_groups[] = {
2517  	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2518  };
2519  static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2520  static const char *x1830_lcd_groups[] = {
2521  	"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2522  };
2523  static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2524  static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2525  static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2526  static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2527  static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2528  static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2529  static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2530  static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2531  static const char *x1830_mac_groups[] = { "mac", };
2532  
2533  static const struct function_desc x1830_functions[] = {
2534  	INGENIC_PIN_FUNCTION("uart0", x1830_uart0),
2535  	INGENIC_PIN_FUNCTION("uart1", x1830_uart1),
2536  	INGENIC_PIN_FUNCTION("sfc", x1830_sfc),
2537  	INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0),
2538  	INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1),
2539  	INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0),
2540  	INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1),
2541  	INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0),
2542  	INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1),
2543  	INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2),
2544  	INGENIC_PIN_FUNCTION("i2s", x1830_i2s),
2545  	INGENIC_PIN_FUNCTION("dmic", x1830_dmic),
2546  	INGENIC_PIN_FUNCTION("lcd", x1830_lcd),
2547  	INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0),
2548  	INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1),
2549  	INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2),
2550  	INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3),
2551  	INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4),
2552  	INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5),
2553  	INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6),
2554  	INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7),
2555  	INGENIC_PIN_FUNCTION("mac", x1830_mac),
2556  };
2557  
2558  static const struct regmap_range x1830_access_ranges[] = {
2559  	regmap_reg_range(0x0000, 0x4000 - 4),
2560  	regmap_reg_range(0x7000, 0x8000 - 4),
2561  };
2562  
2563  static const struct regmap_access_table x1830_access_table = {
2564  	.yes_ranges = x1830_access_ranges,
2565  	.n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
2566  };
2567  
2568  static const struct ingenic_chip_info x1830_chip_info = {
2569  	.num_chips = 4,
2570  	.reg_offset = 0x1000,
2571  	.version = ID_X1830,
2572  	.groups = x1830_groups,
2573  	.num_groups = ARRAY_SIZE(x1830_groups),
2574  	.functions = x1830_functions,
2575  	.num_functions = ARRAY_SIZE(x1830_functions),
2576  	.pull_ups = x1830_pull_ups,
2577  	.pull_downs = x1830_pull_downs,
2578  	.access_table = &x1830_access_table,
2579  };
2580  
2581  static const u32 x2000_pull_ups[5] = {
2582  	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
2583  };
2584  
2585  static const u32 x2000_pull_downs[5] = {
2586  	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
2587  };
2588  
2589  static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
2590  static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
2591  static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
2592  static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
2593  static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
2594  static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
2595  static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
2596  static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
2597  static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
2598  static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
2599  static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
2600  static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
2601  static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
2602  static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
2603  static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
2604  static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
2605  static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
2606  static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
2607  static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
2608  static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
2609  static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
2610  static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
2611  static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
2612  static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2613  static int x2000_sfc_clk_d_pins[] = { 0x71, };
2614  static int x2000_sfc_clk_e_pins[] = { 0x90, };
2615  static int x2000_sfc_ce_d_pins[] = { 0x72, };
2616  static int x2000_sfc_ce_e_pins[] = { 0x91, };
2617  static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
2618  static int x2000_ssi0_dt_d_pins[] = { 0x69, };
2619  static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
2620  static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
2621  static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
2622  static int x2000_ssi0_clk_d_pins[] = { 0x68, };
2623  static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
2624  static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
2625  static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
2626  static int x2000_ssi1_dt_d_pins[] = { 0x72, };
2627  static int x2000_ssi1_dt_e_pins[] = { 0x91, };
2628  static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
2629  static int x2000_ssi1_dr_d_pins[] = { 0x73, };
2630  static int x2000_ssi1_dr_e_pins[] = { 0x92, };
2631  static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
2632  static int x2000_ssi1_clk_d_pins[] = { 0x71, };
2633  static int x2000_ssi1_clk_e_pins[] = { 0x90, };
2634  static int x2000_ssi1_ce_c_pins[] = { 0x49, };
2635  static int x2000_ssi1_ce_d_pins[] = { 0x76, };
2636  static int x2000_ssi1_ce_e_pins[] = { 0x95, };
2637  static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
2638  static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
2639  static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2640  static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
2641  static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
2642  static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
2643  static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
2644  static int x2000_emc_8bit_data_pins[] = {
2645  	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2646  };
2647  static int x2000_emc_16bit_data_pins[] = {
2648  	0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
2649  };
2650  static int x2000_emc_addr_pins[] = {
2651  	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2652  	0x28, 0x29, 0x2a, 0x2b, 0x2c,
2653  };
2654  static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
2655  static int x2000_emc_wait_pins[] = { 0x2f, };
2656  static int x2000_emc_cs1_pins[] = { 0x57, };
2657  static int x2000_emc_cs2_pins[] = { 0x58, };
2658  static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
2659  static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
2660  static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
2661  static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
2662  static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
2663  static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
2664  static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
2665  static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
2666  static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
2667  static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
2668  static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
2669  static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
2670  static int x2000_i2s1_data_tx_pins[] = { 0x47, };
2671  static int x2000_i2s1_data_rx_pins[] = { 0x44, };
2672  static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
2673  static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
2674  static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
2675  static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
2676  static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
2677  static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
2678  static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
2679  static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
2680  static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
2681  static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
2682  static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
2683  static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
2684  static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
2685  static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
2686  static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
2687  static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
2688  static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
2689  static int x2000_dmic_if1_pins[] = { 0x56, };
2690  static int x2000_dmic_if2_pins[] = { 0x57, };
2691  static int x2000_dmic_if3_pins[] = { 0x58, };
2692  static int x2000_cim_8bit_pins[] = {
2693  	0x0e, 0x0c, 0x0d, 0x4f,
2694  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2695  };
2696  static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
2697  static int x2000_lcd_tft_8bit_pins[] = {
2698  	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2699  	0x38, 0x3a, 0x39, 0x3b,
2700  };
2701  static int x2000_lcd_tft_16bit_pins[] = {
2702  	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2703  };
2704  static int x2000_lcd_tft_18bit_pins[] = {
2705  	0x30, 0x31,
2706  };
2707  static int x2000_lcd_tft_24bit_pins[] = {
2708  	0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2709  };
2710  static int x2000_lcd_slcd_8bit_pins[] = {
2711  	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2712  	0x3a, 0x38, 0x3b, 0x30, 0x39,
2713  };
2714  static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
2715  static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
2716  static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
2717  static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
2718  static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
2719  static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
2720  static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
2721  static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
2722  static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
2723  static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
2724  static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
2725  static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
2726  static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
2727  static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
2728  static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
2729  static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
2730  static int x2000_pwm_pwm8_pins[] = { 0x48, };
2731  static int x2000_pwm_pwm9_pins[] = { 0x49, };
2732  static int x2000_pwm_pwm10_pins[] = { 0x4a, };
2733  static int x2000_pwm_pwm11_pins[] = { 0x4b, };
2734  static int x2000_pwm_pwm12_pins[] = { 0x4c, };
2735  static int x2000_pwm_pwm13_pins[] = { 0x4d, };
2736  static int x2000_pwm_pwm14_pins[] = { 0x4e, };
2737  static int x2000_pwm_pwm15_pins[] = { 0x4f, };
2738  static int x2000_mac0_rmii_pins[] = {
2739  	0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
2740  };
2741  static int x2000_mac0_rgmii_pins[] = {
2742  	0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
2743  	0x4c, 0x4d, 0x4f, 0x4e, 0x41,
2744  };
2745  static int x2000_mac1_rmii_pins[] = {
2746  	0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
2747  };
2748  static int x2000_mac1_rgmii_pins[] = {
2749  	0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
2750  	0x33, 0x34, 0x36, 0x35, 0x37,
2751  };
2752  static int x2000_otg_pins[] = { 0x96, };
2753  
2754  static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
2755  
2756  static const struct group_desc x2000_groups[] = {
2757  	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2758  	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2759  	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2760  	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2761  	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2762  	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2763  	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2764  	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2765  	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2766  	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2767  	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2768  	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2769  	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2770  	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2771  	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2772  	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2773  	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2774  	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2775  	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2776  	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2777  	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2778  	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2779  	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2780  	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2781  	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2782  	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2783  	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2784  	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2785  	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2786  	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2787  	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2788  	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2789  	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2790  	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2791  	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2792  	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2793  	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2794  	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2795  	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2796  	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2797  	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2798  	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2799  	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2800  	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2801  	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2802  	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2803  	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2804  	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2805  	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2806  	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2807  	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2808  	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2809  	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2810  	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2811  	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2812  	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2813  	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2814  	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2815  	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2816  	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2817  	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2818  	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2819  	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2820  	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2821  	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2822  	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2823  	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2824  	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2825  	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2826  	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2827  	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2828  	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2829  	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2830  	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2831  	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2832  	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2833  	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2834  	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2835  	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2836  	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2837  	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2838  	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2839  	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2840  	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2841  	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2842  	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2843  	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2844  	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2845  	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2846  	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2847  	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2848  	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2849  	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2850  	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2851  	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2852  	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2853  	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2854  				x2000_cim_8bit_funcs),
2855  	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2856  	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2857  	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2858  	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2859  	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2860  	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2861  	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2862  	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2863  	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2864  	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2865  	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2866  	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2867  	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2868  	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2869  	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2870  	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2871  	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2872  	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2873  	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2874  	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2875  	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2876  	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2877  	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2878  	INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
2879  	INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
2880  	INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
2881  	INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
2882  	INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
2883  	INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
2884  	INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
2885  	INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
2886  	INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2887  	INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2888  	INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2889  	INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2890  	INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2891  };
2892  
2893  static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2894  static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2895  static const char *x2000_uart2_groups[] = { "uart2-data", };
2896  static const char *x2000_uart3_groups[] = {
2897  	"uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2898  };
2899  static const char *x2000_uart4_groups[] = {
2900  	"uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2901  };
2902  static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2903  static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2904  static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2905  static const char *x2000_uart8_groups[] = { "uart8-data", };
2906  static const char *x2000_uart9_groups[] = { "uart9-data", };
2907  static const char *x2000_sfc_groups[] = {
2908  	"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2909  	"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2910  };
2911  static const char *x2000_ssi0_groups[] = {
2912  	"ssi0-dt-b", "ssi0-dt-d",
2913  	"ssi0-dr-b", "ssi0-dr-d",
2914  	"ssi0-clk-b", "ssi0-clk-d",
2915  	"ssi0-ce-b", "ssi0-ce-d",
2916  };
2917  static const char *x2000_ssi1_groups[] = {
2918  	"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2919  	"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2920  	"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2921  	"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2922  };
2923  static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2924  static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2925  static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2926  static const char *x2000_emc_groups[] = {
2927  	"emc-8bit-data", "emc-16bit-data",
2928  	"emc-addr", "emc-rd-we", "emc-wait",
2929  };
2930  static const char *x2000_cs1_groups[] = { "emc-cs1", };
2931  static const char *x2000_cs2_groups[] = { "emc-cs2", };
2932  static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2933  static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2934  static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2935  static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2936  static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2937  static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2938  static const char *x2000_i2s1_groups[] = {
2939  	"i2s1-data-tx", "i2s1-data-rx",
2940  	"i2s1-clk-tx", "i2s1-clk-rx",
2941  	"i2s1-sysclk-tx", "i2s1-sysclk-rx",
2942  };
2943  static const char *x2000_i2s2_groups[] = {
2944  	"i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2945  	"i2s2-clk-rx", "i2s2-sysclk-rx",
2946  };
2947  static const char *x2000_i2s3_groups[] = {
2948  	"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2949  	"i2s3-clk-tx", "i2s3-sysclk-tx",
2950  };
2951  static const char *x2000_dmic_groups[] = {
2952  	"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2953  };
2954  static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2955  static const char *x2000_lcd_groups[] = {
2956  	"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2957  	"lcd-slcd-8bit", "lcd-slcd-16bit",
2958  };
2959  static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2960  static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2961  static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2962  static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2963  static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2964  static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2965  static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2966  static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2967  static const char *x2000_pwm8_groups[] = { "pwm8", };
2968  static const char *x2000_pwm9_groups[] = { "pwm9", };
2969  static const char *x2000_pwm10_groups[] = { "pwm10", };
2970  static const char *x2000_pwm11_groups[] = { "pwm11", };
2971  static const char *x2000_pwm12_groups[] = { "pwm12", };
2972  static const char *x2000_pwm13_groups[] = { "pwm13", };
2973  static const char *x2000_pwm14_groups[] = { "pwm14", };
2974  static const char *x2000_pwm15_groups[] = { "pwm15", };
2975  static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2976  static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2977  static const char *x2000_otg_groups[] = { "otg-vbus", };
2978  
2979  static const struct function_desc x2000_functions[] = {
2980  	INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
2981  	INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
2982  	INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
2983  	INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
2984  	INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
2985  	INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
2986  	INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
2987  	INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
2988  	INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
2989  	INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
2990  	INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
2991  	INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
2992  	INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
2993  	INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
2994  	INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
2995  	INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
2996  	INGENIC_PIN_FUNCTION("emc", x2000_emc),
2997  	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
2998  	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
2999  	INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
3000  	INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
3001  	INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
3002  	INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
3003  	INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
3004  	INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3005  	INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3006  	INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3007  	INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3008  	INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3009  	INGENIC_PIN_FUNCTION("cim", x2000_cim),
3010  	INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3011  	INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3012  	INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3013  	INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3014  	INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3015  	INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3016  	INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3017  	INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3018  	INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3019  	INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3020  	INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3021  	INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3022  	INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3023  	INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3024  	INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3025  	INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3026  	INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3027  	INGENIC_PIN_FUNCTION("mac0", x2000_mac0),
3028  	INGENIC_PIN_FUNCTION("mac1", x2000_mac1),
3029  	INGENIC_PIN_FUNCTION("otg", x2000_otg),
3030  };
3031  
3032  static const struct regmap_range x2000_access_ranges[] = {
3033  	regmap_reg_range(0x000, 0x500 - 4),
3034  	regmap_reg_range(0x700, 0x800 - 4),
3035  };
3036  
3037  /* shared with X2100 */
3038  static const struct regmap_access_table x2000_access_table = {
3039  	.yes_ranges = x2000_access_ranges,
3040  	.n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
3041  };
3042  
3043  static const struct ingenic_chip_info x2000_chip_info = {
3044  	.num_chips = 5,
3045  	.reg_offset = 0x100,
3046  	.version = ID_X2000,
3047  	.groups = x2000_groups,
3048  	.num_groups = ARRAY_SIZE(x2000_groups),
3049  	.functions = x2000_functions,
3050  	.num_functions = ARRAY_SIZE(x2000_functions),
3051  	.pull_ups = x2000_pull_ups,
3052  	.pull_downs = x2000_pull_downs,
3053  	.access_table = &x2000_access_table,
3054  };
3055  
3056  static const u32 x2100_pull_ups[5] = {
3057  	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
3058  };
3059  
3060  static const u32 x2100_pull_downs[5] = {
3061  	0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
3062  };
3063  
3064  static int x2100_mac_pins[] = {
3065  	0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
3066  };
3067  
3068  static const struct group_desc x2100_groups[] = {
3069  	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3070  	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3071  	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3072  	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3073  	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3074  	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3075  	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3076  	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3077  	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3078  	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3079  	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3080  	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3081  	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3082  	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3083  	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3084  	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3085  	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3086  	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3087  	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3088  	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3089  	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3090  	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3091  	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3092  	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3093  	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3094  	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3095  	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3096  	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3097  	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3098  	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3099  	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3100  	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3101  	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3102  	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3103  	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3104  	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3105  	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3106  	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3107  	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3108  	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3109  	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3110  	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3111  	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3112  	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3113  	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3114  	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3115  	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3116  	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3117  	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3118  	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3119  	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3120  	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3121  	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3122  	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3123  	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3124  	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3125  	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3126  	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3127  	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3128  	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3129  	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3130  	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3131  	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3132  	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3133  	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3134  	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3135  	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3136  	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3137  	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3138  	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3139  	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3140  	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3141  	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3142  	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3143  	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3144  	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3145  	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3146  	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3147  	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3148  	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3149  	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3150  	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3151  	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3152  	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3153  	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3154  	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3155  	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3156  	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3157  	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3158  	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3159  	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3160  	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3161  	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3162  	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3163  	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3164  	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3165  	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3166  				x2000_cim_8bit_funcs),
3167  	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3168  	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3169  	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3170  	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3171  	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3172  	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3173  	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3174  	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3175  	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3176  	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3177  	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3178  	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3179  	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3180  	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3181  	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3182  	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3183  	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3184  	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3185  	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3186  	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3187  	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3188  	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3189  	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3190  	INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3191  	INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3192  	INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3193  	INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3194  	INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3195  	INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3196  	INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3197  	INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3198  	INGENIC_PIN_GROUP("mac", x2100_mac, 1),
3199  };
3200  
3201  static const char *x2100_mac_groups[] = { "mac", };
3202  
3203  static const struct function_desc x2100_functions[] = {
3204  	INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3205  	INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3206  	INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
3207  	INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
3208  	INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
3209  	INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
3210  	INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
3211  	INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
3212  	INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
3213  	INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
3214  	INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
3215  	INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
3216  	INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
3217  	INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
3218  	INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
3219  	INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
3220  	INGENIC_PIN_FUNCTION("emc", x2000_emc),
3221  	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3222  	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3223  	INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
3224  	INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
3225  	INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
3226  	INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
3227  	INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
3228  	INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3229  	INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3230  	INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3231  	INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3232  	INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3233  	INGENIC_PIN_FUNCTION("cim", x2000_cim),
3234  	INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3235  	INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3236  	INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3237  	INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3238  	INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3239  	INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3240  	INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3241  	INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3242  	INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3243  	INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3244  	INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3245  	INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3246  	INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3247  	INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3248  	INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3249  	INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3250  	INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3251  	INGENIC_PIN_FUNCTION("mac", x2100_mac),
3252  };
3253  
3254  static const struct ingenic_chip_info x2100_chip_info = {
3255  	.num_chips = 5,
3256  	.reg_offset = 0x100,
3257  	.version = ID_X2100,
3258  	.groups = x2100_groups,
3259  	.num_groups = ARRAY_SIZE(x2100_groups),
3260  	.functions = x2100_functions,
3261  	.num_functions = ARRAY_SIZE(x2100_functions),
3262  	.pull_ups = x2100_pull_ups,
3263  	.pull_downs = x2100_pull_downs,
3264  	.access_table = &x2000_access_table,
3265  };
3266  
ingenic_gpio_read_reg(struct ingenic_gpio_chip * jzgc,u8 reg)3267  static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3268  {
3269  	unsigned int val;
3270  
3271  	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3272  
3273  	return (u32) val;
3274  }
3275  
ingenic_gpio_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3276  static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3277  		u8 reg, u8 offset, bool set)
3278  {
3279  	if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3280  		regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3281  				BIT(offset), set ? BIT(offset) : 0);
3282  		return;
3283  	}
3284  
3285  	if (set)
3286  		reg = REG_SET(reg);
3287  	else
3288  		reg = REG_CLEAR(reg);
3289  
3290  	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3291  }
3292  
ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3293  static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3294  		u8 reg, u8 offset, bool set)
3295  {
3296  	if (set)
3297  		reg = REG_SET(reg);
3298  	else
3299  		reg = REG_CLEAR(reg);
3300  
3301  	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3302  			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3303  }
3304  
ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip * jzgc)3305  static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3306  {
3307  	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3308  			jzgc->jzpc->info->reg_offset),
3309  			jzgc->gc.base / PINS_PER_GPIO_CHIP);
3310  }
3311  
jz4730_gpio_set_bits(struct ingenic_gpio_chip * jzgc,u8 reg_upper,u8 reg_lower,u8 offset,u8 value)3312  static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3313  		u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
3314  {
3315  	/*
3316  	 * JZ4730 function and IRQ registers support two-bits-per-pin
3317  	 * definitions, split into two groups of 16.
3318  	 */
3319  	u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3320  	unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
3321  	unsigned int mask = GENMASK(1, 0) << idx * 2;
3322  
3323  	regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3324  }
3325  
ingenic_gpio_get_value(struct ingenic_gpio_chip * jzgc,u8 offset)3326  static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3327  					  u8 offset)
3328  {
3329  	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3330  
3331  	return !!(val & BIT(offset));
3332  }
3333  
ingenic_gpio_set_value(struct ingenic_gpio_chip * jzgc,u8 offset,int value)3334  static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3335  				   u8 offset, int value)
3336  {
3337  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3338  		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3339  	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3340  		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3341  	else
3342  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3343  }
3344  
irq_set_type(struct ingenic_gpio_chip * jzgc,u8 offset,unsigned int type)3345  static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3346  		u8 offset, unsigned int type)
3347  {
3348  	u8 reg1, reg2;
3349  	bool val1, val2, val3;
3350  
3351  	switch (type) {
3352  	case IRQ_TYPE_EDGE_BOTH:
3353  		val1 = val2 = false;
3354  		val3 = true;
3355  		break;
3356  	case IRQ_TYPE_EDGE_RISING:
3357  		val1 = val2 = true;
3358  		val3 = false;
3359  		break;
3360  	case IRQ_TYPE_EDGE_FALLING:
3361  		val1 = val3 = false;
3362  		val2 = true;
3363  		break;
3364  	case IRQ_TYPE_LEVEL_HIGH:
3365  		val1 = true;
3366  		val2 = val3 = false;
3367  		break;
3368  	case IRQ_TYPE_LEVEL_LOW:
3369  	default:
3370  		val1 = val2 = val3 = false;
3371  		break;
3372  	}
3373  
3374  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
3375  		reg1 = JZ4770_GPIO_PAT1;
3376  		reg2 = JZ4770_GPIO_PAT0;
3377  	} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3378  		reg1 = JZ4740_GPIO_TRIG;
3379  		reg2 = JZ4740_GPIO_DIR;
3380  	} else {
3381  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3382  		jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3383  				JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
3384  		return;
3385  	}
3386  
3387  	if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3388  		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3389  		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3390  		ingenic_gpio_shadow_set_bit_load(jzgc);
3391  		ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3392  	} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
3393  		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3394  		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3395  		ingenic_gpio_shadow_set_bit_load(jzgc);
3396  	} else {
3397  		ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3398  		ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3399  	}
3400  }
3401  
ingenic_gpio_irq_mask(struct irq_data * irqd)3402  static void ingenic_gpio_irq_mask(struct irq_data *irqd)
3403  {
3404  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3405  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3406  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3407  
3408  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3409  		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3410  	else
3411  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3412  }
3413  
ingenic_gpio_irq_unmask(struct irq_data * irqd)3414  static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
3415  {
3416  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3417  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3418  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3419  
3420  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3421  		ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3422  	else
3423  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3424  }
3425  
ingenic_gpio_irq_enable(struct irq_data * irqd)3426  static void ingenic_gpio_irq_enable(struct irq_data *irqd)
3427  {
3428  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3429  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3430  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3431  
3432  	gpiochip_enable_irq(gc, irq);
3433  
3434  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3435  		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3436  	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3437  		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3438  	else
3439  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3440  
3441  	ingenic_gpio_irq_unmask(irqd);
3442  }
3443  
ingenic_gpio_irq_disable(struct irq_data * irqd)3444  static void ingenic_gpio_irq_disable(struct irq_data *irqd)
3445  {
3446  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3447  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3448  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3449  
3450  	ingenic_gpio_irq_mask(irqd);
3451  
3452  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3453  		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3454  	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3455  		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3456  	else
3457  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3458  
3459  	gpiochip_disable_irq(gc, irq);
3460  }
3461  
ingenic_gpio_irq_ack(struct irq_data * irqd)3462  static void ingenic_gpio_irq_ack(struct irq_data *irqd)
3463  {
3464  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3465  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3466  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3467  	bool high;
3468  
3469  	if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
3470  	    !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3471  		/*
3472  		 * Switch to an interrupt for the opposite edge to the one that
3473  		 * triggered the interrupt being ACKed.
3474  		 */
3475  		high = ingenic_gpio_get_value(jzgc, irq);
3476  		if (high)
3477  			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3478  		else
3479  			irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3480  	}
3481  
3482  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3483  		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3484  	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3485  		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3486  	else
3487  		ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3488  }
3489  
ingenic_gpio_irq_set_type(struct irq_data * irqd,unsigned int type)3490  static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
3491  {
3492  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3493  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3494  	irq_hw_number_t irq = irqd_to_hwirq(irqd);
3495  
3496  	switch (type) {
3497  	case IRQ_TYPE_EDGE_BOTH:
3498  	case IRQ_TYPE_EDGE_RISING:
3499  	case IRQ_TYPE_EDGE_FALLING:
3500  		irq_set_handler_locked(irqd, handle_edge_irq);
3501  		break;
3502  	case IRQ_TYPE_LEVEL_HIGH:
3503  	case IRQ_TYPE_LEVEL_LOW:
3504  		irq_set_handler_locked(irqd, handle_level_irq);
3505  		break;
3506  	default:
3507  		irq_set_handler_locked(irqd, handle_bad_irq);
3508  	}
3509  
3510  	if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3511  		/*
3512  		 * The hardware does not support interrupts on both edges. The
3513  		 * best we can do is to set up a single-edge interrupt and then
3514  		 * switch to the opposing edge when ACKing the interrupt.
3515  		 */
3516  		bool high = ingenic_gpio_get_value(jzgc, irq);
3517  
3518  		type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
3519  	}
3520  
3521  	irq_set_type(jzgc, irq, type);
3522  	return 0;
3523  }
3524  
ingenic_gpio_irq_set_wake(struct irq_data * irqd,unsigned int on)3525  static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
3526  {
3527  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3528  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3529  
3530  	return irq_set_irq_wake(jzgc->irq, on);
3531  }
3532  
ingenic_gpio_irq_handler(struct irq_desc * desc)3533  static void ingenic_gpio_irq_handler(struct irq_desc *desc)
3534  {
3535  	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3536  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3537  	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
3538  	unsigned long flag, i;
3539  
3540  	chained_irq_enter(irq_chip, desc);
3541  
3542  	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3543  		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3544  	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3545  		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3546  	else
3547  		flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3548  
3549  	for_each_set_bit(i, &flag, 32)
3550  		generic_handle_domain_irq(gc->irq.domain, i);
3551  	chained_irq_exit(irq_chip, desc);
3552  }
3553  
ingenic_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)3554  static void ingenic_gpio_set(struct gpio_chip *gc,
3555  		unsigned int offset, int value)
3556  {
3557  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3558  
3559  	ingenic_gpio_set_value(jzgc, offset, value);
3560  }
3561  
ingenic_gpio_get(struct gpio_chip * gc,unsigned int offset)3562  static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
3563  {
3564  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3565  
3566  	return (int) ingenic_gpio_get_value(jzgc, offset);
3567  }
3568  
ingenic_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)3569  static int ingenic_gpio_direction_output(struct gpio_chip *gc,
3570  		unsigned int offset, int value)
3571  {
3572  	ingenic_gpio_set(gc, offset, value);
3573  	return pinctrl_gpio_direction_output(gc, offset);
3574  }
3575  
ingenic_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg,bool set)3576  static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
3577  		unsigned int pin, unsigned int reg, bool set)
3578  {
3579  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3580  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3581  
3582  	if (set) {
3583  		if (is_soc_or_above(jzpc, ID_JZ4740))
3584  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3585  					REG_SET(reg), BIT(idx));
3586  		else
3587  			regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
3588  					reg, BIT(idx));
3589  	} else {
3590  		if (is_soc_or_above(jzpc, ID_JZ4740))
3591  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3592  					REG_CLEAR(reg), BIT(idx));
3593  		else
3594  			regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
3595  					reg, BIT(idx));
3596  	}
3597  }
3598  
ingenic_shadow_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg,bool set)3599  static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
3600  		unsigned int pin, u8 reg, bool set)
3601  {
3602  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3603  
3604  	regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
3605  			(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
3606  }
3607  
ingenic_shadow_config_pin_load(struct ingenic_pinctrl * jzpc,unsigned int pin)3608  static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
3609  		unsigned int pin)
3610  {
3611  	regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
3612  			pin / PINS_PER_GPIO_CHIP);
3613  }
3614  
jz4730_config_pin_function(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg_upper,u8 reg_lower,u8 value)3615  static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
3616  		unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3617  {
3618  	/*
3619  	 * JZ4730 function and IRQ registers support two-bits-per-pin
3620  	 * definitions, split into two groups of 16.
3621  	 */
3622  	unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
3623  	unsigned int mask = GENMASK(1, 0) << idx * 2;
3624  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3625  	u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3626  
3627  	regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
3628  			mask, value << (idx * 2));
3629  }
3630  
ingenic_get_pin_config(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg)3631  static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
3632  		unsigned int pin, unsigned int reg)
3633  {
3634  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3635  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3636  	unsigned int val;
3637  
3638  	regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
3639  
3640  	return val & BIT(idx);
3641  }
3642  
ingenic_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)3643  static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
3644  {
3645  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3646  	struct ingenic_pinctrl *jzpc = jzgc->jzpc;
3647  	unsigned int pin = gc->base + offset;
3648  
3649  	if (is_soc_or_above(jzpc, ID_JZ4770)) {
3650  		if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
3651  		    ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3652  			return GPIO_LINE_DIRECTION_IN;
3653  		return GPIO_LINE_DIRECTION_OUT;
3654  	} else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
3655  		if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
3656  			return GPIO_LINE_DIRECTION_IN;
3657  		return GPIO_LINE_DIRECTION_OUT;
3658  	}
3659  
3660  	if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3661  		return GPIO_LINE_DIRECTION_IN;
3662  
3663  	if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
3664  		return GPIO_LINE_DIRECTION_OUT;
3665  
3666  	return GPIO_LINE_DIRECTION_IN;
3667  }
3668  
3669  static const struct pinctrl_ops ingenic_pctlops = {
3670  	.get_groups_count = pinctrl_generic_get_group_count,
3671  	.get_group_name = pinctrl_generic_get_group_name,
3672  	.get_group_pins = pinctrl_generic_get_group_pins,
3673  	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3674  	.dt_free_map = pinconf_generic_dt_free_map,
3675  };
3676  
ingenic_gpio_irq_request(struct irq_data * data)3677  static int ingenic_gpio_irq_request(struct irq_data *data)
3678  {
3679  	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3680  	irq_hw_number_t irq = irqd_to_hwirq(data);
3681  	int ret;
3682  
3683  	ret = pinctrl_gpio_direction_input(gpio_chip, irq);
3684  	if (ret)
3685  		return ret;
3686  
3687  	return gpiochip_reqres_irq(gpio_chip, irq);
3688  }
3689  
ingenic_gpio_irq_release(struct irq_data * data)3690  static void ingenic_gpio_irq_release(struct irq_data *data)
3691  {
3692  	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3693  	irq_hw_number_t irq = irqd_to_hwirq(data);
3694  
3695  	return gpiochip_relres_irq(gpio_chip, irq);
3696  }
3697  
ingenic_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)3698  static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
3699  {
3700  	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3701  
3702  	seq_printf(p, "%s", gpio_chip->label);
3703  }
3704  
3705  static const struct irq_chip ingenic_gpio_irqchip = {
3706  	.irq_enable		= ingenic_gpio_irq_enable,
3707  	.irq_disable		= ingenic_gpio_irq_disable,
3708  	.irq_unmask		= ingenic_gpio_irq_unmask,
3709  	.irq_mask		= ingenic_gpio_irq_mask,
3710  	.irq_ack		= ingenic_gpio_irq_ack,
3711  	.irq_set_type		= ingenic_gpio_irq_set_type,
3712  	.irq_set_wake		= ingenic_gpio_irq_set_wake,
3713  	.irq_request_resources	= ingenic_gpio_irq_request,
3714  	.irq_release_resources	= ingenic_gpio_irq_release,
3715  	.irq_print_chip		= ingenic_gpio_irq_print_chip,
3716  	.flags			= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
3717  };
3718  
ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl * jzpc,int pin,int func)3719  static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
3720  		int pin, int func)
3721  {
3722  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3723  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3724  
3725  	dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
3726  			'A' + offt, idx, func);
3727  
3728  	if (is_soc_or_above(jzpc, ID_X1000)) {
3729  		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3730  		ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
3731  		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3732  		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3733  		ingenic_shadow_config_pin_load(jzpc, pin);
3734  	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3735  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3736  		ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
3737  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3738  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3739  	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3740  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
3741  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
3742  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
3743  	} else {
3744  		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3745  		jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
3746  	}
3747  
3748  	return 0;
3749  }
3750  
ingenic_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)3751  static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
3752  		unsigned int selector, unsigned int group)
3753  {
3754  	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3755  	struct function_desc *func;
3756  	struct group_desc *grp;
3757  	unsigned int i;
3758  	uintptr_t mode;
3759  	u8 *pin_modes;
3760  
3761  	func = pinmux_generic_get_function(pctldev, selector);
3762  	if (!func)
3763  		return -EINVAL;
3764  
3765  	grp = pinctrl_generic_get_group(pctldev, group);
3766  	if (!grp)
3767  		return -EINVAL;
3768  
3769  	dev_dbg(pctldev->dev, "enable function %s group %s\n",
3770  		func->func.name, grp->grp.name);
3771  
3772  	mode = (uintptr_t)grp->data;
3773  	if (mode <= 3) {
3774  		for (i = 0; i < grp->grp.npins; i++)
3775  			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);
3776  	} else {
3777  		pin_modes = grp->data;
3778  
3779  		for (i = 0; i < grp->grp.npins; i++)
3780  			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);
3781  	}
3782  
3783  	return 0;
3784  }
3785  
ingenic_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)3786  static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
3787  		struct pinctrl_gpio_range *range,
3788  		unsigned int pin, bool input)
3789  {
3790  	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3791  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3792  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3793  
3794  	dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
3795  			'A' + offt, idx, input ? "in" : "out");
3796  
3797  	if (is_soc_or_above(jzpc, ID_X1000)) {
3798  		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3799  		ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
3800  		ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3801  		ingenic_shadow_config_pin_load(jzpc, pin);
3802  	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3803  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3804  		ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
3805  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3806  	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3807  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
3808  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
3809  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
3810  	} else {
3811  		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3812  		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
3813  		jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
3814  	}
3815  
3816  	return 0;
3817  }
3818  
3819  static const struct pinmux_ops ingenic_pmxops = {
3820  	.get_functions_count = pinmux_generic_get_function_count,
3821  	.get_function_name = pinmux_generic_get_function_name,
3822  	.get_function_groups = pinmux_generic_get_function_groups,
3823  	.set_mux = ingenic_pinmux_set_mux,
3824  	.gpio_set_direction = ingenic_pinmux_gpio_set_direction,
3825  };
3826  
ingenic_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)3827  static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
3828  		unsigned int pin, unsigned long *config)
3829  {
3830  	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3831  	enum pin_config_param param = pinconf_to_config_param(*config);
3832  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3833  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3834  	unsigned int arg = 1;
3835  	unsigned int bias, reg;
3836  	bool pull, pullup, pulldown;
3837  
3838  	if (is_soc_or_above(jzpc, ID_X2000)) {
3839  		pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3840  				!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3841  				(jzpc->info->pull_ups[offt] & BIT(idx));
3842  		pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3843  				!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3844  				(jzpc->info->pull_downs[offt] & BIT(idx));
3845  
3846  	} else if (is_soc_or_above(jzpc, ID_X1830)) {
3847  		unsigned int half = PINS_PER_GPIO_CHIP / 2;
3848  		unsigned int idxh = (pin % half) * 2;
3849  
3850  		if (idx < half)
3851  			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3852  					X1830_GPIO_PEL, &bias);
3853  		else
3854  			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3855  					X1830_GPIO_PEH, &bias);
3856  
3857  		bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
3858  
3859  		pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
3860  		pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
3861  
3862  	} else {
3863  		if (is_soc_or_above(jzpc, ID_JZ4770))
3864  			pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
3865  		else if (is_soc_or_above(jzpc, ID_JZ4740))
3866  			pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
3867  		else
3868  			pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
3869  
3870  		pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
3871  		pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
3872  	}
3873  
3874  	switch (param) {
3875  	case PIN_CONFIG_BIAS_DISABLE:
3876  		if (pullup || pulldown)
3877  			return -EINVAL;
3878  
3879  		break;
3880  
3881  	case PIN_CONFIG_BIAS_PULL_UP:
3882  		if (!pullup)
3883  			return -EINVAL;
3884  
3885  		break;
3886  
3887  	case PIN_CONFIG_BIAS_PULL_DOWN:
3888  		if (!pulldown)
3889  			return -EINVAL;
3890  
3891  		break;
3892  
3893  	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3894  		if (is_soc_or_above(jzpc, ID_X2000))
3895  			reg = X2000_GPIO_SMT;
3896  		else if (is_soc_or_above(jzpc, ID_X1830))
3897  			reg = X1830_GPIO_SMT;
3898  		else
3899  			return -EINVAL;
3900  
3901  		arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3902  		break;
3903  
3904  	case PIN_CONFIG_SLEW_RATE:
3905  		if (is_soc_or_above(jzpc, ID_X2000))
3906  			reg = X2000_GPIO_SR;
3907  		else if (is_soc_or_above(jzpc, ID_X1830))
3908  			reg = X1830_GPIO_SR;
3909  		else
3910  			return -EINVAL;
3911  
3912  		arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3913  		break;
3914  
3915  	default:
3916  		return -ENOTSUPP;
3917  	}
3918  
3919  	*config = pinconf_to_config_packed(param, arg);
3920  	return 0;
3921  }
3922  
ingenic_set_bias(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int bias)3923  static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
3924  		unsigned int pin, unsigned int bias)
3925  {
3926  	if (is_soc_or_above(jzpc, ID_X2000)) {
3927  		switch (bias) {
3928  		case GPIO_PULL_UP:
3929  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3930  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
3931  			break;
3932  
3933  		case GPIO_PULL_DOWN:
3934  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3935  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
3936  			break;
3937  
3938  		case GPIO_PULL_DIS:
3939  		default:
3940  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3941  			ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3942  		}
3943  
3944  	} else if (is_soc_or_above(jzpc, ID_X1830)) {
3945  		unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3946  		unsigned int half = PINS_PER_GPIO_CHIP / 2;
3947  		unsigned int idxh = (pin % half) * 2;
3948  		unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3949  
3950  		if (idx < half) {
3951  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3952  					REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
3953  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3954  					REG_SET(X1830_GPIO_PEL), bias << idxh);
3955  		} else {
3956  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3957  					REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
3958  			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3959  					REG_SET(X1830_GPIO_PEH), bias << idxh);
3960  		}
3961  
3962  	} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3963  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
3964  	} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3965  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
3966  	} else {
3967  		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
3968  	}
3969  }
3970  
ingenic_set_schmitt_trigger(struct ingenic_pinctrl * jzpc,unsigned int pin,bool enable)3971  static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
3972  		unsigned int pin, bool enable)
3973  {
3974  	if (is_soc_or_above(jzpc, ID_X2000))
3975  		ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
3976  	else
3977  		ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
3978  }
3979  
ingenic_set_output_level(struct ingenic_pinctrl * jzpc,unsigned int pin,bool high)3980  static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
3981  				     unsigned int pin, bool high)
3982  {
3983  	if (is_soc_or_above(jzpc, ID_JZ4770))
3984  		ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
3985  	else if (is_soc_or_above(jzpc, ID_JZ4740))
3986  		ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
3987  	else
3988  		ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
3989  }
3990  
ingenic_set_slew_rate(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int slew)3991  static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
3992  		unsigned int pin, unsigned int slew)
3993  {
3994  	if (is_soc_or_above(jzpc, ID_X2000))
3995  		ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
3996  	else
3997  		ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
3998  }
3999  
ingenic_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)4000  static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
4001  		unsigned long *configs, unsigned int num_configs)
4002  {
4003  	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4004  	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4005  	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4006  	unsigned int cfg, arg;
4007  	int ret;
4008  
4009  	for (cfg = 0; cfg < num_configs; cfg++) {
4010  		switch (pinconf_to_config_param(configs[cfg])) {
4011  		case PIN_CONFIG_BIAS_DISABLE:
4012  		case PIN_CONFIG_BIAS_PULL_UP:
4013  		case PIN_CONFIG_BIAS_PULL_DOWN:
4014  		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4015  		case PIN_CONFIG_OUTPUT:
4016  		case PIN_CONFIG_SLEW_RATE:
4017  			continue;
4018  		default:
4019  			return -ENOTSUPP;
4020  		}
4021  	}
4022  
4023  	for (cfg = 0; cfg < num_configs; cfg++) {
4024  		arg = pinconf_to_config_argument(configs[cfg]);
4025  
4026  		switch (pinconf_to_config_param(configs[cfg])) {
4027  		case PIN_CONFIG_BIAS_DISABLE:
4028  			dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
4029  					'A' + offt, idx);
4030  			ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
4031  			break;
4032  
4033  		case PIN_CONFIG_BIAS_PULL_UP:
4034  			if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
4035  				return -EINVAL;
4036  			dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
4037  					'A' + offt, idx);
4038  			ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
4039  			break;
4040  
4041  		case PIN_CONFIG_BIAS_PULL_DOWN:
4042  			if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
4043  				return -EINVAL;
4044  			dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
4045  					'A' + offt, idx);
4046  			ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
4047  			break;
4048  
4049  		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4050  			if (!is_soc_or_above(jzpc, ID_X1830))
4051  				return -EINVAL;
4052  
4053  			ingenic_set_schmitt_trigger(jzpc, pin, arg);
4054  			break;
4055  
4056  		case PIN_CONFIG_OUTPUT:
4057  			ret = pinctrl_gpio_direction_output(jzpc->gc,
4058  							pin - jzpc->gc->base);
4059  			if (ret)
4060  				return ret;
4061  
4062  			ingenic_set_output_level(jzpc, pin, arg);
4063  			break;
4064  
4065  		case PIN_CONFIG_SLEW_RATE:
4066  			if (!is_soc_or_above(jzpc, ID_X1830))
4067  				return -EINVAL;
4068  
4069  			ingenic_set_slew_rate(jzpc, pin, arg);
4070  			break;
4071  
4072  		default:
4073  			/* unreachable */
4074  			break;
4075  		}
4076  	}
4077  
4078  	return 0;
4079  }
4080  
ingenic_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)4081  static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
4082  		unsigned int group, unsigned long *config)
4083  {
4084  	const unsigned int *pins;
4085  	unsigned int i, npins, old = 0;
4086  	int ret;
4087  
4088  	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4089  	if (ret)
4090  		return ret;
4091  
4092  	for (i = 0; i < npins; i++) {
4093  		if (ingenic_pinconf_get(pctldev, pins[i], config))
4094  			return -ENOTSUPP;
4095  
4096  		/* configs do not match between two pins */
4097  		if (i && (old != *config))
4098  			return -ENOTSUPP;
4099  
4100  		old = *config;
4101  	}
4102  
4103  	return 0;
4104  }
4105  
ingenic_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)4106  static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
4107  		unsigned int group, unsigned long *configs,
4108  		unsigned int num_configs)
4109  {
4110  	const unsigned int *pins;
4111  	unsigned int i, npins;
4112  	int ret;
4113  
4114  	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4115  	if (ret)
4116  		return ret;
4117  
4118  	for (i = 0; i < npins; i++) {
4119  		ret = ingenic_pinconf_set(pctldev,
4120  				pins[i], configs, num_configs);
4121  		if (ret)
4122  			return ret;
4123  	}
4124  
4125  	return 0;
4126  }
4127  
4128  static const struct pinconf_ops ingenic_confops = {
4129  	.is_generic = true,
4130  	.pin_config_get = ingenic_pinconf_get,
4131  	.pin_config_set = ingenic_pinconf_set,
4132  	.pin_config_group_get = ingenic_pinconf_group_get,
4133  	.pin_config_group_set = ingenic_pinconf_group_set,
4134  };
4135  
4136  static const struct regmap_config ingenic_pinctrl_regmap_config = {
4137  	.reg_bits = 32,
4138  	.val_bits = 32,
4139  	.reg_stride = 4,
4140  };
4141  
4142  static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
4143  	{ .compatible = "ingenic,jz4730-gpio" },
4144  	{ .compatible = "ingenic,jz4740-gpio" },
4145  	{ .compatible = "ingenic,jz4725b-gpio" },
4146  	{ .compatible = "ingenic,jz4750-gpio" },
4147  	{ .compatible = "ingenic,jz4755-gpio" },
4148  	{ .compatible = "ingenic,jz4760-gpio" },
4149  	{ .compatible = "ingenic,jz4770-gpio" },
4150  	{ .compatible = "ingenic,jz4775-gpio" },
4151  	{ .compatible = "ingenic,jz4780-gpio" },
4152  	{ .compatible = "ingenic,x1000-gpio" },
4153  	{ .compatible = "ingenic,x1830-gpio" },
4154  	{ .compatible = "ingenic,x2000-gpio" },
4155  	{ .compatible = "ingenic,x2100-gpio" },
4156  	{},
4157  };
4158  
ingenic_gpio_probe(struct ingenic_pinctrl * jzpc,struct fwnode_handle * fwnode)4159  static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
4160  				     struct fwnode_handle *fwnode)
4161  {
4162  	struct ingenic_gpio_chip *jzgc;
4163  	struct device *dev = jzpc->dev;
4164  	struct gpio_irq_chip *girq;
4165  	unsigned int bank;
4166  	int err;
4167  
4168  	err = fwnode_property_read_u32(fwnode, "reg", &bank);
4169  	if (err) {
4170  		dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
4171  		return err;
4172  	}
4173  
4174  	jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4175  	if (!jzgc)
4176  		return -ENOMEM;
4177  
4178  	jzpc->gc = &jzgc->gc;
4179  
4180  	jzgc->jzpc = jzpc;
4181  	jzgc->reg_base = bank * jzpc->info->reg_offset;
4182  
4183  	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4184  	if (!jzgc->gc.label)
4185  		return -ENOMEM;
4186  
4187  	/* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
4188  	 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
4189  	 * <linux/gpio/consumer.h> INSTEAD.
4190  	 */
4191  	jzgc->gc.base = bank * 32;
4192  
4193  	jzgc->gc.ngpio = 32;
4194  	jzgc->gc.parent = dev;
4195  	jzgc->gc.fwnode = fwnode;
4196  	jzgc->gc.owner = THIS_MODULE;
4197  
4198  	jzgc->gc.set = ingenic_gpio_set;
4199  	jzgc->gc.get = ingenic_gpio_get;
4200  	jzgc->gc.direction_input = pinctrl_gpio_direction_input;
4201  	jzgc->gc.direction_output = ingenic_gpio_direction_output;
4202  	jzgc->gc.get_direction = ingenic_gpio_get_direction;
4203  	jzgc->gc.request = gpiochip_generic_request;
4204  	jzgc->gc.free = gpiochip_generic_free;
4205  
4206  	err = fwnode_irq_get(fwnode, 0);
4207  	if (err < 0)
4208  		return err;
4209  	if (!err)
4210  		return -EINVAL;
4211  	jzgc->irq = err;
4212  
4213  	girq = &jzgc->gc.irq;
4214  	gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
4215  	girq->parent_handler = ingenic_gpio_irq_handler;
4216  	girq->num_parents = 1;
4217  	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
4218  				     GFP_KERNEL);
4219  	if (!girq->parents)
4220  		return -ENOMEM;
4221  
4222  	girq->parents[0] = jzgc->irq;
4223  	girq->default_type = IRQ_TYPE_NONE;
4224  	girq->handler = handle_level_irq;
4225  
4226  	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
4227  	if (err)
4228  		return err;
4229  
4230  	return 0;
4231  }
4232  
ingenic_pinctrl_probe(struct platform_device * pdev)4233  static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
4234  {
4235  	struct device *dev = &pdev->dev;
4236  	struct ingenic_pinctrl *jzpc;
4237  	struct pinctrl_desc *pctl_desc;
4238  	void __iomem *base;
4239  	const struct ingenic_chip_info *chip_info;
4240  	struct regmap_config regmap_config;
4241  	struct fwnode_handle *fwnode;
4242  	unsigned int i;
4243  	int err;
4244  
4245  	chip_info = device_get_match_data(dev);
4246  	if (!chip_info) {
4247  		dev_err(dev, "Unsupported SoC\n");
4248  		return -EINVAL;
4249  	}
4250  
4251  	jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
4252  	if (!jzpc)
4253  		return -ENOMEM;
4254  
4255  	base = devm_platform_ioremap_resource(pdev, 0);
4256  	if (IS_ERR(base))
4257  		return PTR_ERR(base);
4258  
4259  	regmap_config = ingenic_pinctrl_regmap_config;
4260  	if (chip_info->access_table) {
4261  		regmap_config.rd_table = chip_info->access_table;
4262  		regmap_config.wr_table = chip_info->access_table;
4263  	} else {
4264  		regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
4265  	}
4266  
4267  	jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
4268  	if (IS_ERR(jzpc->map)) {
4269  		dev_err(dev, "Failed to create regmap\n");
4270  		return PTR_ERR(jzpc->map);
4271  	}
4272  
4273  	jzpc->dev = dev;
4274  	jzpc->info = chip_info;
4275  
4276  	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
4277  	if (!pctl_desc)
4278  		return -ENOMEM;
4279  
4280  	/* fill in pinctrl_desc structure */
4281  	pctl_desc->name = dev_name(dev);
4282  	pctl_desc->owner = THIS_MODULE;
4283  	pctl_desc->pctlops = &ingenic_pctlops;
4284  	pctl_desc->pmxops = &ingenic_pmxops;
4285  	pctl_desc->confops = &ingenic_confops;
4286  	pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
4287  	pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
4288  			pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
4289  	if (!jzpc->pdesc)
4290  		return -ENOMEM;
4291  
4292  	for (i = 0; i < pctl_desc->npins; i++) {
4293  		jzpc->pdesc[i].number = i;
4294  		jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
4295  						'A' + (i / PINS_PER_GPIO_CHIP),
4296  						i % PINS_PER_GPIO_CHIP);
4297  	}
4298  
4299  	jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
4300  	if (IS_ERR(jzpc->pctl)) {
4301  		dev_err(dev, "Failed to register pinctrl\n");
4302  		return PTR_ERR(jzpc->pctl);
4303  	}
4304  
4305  	for (i = 0; i < chip_info->num_groups; i++) {
4306  		const struct group_desc *group = &chip_info->groups[i];
4307  		const struct pingroup *grp = &group->grp;
4308  
4309  		err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,
4310  						group->data);
4311  		if (err < 0) {
4312  			dev_err(dev, "Failed to register group %s\n", grp->name);
4313  			return err;
4314  		}
4315  	}
4316  
4317  	for (i = 0; i < chip_info->num_functions; i++) {
4318  		const struct function_desc *function = &chip_info->functions[i];
4319  		const struct pinfunction *func = &function->func;
4320  
4321  		err = pinmux_generic_add_function(jzpc->pctl, func->name,
4322  						  func->groups, func->ngroups,
4323  						  function->data);
4324  		if (err < 0) {
4325  			dev_err(dev, "Failed to register function %s\n", func->name);
4326  			return err;
4327  		}
4328  	}
4329  
4330  	dev_set_drvdata(dev, jzpc->map);
4331  
4332  	device_for_each_child_node(dev, fwnode) {
4333  		if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
4334  			err = ingenic_gpio_probe(jzpc, fwnode);
4335  			if (err) {
4336  				fwnode_handle_put(fwnode);
4337  				return err;
4338  			}
4339  		}
4340  	}
4341  
4342  	return 0;
4343  }
4344  
4345  #define IF_ENABLED(cfg, ptr)	PTR_IF(IS_ENABLED(cfg), (ptr))
4346  
4347  static const struct of_device_id ingenic_pinctrl_of_matches[] = {
4348  	{
4349  		.compatible = "ingenic,jz4730-pinctrl",
4350  		.data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
4351  	},
4352  	{
4353  		.compatible = "ingenic,jz4740-pinctrl",
4354  		.data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
4355  	},
4356  	{
4357  		.compatible = "ingenic,jz4725b-pinctrl",
4358  		.data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
4359  	},
4360  	{
4361  		.compatible = "ingenic,jz4750-pinctrl",
4362  		.data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
4363  	},
4364  	{
4365  		.compatible = "ingenic,jz4755-pinctrl",
4366  		.data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
4367  	},
4368  	{
4369  		.compatible = "ingenic,jz4760-pinctrl",
4370  		.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4371  	},
4372  	{
4373  		.compatible = "ingenic,jz4760b-pinctrl",
4374  		.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4375  	},
4376  	{
4377  		.compatible = "ingenic,jz4770-pinctrl",
4378  		.data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
4379  	},
4380  	{
4381  		.compatible = "ingenic,jz4775-pinctrl",
4382  		.data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
4383  	},
4384  	{
4385  		.compatible = "ingenic,jz4780-pinctrl",
4386  		.data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
4387  	},
4388  	{
4389  		.compatible = "ingenic,x1000-pinctrl",
4390  		.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4391  	},
4392  	{
4393  		.compatible = "ingenic,x1000e-pinctrl",
4394  		.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4395  	},
4396  	{
4397  		.compatible = "ingenic,x1500-pinctrl",
4398  		.data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
4399  	},
4400  	{
4401  		.compatible = "ingenic,x1830-pinctrl",
4402  		.data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
4403  	},
4404  	{
4405  		.compatible = "ingenic,x2000-pinctrl",
4406  		.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4407  	},
4408  	{
4409  		.compatible = "ingenic,x2000e-pinctrl",
4410  		.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4411  	},
4412  	{
4413  		.compatible = "ingenic,x2100-pinctrl",
4414  		.data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
4415  	},
4416  	{ /* sentinel */ },
4417  };
4418  
4419  static struct platform_driver ingenic_pinctrl_driver = {
4420  	.driver = {
4421  		.name = "pinctrl-ingenic",
4422  		.of_match_table = ingenic_pinctrl_of_matches,
4423  	},
4424  };
4425  
ingenic_pinctrl_drv_register(void)4426  static int __init ingenic_pinctrl_drv_register(void)
4427  {
4428  	return platform_driver_probe(&ingenic_pinctrl_driver,
4429  				     ingenic_pinctrl_probe);
4430  }
4431  subsys_initcall(ingenic_pinctrl_drv_register);
4432