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Searched refs:ixUVD_CGC_MEM_CTRL (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h27 #define ixUVD_CGC_MEM_CTRL 0x00C0 macro
Duvd_4_2_d.h86 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_3_1_d.h88 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_5_0_d.h97 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_6_0_d.h113 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c601 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
603 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
610 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
612 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c615 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
617 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
624 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
626 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
Duvd_v5_0.c774 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
776 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
783 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
785 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
Duvd_v6_0.c1434 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1436 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
1443 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1445 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_3_0_0_offset.h1509 #define ixUVD_CGC_MEM_CTRL … macro
Dvcn_5_0_0_offset.h1624 #define ixUVD_CGC_MEM_CTRL … macro
Dvcn_4_0_0_offset.h1984 #define ixUVD_CGC_MEM_CTRL … macro
Dvcn_4_0_3_offset.h2284 #define ixUVD_CGC_MEM_CTRL … macro