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Searched refs:ixAZALIA_F2_CODEC_PIN_CONTROL_HBR (Results 1 – 22 of 22) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h149 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C macro
Ddce_8_0_d.h5388 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c macro
Ddce_10_0_d.h6622 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c macro
Ddce_11_0_d.h6784 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c macro
Ddce_11_2_d.h8129 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c macro
Ddce_12_0_offset.h17974 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7333 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_0_1_offset.h12132 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_1_0_offset.h12976 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_2_1_0_offset.h12736 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_5_1_offset.h1438 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_1_2_offset.h13950 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_2_1_offset.h13457 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_2_0_offset.h13503 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_1_5_offset.h14056 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_1_4_offset.h1603 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_5_0_offset.h1459 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_4_1_0_offset.h15513 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_1_6_offset.h14547 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_0_2_offset.h15135 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_2_0_0_offset.h16400 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro
Ddcn_3_0_0_offset.h16885 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … macro