Home
last modified time | relevance | path

Searched refs:iowrite32 (Results 1 – 25 of 515) sorted by relevance

12345678910>>...21

/linux-6.12.1/drivers/net/wwan/t7xx/
Dt7xx_cldma.c34 iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY); in t7xx_cldma_clear_ip_busy()
57 iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG); in t7xx_cldma_hw_restore()
59 iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM); in t7xx_cldma_hw_restore()
60 iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM); in t7xx_cldma_hw_restore()
72 iowrite32(val, reg); in t7xx_cldma_hw_start_queue()
78 iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0); in t7xx_cldma_hw_start()
79 iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0); in t7xx_cldma_hw_start()
81 iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0); in t7xx_cldma_hw_start()
82 iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0); in t7xx_cldma_hw_start()
91 iowrite32(val, ao_base + REG_INFRA_RST2_SET); in t7xx_cldma_hw_reset()
[all …]
Dt7xx_dpmaif.c42 iowrite32(DPMAIF_AP_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_init_intr()
45 iowrite32(ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMCR0); in t7xx_dpmaif_init_intr()
46 iowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMSR0); in t7xx_dpmaif_init_intr()
60 iowrite32(DPMAIF_AP_APDL_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0); in t7xx_dpmaif_init_intr()
63 iowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_init_intr()
71 iowrite32(DPMAIF_AP_IP_BUSY_MASK, hw_info->pcie_base + DPMAIF_AP_IP_BUSY); in t7xx_dpmaif_init_intr()
72 iowrite32(isr_en_msk->ap_udl_ip_busy_en_msk, in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
77 iowrite32(DPMA_HPC_ALL_INT_MASK, hw_info->pcie_base + DPMAIF_HPC_INTR_MASK); in t7xx_dpmaif_init_intr()
91 iowrite32(ul_int_que_done, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMSR0); in t7xx_dpmaif_mask_ulq_intr()
[all …]
Dt7xx_mhccif.c37 iowrite32(mask, mhccif_pbase + REG_EP2RC_SW_INT_ACK); in t7xx_mhccif_clear_interrupts()
50 iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
68 iowrite32(T7XX_L1_BIT(1), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
73 iowrite32(val, IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
87 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET); in t7xx_mhccif_mask_set()
92 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR); in t7xx_mhccif_mask_clr()
120 iowrite32(BIT(channel), mhccif_pbase + REG_RC2EP_SW_BSY); in t7xx_mhccif_h2d_swint_trigger()
121 iowrite32(channel, mhccif_pbase + REG_RC2EP_SW_TCHNUM); in t7xx_mhccif_h2d_swint_trigger()
/linux-6.12.1/drivers/watchdog/
Ddavinci_wdt.c80 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start()
82 iowrite32(0, davinci_wdt->base + TGCR); in davinci_wdt_start()
84 iowrite32(tgcr, davinci_wdt->base + TGCR); in davinci_wdt_start()
86 iowrite32(0, davinci_wdt->base + TIM12); in davinci_wdt_start()
87 iowrite32(0, davinci_wdt->base + TIM34); in davinci_wdt_start()
90 iowrite32(timer_margin, davinci_wdt->base + PRD12); in davinci_wdt_start()
92 iowrite32(timer_margin, davinci_wdt->base + PRD34); in davinci_wdt_start()
94 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); in davinci_wdt_start()
100 iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); in davinci_wdt_start()
102 iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); in davinci_wdt_start()
[all …]
/linux-6.12.1/drivers/net/ethernet/dec/tulip/
Dmedia.c68 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); in tulip_mdio_read()
82 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); in tulip_mdio_read()
84 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); in tulip_mdio_read()
91 iowrite32(MDIO_ENB | dataval, mdio_addr); in tulip_mdio_read()
93 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); in tulip_mdio_read()
98 iowrite32(MDIO_ENB_IN, mdio_addr); in tulip_mdio_read()
101 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); in tulip_mdio_read()
123 iowrite32(val, ioaddr + comet_miireg2offset[location]); in tulip_mdio_write()
129 iowrite32(cmd, ioaddr + 0xA0); in tulip_mdio_write()
141 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); in tulip_mdio_write()
[all …]
D21142.c79 iowrite32(0, ioaddr + CSR13); in t21142_media_task()
80 iowrite32(0x0003FFFF, ioaddr + CSR14); in t21142_media_task()
82 iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13); in t21142_media_task()
87 iowrite32(0, ioaddr + CSR13); in t21142_media_task()
88 iowrite32(0x0003FFFF, ioaddr + CSR14); in t21142_media_task()
90 iowrite32(1, ioaddr + CSR13); in t21142_media_task()
98 iowrite32(0x0301, ioaddr + CSR12); in t21142_media_task()
124 iowrite32(0x0001, ioaddr + CSR13); in t21142_start_nway()
126 iowrite32(csr14, ioaddr + CSR14); in t21142_start_nway()
128 iowrite32(tp->csr6, ioaddr + CSR6); in t21142_start_nway()
[all …]
Dpnic.c33 iowrite32(0x32 | (dev->if_port & 1), ioaddr + CSR12); in pnic_do_nway()
35 iowrite32(0x1F868, ioaddr + 0xB8); in pnic_do_nway()
62 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7); in pnic_lnk_change()
70 iowrite32(tp->csr6, ioaddr + CSR6); in pnic_lnk_change()
71 iowrite32(0x30, ioaddr + CSR12); in pnic_lnk_change()
72 iowrite32(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */ in pnic_lnk_change()
83 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7); in pnic_lnk_change()
118 iowrite32(0x0201F078, ioaddr + 0xB8); in pnic_timer()
137 iowrite32(0x33, ioaddr + CSR12); in pnic_timer()
139 iowrite32(0x1F868, ioaddr + 0xB8); in pnic_timer()
[all …]
/linux-6.12.1/drivers/ata/
Dsata_rcar.c158 iowrite32(0, base + SATAPHYADDR_REG); in sata_rcar_gen1_phy_preinit()
160 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_preinit()
163 iowrite32(0, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_preinit()
173 iowrite32(0, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_write()
175 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); in sata_rcar_gen1_phy_write()
177 iowrite32(val, base + SATAPHYWDATA_REG); in sata_rcar_gen1_phy_write()
182 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); in sata_rcar_gen1_phy_write()
192 iowrite32(0, base + SATAPHYADDR_REG); in sata_rcar_gen1_phy_write()
210 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); in sata_rcar_gen2_phy_init()
211 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); in sata_rcar_gen2_phy_init()
[all …]
/linux-6.12.1/drivers/scsi/snic/
Dvnic_cq.c43 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size); in svnic_cq_init()
44 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable); in svnic_cq_init()
45 iowrite32(color_enable, &cq->ctrl->color_enable); in svnic_cq_init()
46 iowrite32(cq_head, &cq->ctrl->cq_head); in svnic_cq_init()
47 iowrite32(cq_tail, &cq->ctrl->cq_tail); in svnic_cq_init()
48 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color); in svnic_cq_init()
49 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable); in svnic_cq_init()
50 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable); in svnic_cq_init()
51 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable); in svnic_cq_init()
52 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset); in svnic_cq_init()
[all …]
/linux-6.12.1/drivers/net/ethernet/cisco/enic/
Dvnic_cq.c48 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size); in vnic_cq_init()
49 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable); in vnic_cq_init()
50 iowrite32(color_enable, &cq->ctrl->color_enable); in vnic_cq_init()
51 iowrite32(cq_head, &cq->ctrl->cq_head); in vnic_cq_init()
52 iowrite32(cq_tail, &cq->ctrl->cq_tail); in vnic_cq_init()
53 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color); in vnic_cq_init()
54 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable); in vnic_cq_init()
55 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable); in vnic_cq_init()
56 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable); in vnic_cq_init()
57 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset); in vnic_cq_init()
[all …]
Dvnic_rq.c111 iowrite32(count, &rq->ctrl->ring_size); in vnic_rq_init_start()
112 iowrite32(cq_index, &rq->ctrl->cq_index); in vnic_rq_init_start()
113 iowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable); in vnic_rq_init_start()
114 iowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset); in vnic_rq_init_start()
115 iowrite32(0, &rq->ctrl->dropped_packet_count); in vnic_rq_init_start()
116 iowrite32(0, &rq->ctrl->error_status); in vnic_rq_init_start()
117 iowrite32(fetch_index, &rq->ctrl->fetch_index); in vnic_rq_init_start()
118 iowrite32(posted_index, &rq->ctrl->posted_index); in vnic_rq_init_start()
140 iowrite32(1, &rq->ctrl->enable); in vnic_rq_enable()
154 iowrite32(0, &rq->ctrl->enable); in vnic_rq_disable()
[all …]
Dvnic_wq.c131 iowrite32(count, &wq->ctrl->ring_size); in enic_wq_init_start()
132 iowrite32(fetch_index, &wq->ctrl->fetch_index); in enic_wq_init_start()
133 iowrite32(posted_index, &wq->ctrl->posted_index); in enic_wq_init_start()
134 iowrite32(cq_index, &wq->ctrl->cq_index); in enic_wq_init_start()
135 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); in enic_wq_init_start()
136 iowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset); in enic_wq_init_start()
137 iowrite32(0, &wq->ctrl->error_status); in enic_wq_init_start()
160 iowrite32(1, &wq->ctrl->enable); in vnic_wq_enable()
168 iowrite32(0, &wq->ctrl->enable); in vnic_wq_disable()
199 iowrite32(0, &wq->ctrl->fetch_index); in vnic_wq_clean()
[all …]
/linux-6.12.1/drivers/scsi/fnic/
Dvnic_cq.c50 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size); in vnic_cq_init()
51 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable); in vnic_cq_init()
52 iowrite32(color_enable, &cq->ctrl->color_enable); in vnic_cq_init()
53 iowrite32(cq_head, &cq->ctrl->cq_head); in vnic_cq_init()
54 iowrite32(cq_tail, &cq->ctrl->cq_tail); in vnic_cq_init()
55 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color); in vnic_cq_init()
56 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable); in vnic_cq_init()
57 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable); in vnic_cq_init()
58 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable); in vnic_cq_init()
59 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset); in vnic_cq_init()
[all …]
Dvnic_wq.c151 iowrite32(count, &wq->ctrl->ring_size); in vnic_wq_init_start()
152 iowrite32(fetch_index, &wq->ctrl->fetch_index); in vnic_wq_init_start()
153 iowrite32(posted_index, &wq->ctrl->posted_index); in vnic_wq_init_start()
154 iowrite32(cq_index, &wq->ctrl->cq_index); in vnic_wq_init_start()
155 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); in vnic_wq_init_start()
156 iowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset); in vnic_wq_init_start()
157 iowrite32(0, &wq->ctrl->error_status); in vnic_wq_init_start()
173 iowrite32(wq->ring.desc_count, &wq->ctrl->ring_size); in vnic_wq_init()
174 iowrite32(0, &wq->ctrl->fetch_index); in vnic_wq_init()
175 iowrite32(0, &wq->ctrl->posted_index); in vnic_wq_init()
[all …]
Dvnic_wq_copy.c15 iowrite32(1, &wq->ctrl->enable); in vnic_wq_copy_enable()
22 iowrite32(0, &wq->ctrl->enable); in vnic_wq_copy_disable()
50 iowrite32(0, &wq->ctrl->fetch_index); in vnic_wq_copy_clean()
51 iowrite32(0, &wq->ctrl->posted_index); in vnic_wq_copy_clean()
52 iowrite32(0, &wq->ctrl->error_status); in vnic_wq_copy_clean()
92 iowrite32(wq->ring.desc_count, &wq->ctrl->ring_size); in vnic_wq_copy_init()
93 iowrite32(0, &wq->ctrl->fetch_index); in vnic_wq_copy_init()
94 iowrite32(0, &wq->ctrl->posted_index); in vnic_wq_copy_init()
95 iowrite32(cq_index, &wq->ctrl->cq_index); in vnic_wq_copy_init()
96 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); in vnic_wq_copy_init()
[all …]
/linux-6.12.1/arch/arc/plat-axs10x/
Daxs10x.c67 iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK); in axs10x_enable_gpio_intc_wire()
68 iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL); in axs10x_enable_gpio_intc_wire()
69 iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY); in axs10x_enable_gpio_intc_wire()
70 iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); in axs10x_enable_gpio_intc_wire()
239 iowrite32(slave_select, base + 0x0); /* SLV0 */ in axs101_set_memmap()
240 iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ in axs101_set_memmap()
248 iowrite32(slave_select, base + 0x4); /* SLV1 */ in axs101_set_memmap()
249 iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ in axs101_set_memmap()
258 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD); in axs101_early_init()
263 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD); in axs101_early_init()
[all …]
/linux-6.12.1/drivers/rtc/
Drtc-asm9260.c126 iowrite32(0, priv->iobase + HW_CIIR); in asm9260_rtc_irq()
177 iowrite32(0, priv->iobase + HW_SEC); in asm9260_rtc_set_time()
179 iowrite32(tm->tm_year, priv->iobase + HW_YEAR); in asm9260_rtc_set_time()
180 iowrite32(tm->tm_mon, priv->iobase + HW_MONTH); in asm9260_rtc_set_time()
181 iowrite32(tm->tm_mday, priv->iobase + HW_DOM); in asm9260_rtc_set_time()
182 iowrite32(tm->tm_wday, priv->iobase + HW_DOW); in asm9260_rtc_set_time()
183 iowrite32(tm->tm_yday, priv->iobase + HW_DOY); in asm9260_rtc_set_time()
184 iowrite32(tm->tm_hour, priv->iobase + HW_HOUR); in asm9260_rtc_set_time()
185 iowrite32(tm->tm_min, priv->iobase + HW_MIN); in asm9260_rtc_set_time()
186 iowrite32(tm->tm_sec, priv->iobase + HW_SEC); in asm9260_rtc_set_time()
[all …]
/linux-6.12.1/drivers/w1/masters/
Damd_axi_w1.c81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
123 iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
126 iowrite32(AXIW1_WRITEBIT + (bit & 0x01), in amd_axi_w1_touch_bit()
130 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
144 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
170 iowrite32(AXIW1_READBYTE, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_read_byte()
173 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
186 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
211 iowrite32(AXIW1_WRITEBYTE + val, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_write_byte()
214 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_write_byte()
[all …]
/linux-6.12.1/drivers/crypto/intel/keembay/
Docs-aes.c206 iowrite32(0x7FF, aes_dev->base_reg + AES_BYTE_ORDER_CFG_OFFSET); in aes_a_set_endianness()
212 iowrite32(AES_ACTIVE_TRIGGER, aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_op_trigger()
218 iowrite32(AES_ACTIVE_TERMINATION, in aes_a_op_termination()
233 iowrite32(AES_ACTIVE_LAST_CCM_GCM, in aes_a_set_last_gcx()
267 iowrite32(AES_ACTIVE_LAST_ADATA | AES_ACTIVE_LAST_CCM_GCM, in aes_a_set_last_gcx_and_adata()
274 iowrite32(0, aes_dev->base_reg + AES_A_DMA_SRC_SIZE_OFFSET); in aes_a_dma_set_xfer_size_zero()
275 iowrite32(0, aes_dev->base_reg + AES_A_DMA_DST_SIZE_OFFSET); in aes_a_dma_set_xfer_size_zero()
281 iowrite32(AES_A_DMA_DMA_MODE_ACTIVE, in aes_a_dma_active()
288 iowrite32(AES_A_DMA_DMA_MODE_ACTIVE | in aes_a_dma_active_src_ll_en()
296 iowrite32(AES_A_DMA_DMA_MODE_ACTIVE | in aes_a_dma_active_dst_ll_en()
[all …]
/linux-6.12.1/drivers/rapidio/devices/
Dtsi721.c91 iowrite32(data, priv->regs + offset); in tsi721_lcwrite()
144 iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT); in tsi721_maint_dma()
173 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT); in tsi721_maint_dma()
174 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); in tsi721_maint_dma()
176 iowrite32(0, regs + TSI721_DMAC_DWRCNT); in tsi721_maint_dma()
193 iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP); in tsi721_maint_dma()
286 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, in tsi721_pw_handler()
330 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, in tsi721_pw_enable()
333 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE); in tsi721_pw_enable()
383 iowrite32(regval, in tsi721_dbell_handler()
[all …]
/linux-6.12.1/drivers/media/pci/dt3155/
Ddt3155.c40 iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2); in read_i2c_reg()
47 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); in read_i2c_reg()
70 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); in write_i2c_reg()
76 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); in write_i2c_reg()
96 iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2); in write_i2c_reg_nowait()
116 iowrite32(DIRECT_ABORT, addr + IIC_CSR1); in wait_i2c_reg()
154 iowrite32(dma_addr, pd->regs + EVEN_DMA_START); in dt3155_start_streaming()
155 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START); in dt3155_start_streaming()
156 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE); in dt3155_start_streaming()
157 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE); in dt3155_start_streaming()
[all …]
/linux-6.12.1/drivers/dma/ptdma/
Dptdma-dev.c60 iowrite32(cmd_q->qcontrol | CMD_Q_RUN, cmd_q->reg_control); in pt_start_queue()
66 iowrite32(cmd_q->qcontrol & ~CMD_Q_RUN, cmd_q->reg_control); in pt_stop_queue()
91 iowrite32(tail, cmd_q->reg_control + 0x0004); in pt_core_execute_cmd()
138 iowrite32(tail, cmd_q->reg_control + 0x0008); in pt_do_cmd_complete()
159 iowrite32(status, cmd_q->reg_control + 0x0010); in pt_check_status_trans()
195 iowrite32(CMD_CONFIG_VHB_EN, pt->io_regs + CMD_CONFIG_OFFSET); in pt_core_init()
196 iowrite32(CMD_QUEUE_PRIO, pt->io_regs + CMD_QUEUE_PRIO_OFFSET); in pt_core_init()
197 iowrite32(CMD_TIMEOUT_DISABLE, pt->io_regs + CMD_TIMEOUT_OFFSET); in pt_core_init()
198 iowrite32(CMD_CLK_GATE_CONFIG, pt->io_regs + CMD_CLK_GATE_CTL_OFFSET); in pt_core_init()
199 iowrite32(CMD_CONFIG_REQID, pt->io_regs + CMD_REQID_CONFIG_OFFSET); in pt_core_init()
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpci-rcar-gen2.c126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
143 iowrite32(status & RCAR_PCI_INT_ALLERRORS, in rcar_pci_err_irq()
166 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); in rcar_pci_setup_errirq()
204 iowrite32(val, reg + RCAR_USBCTR_REG); in rcar_pci_setup()
231 iowrite32(val, reg + RCAR_USBCTR_REG); in rcar_pci_setup()
234 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG); in rcar_pci_setup()
240 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG); in rcar_pci_setup()
243 iowrite32(window_addr | RCAR_PCIAHB_PREFETCH16, in rcar_pci_setup()
248 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG); in rcar_pci_setup()
251 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG, in rcar_pci_setup()
[all …]
/linux-6.12.1/drivers/net/ethernet/renesas/
Drcar_gen4_ptp.c41 iowrite32(addend, ptp_priv->addr + ptp_priv->offs->increment); in rcar_gen4_ptp_adjfine()
76 iowrite32(1, ptp_priv->addr + ptp_priv->offs->disable); in _rcar_gen4_ptp_settime()
77 iowrite32(0, ptp_priv->addr + ptp_priv->offs->config_t2); in _rcar_gen4_ptp_settime()
78 iowrite32(0, ptp_priv->addr + ptp_priv->offs->config_t1); in _rcar_gen4_ptp_settime()
79 iowrite32(0, ptp_priv->addr + ptp_priv->offs->config_t0); in _rcar_gen4_ptp_settime()
80 iowrite32(1, ptp_priv->addr + ptp_priv->offs->enable); in _rcar_gen4_ptp_settime()
81 iowrite32(ts->tv_sec >> 32, ptp_priv->addr + ptp_priv->offs->config_t2); in _rcar_gen4_ptp_settime()
82 iowrite32(ts->tv_sec, ptp_priv->addr + ptp_priv->offs->config_t1); in _rcar_gen4_ptp_settime()
83 iowrite32(ts->tv_nsec, ptp_priv->addr + ptp_priv->offs->config_t0); in _rcar_gen4_ptp_settime()
169 iowrite32(ptp_priv->default_addend, ptp_priv->addr + ptp_priv->offs->increment); in rcar_gen4_ptp_register()
[all …]
/linux-6.12.1/arch/arm/mach-shmobile/
Dsetup-r8a7740.c33 iowrite32(0x01600164, reg); in r8a7740_meram_workaround()
47 iowrite32(0x0, pfc_inta_ctrl); in r8a7740_init_irq_of()
54 iowrite32(0x0, intc_prio_base + 0x0); in r8a7740_init_irq_of()
55 iowrite32(0x0, intc_prio_base + 0x4); in r8a7740_init_irq_of()
56 iowrite32(0x0, intc_prio_base + 0x8); in r8a7740_init_irq_of()
57 iowrite32(0x0, intc_prio_base + 0xc); in r8a7740_init_irq_of()

12345678910>>...21