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Searched refs:intr_vsync (Results 1 – 23 of 23) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_8_0_sc8280xp.h323 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
332 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
342 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
352 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
361 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
370 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
379 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
388 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
397 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
Ddpu_9_2_x1e80100.h337 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
346 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
356 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
366 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
375 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
384 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
393 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
402 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
411 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
Ddpu_5_1_sc8180x.h325 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
334 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
344 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
356 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
365 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
374 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
Ddpu_4_0_sdm845.h261 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
269 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
277 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
285 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_3_0_msm8998.h245 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
253 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
261 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
268 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_5_2_sm7150.h226 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
235 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
245 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
255 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_7_2_sc7280.h191 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
200 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
210 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
Ddpu_7_0_sm8350.h325 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
334 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
344 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
354 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_5_0_sm8150.h318 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
327 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
337 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
347 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_9_0_sm8550.h336 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
345 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
355 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
365 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_6_0_sm8250.h301 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
310 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
320 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
330 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_3_2_sdm660.h204 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
213 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
222 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
Ddpu_10_0_sm8650.h362 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
371 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
381 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
391 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_8_1_sm8450.h343 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
352 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
362 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
372 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_3_3_sdm630.h149 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
158 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_2_sc7180.h141 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
150 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_5_4_sm6125.h167 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
176 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_4_sm6350.h173 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
182 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_3_sm6115.h97 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_5_qcm2290.h97 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_9_sm6375.h107 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h598 unsigned int intr_vsync; member
Ddpu_encoder_phys_vid.c383 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; in dpu_encoder_phys_vid_atomic_mode_set()