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Searched refs:intr_start (Results 1 – 23 of 23) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_5_4_sm6125.h39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_3_3_sdm630.h40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
Ddpu_5_2_sm7150.h42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_3_2_sdm660.h41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
Ddpu_7_0_sm8350.h44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_5_0_sm8150.h46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
66 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
71 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_9_0_sm8550.h36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_6_0_sm8250.h44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_6_4_sm6350.h39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
Ddpu_4_0_sdm845.h44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
Ddpu_3_0_msm8998.h46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
63 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
Ddpu_5_1_sc8180x.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_10_0_sm8650.h36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_8_1_sm8450.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_7_2_sc7280.h36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
Ddpu_8_0_sc8280xp.h44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_9_2_x1e80100.h35 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
Ddpu_6_2_sc7180.h36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
Ddpu_6_3_sm6115.h33 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
Ddpu_6_5_qcm2290.h33 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
Ddpu_6_9_sm6375.h34 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h486 unsigned int intr_start; member
Ddpu_encoder_phys_cmd.c150 phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; in dpu_encoder_phys_cmd_atomic_mode_set()