| /linux-6.12.1/drivers/net/ipa/ |
| D | ipa_interrupt.c | 50 static void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) in ipa_interrupt_suspend_clear_all() argument
52 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_suspend_clear_all()
74 static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_process() argument
76 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process()
100 ipa_interrupt_suspend_clear_all(interrupt); in ipa_interrupt_process()
112 struct ipa_interrupt *interrupt = dev_id; in ipa_isr_thread() local
113 struct ipa *ipa = interrupt->ipa; in ipa_isr_thread()
114 u32 enabled = interrupt->enabled; in ipa_isr_thread()
139 ipa_interrupt_process(interrupt, irq_id); in ipa_isr_thread()
162 iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg)); in ipa_interrupt_enabled_update()
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
73 #interrupt-cells = <2>;
[all …]
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| D | loongson64-2k1000.dtsi | 5 #include <dt-bindings/interrupt-controller/irq.h>
32 cpuintc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
36 compatible = "mti,cpu-interrupt-controller";
59 liointc0: interrupt-controller@1fe11400 {
66 interrupt-controller;
67 #interrupt-cells = <2>;
69 interrupt-parent = <&cpuintc>;
71 interrupt-names = "int0";
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
|
| /linux-6.12.1/arch/loongarch/boot/dts/ |
| D | loongson-2k2000.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
41 cpuintc: interrupt-controller {
42 compatible = "loongson,cpu-interrupt-controller";
43 #interrupt-cells = <1>;
44 interrupt-controller;
96 interrupt-parent = <&eiointc>;
119 interrupt-parent = <&liointc>;
124 liointc: interrupt-controller@1fe01400 {
128 interrupt-controller;
129 #interrupt-cells = <2>;
[all …]
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| D | loongson-2k0500.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
34 cpuintc: interrupt-controller {
35 compatible = "loongson,cpu-interrupt-controller";
36 #interrupt-cells = <1>;
37 interrupt-controller;
90 interrupt-parent = <&eiointc>;
100 interrupt-parent = <&eiointc>;
110 interrupt-parent = <&eiointc>;
120 interrupt-parent = <&eiointc>;
127 liointc0: interrupt-controller@1fe11400 {
[all …]
|
| /linux-6.12.1/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7346.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| D | bcm7125.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7362.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| D | bcm7420.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
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| D | bcm7435.dtsi | 42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
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| D | bcm7425.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-xp-mv78460.dtsi | 122 interrupt-names = "intx";
124 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
138 pcie1_intc: interrupt-controller {
139 interrupt-controller;
140 #interrupt-cells = <1>;
150 interrupt-names = "intx";
152 #interrupt-cells = <1>;
156 interrupt-map-mask = <0 0 0 7>;
[all …]
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| D | armada-xp-mv78260.dtsi | 101 interrupt-names = "intx";
103 #interrupt-cells = <1>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
117 pcie1_intc: interrupt-controller {
118 interrupt-controller;
119 #interrupt-cells = <1>;
129 interrupt-names = "intx";
131 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 7>;
[all …]
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| D | armada-xp-mv78230.dtsi | 86 interrupt-names = "intx";
88 #interrupt-cells = <1>;
92 interrupt-map-mask = <0 0 0 7>;
93 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
102 pcie1_intc: interrupt-controller {
103 interrupt-controller;
104 #interrupt-cells = <1>;
114 interrupt-names = "intx";
116 #interrupt-cells = <1>;
120 interrupt-map-mask = <0 0 0 7>;
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | exynos5410-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
[all …]
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| D | interrupts.txt | 1 Specifying interrupt information for devices
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
28 and the interrupt specifier.
[all …]
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| D | marvell,icu.txt | 5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
48 icu: interrupt-controller@1e0000 {
52 CP110_LABEL(icu_nsr): interrupt-controller@10 {
[all …]
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
73 - last-interrupt-source
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/tesla/ |
| D | fsd-pinctrl.dtsi | 18 interrupt-controller;
19 #interrupt-cells = <2>;
26 interrupt-controller;
27 #interrupt-cells = <2>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
42 interrupt-controller;
43 #interrupt-cells = <2>;
50 interrupt-controller;
51 #interrupt-cells = <2>;
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/img/ |
| D | boston.dts | 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
46 #interrupt-cells = <1>;
48 interrupt-parent = <&gic>;
56 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0_intc 1>,
62 pci0_intc: interrupt-controller {
63 interrupt-controller;
65 #interrupt-cells = <1>;
76 #interrupt-cells = <1>;
[all …]
|