Searched refs:internal_clk (Results 1 – 3 of 3) sorted by relevance
48 static bool internal_clk = true; variable49 module_param(internal_clk, bool, 0444);50 MODULE_PARM_DESC(internal_clk, "Use internal clock, default true (24MHz)");123 if (internal_clk) { in f81601_pci_probe()164 if (internal_clk) in f81601_pci_probe()
354 unsigned long internal_clk = 0; in omap_i2c_init() local408 internal_clk = 19200; in omap_i2c_init()410 internal_clk = 9600; in omap_i2c_init()412 internal_clk = 4000; in omap_i2c_init()424 psc = fclk_rate / internal_clk; in omap_i2c_init()432 scl = internal_clk / 400; in omap_i2c_init()444 scl = internal_clk / omap->speed; in omap_i2c_init()449 fsscll = internal_clk / (omap->speed * 2) - 7; in omap_i2c_init()450 fssclh = internal_clk / (omap->speed * 2) - 5; in omap_i2c_init()
49 u32 internal_clk; member626 state->internal_clk = state->cfg.bw->internal; in dib7000m_demod_reset()990 value = 30 * state->internal_clk * factor; in dib7000m_autosearch_start()993 value = 100 * state->internal_clk * factor; in dib7000m_autosearch_start()996 value = 500 * state->internal_clk * factor; in dib7000m_autosearch_start()