| /linux-6.12.1/arch/powerpc/lib/ |
| D | feature-fixups.c | 141 static int do_patch_fixups(long *start, long *end, unsigned int *instrs, int num) in do_patch_fixups() argument
149 if (!is_fixup_addr_valid(dest, sizeof(*instrs) * num)) in do_patch_fixups()
155 patch_instruction(dest + j, ppc_inst(instrs[j])); in do_patch_fixups()
162 static int do_patch_entry_fixups(long *start, long *end, unsigned int *instrs, in do_patch_entry_fixups() argument
170 if (!is_fixup_addr_valid(dest, sizeof(*instrs) * 3)) in do_patch_entry_fixups()
177 patch_instruction(dest, ppc_inst(instrs[0])); in do_patch_entry_fixups()
178 patch_instruction(dest + 2, ppc_inst(instrs[2])); in do_patch_entry_fixups()
181 patch_instruction(dest + 1, ppc_inst(instrs[1])); in do_patch_entry_fixups()
182 patch_instruction(dest + 2, ppc_inst(instrs[2])); in do_patch_entry_fixups()
183 patch_instruction(dest, ppc_inst(instrs[0])); in do_patch_entry_fixups()
[all …]
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| /linux-6.12.1/drivers/mtd/nand/raw/ |
| D | nand_base.c | 1146 struct nand_op_instr instrs[] = { in nand_sp_exec_read_page_op() local
1153 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_sp_exec_read_page_op()
1161 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; in nand_sp_exec_read_page_op()
1164 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; in nand_sp_exec_read_page_op()
1175 instrs[1].ctx.addr.naddrs++; in nand_sp_exec_read_page_op()
1188 struct nand_op_instr instrs[] = { in nand_lp_exec_read_page_op() local
1196 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_lp_exec_read_page_op()
1212 instrs[1].ctx.addr.naddrs++; in nand_lp_exec_read_page_op()
1401 struct nand_op_instr instrs[] = { in nand_read_param_page_op() local
1409 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_read_param_page_op()
[all …]
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| D | fsl_upm.c | 148 ret = func_exec_instr(chip, &op->instrs[i]); in fun_exec_op()
152 if (op->instrs[i].delay_ns) in fun_exec_op()
153 ndelay(op->instrs[i].delay_ns); in fun_exec_op()
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| D | arasan-nand-controller.c | 615 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
768 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_RNDOUT && in anfc_data_read_type_exec()
769 subop->instrs[2].ctx.cmd.opcode == NAND_CMD_RNDOUTSTART) in anfc_data_read_type_exec()
820 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) in anfc_status_type_exec()
828 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); in anfc_status_type_exec()
917 instr = &op->instrs[op_id]; in anfc_check_op()
950 op->instrs[0].type == NAND_OP_CMD_INSTR && in anfc_check_op()
951 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && in anfc_check_op()
952 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in anfc_check_op()
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| D | nand_hynix.c | 74 struct nand_op_instr instrs[] = { in hynix_nand_cmd_op() local
77 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_cmd_op()
92 struct nand_op_instr instrs[] = { in hynix_nand_reg_write_op() local
96 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_reg_write_op()
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| D | gpio.c | 151 ret = gpio_nand_exec_instr(chip, &op->instrs[i]); in gpio_nand_exec_op()
155 if (op->instrs[i].delay_ns) in gpio_nand_exec_op()
156 ndelay(op->instrs[i].delay_ns); in gpio_nand_exec_op()
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| D | nand_toshiba.c | 37 struct nand_op_instr instrs[] = { in toshiba_nand_benand_read_eccstatus_op() local
42 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in toshiba_nand_benand_read_eccstatus_op()
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| D | nand_macronix.c | 264 struct nand_op_instr instrs[] = { in nand_power_down_op() local
268 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_power_down_op()
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| D | ams-delta.c | 151 for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) { in gpio_nand_exec_op()
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| D | technologic-nand-controller.c | 122 ret = ts72xx_nand_exec_instr(chip, &op->instrs[i]); in ts72xx_nand_exec_op()
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| D | cadence-nand-controller.c | 2048 instr = &subop->instrs[op_id]; in cadence_nand_cmd_opcode()
2082 instr = &subop->instrs[op_id]; in cadence_nand_cmd_address()
2116 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) { in cadence_nand_cmd_erase()
2123 instr = &subop->instrs[1]; in cadence_nand_cmd_erase()
2142 .instrs = &subop->instrs[op_id], in cadence_nand_cmd_erase()
2163 instr = &subop->instrs[op_id]; in cadence_nand_cmd_data()
2229 const struct nand_op_instr *instr = &subop->instrs[op_id]; in cadence_nand_cmd_waitrdy()
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| D | diskonchip.c | 348 struct nand_op_instr instrs[] = { in doc200x_readid() local
354 struct nand_operation op = NAND_OPERATION(cs, instrs); in doc200x_readid()
583 doc200x_exec_instr(this, &op->instrs[i]); in doc200x_exec_op()
655 doc2001plus_exec_instr(this, &op->instrs[i]); in doc2001plus_exec_op()
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| D | au1550nd.c | 227 ret = au1550nd_exec_instr(this, &op->instrs[i]); in au1550nd_exec_op()
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| D | cs553x_nand.c | 206 ret = cs553x_exec_instr(cs553x, &op->instrs[i]); in cs553x_exec_op()
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| D | qcom_nandc.c | 2604 instr = &subop->instrs[op_id]; in qcom_parse_instructions()
2802 int instrs = 1; in qcom_misc_cmd_type_exec() local
2817 instrs = 3; in qcom_misc_cmd_type_exec()
2832 write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
2981 instr = &op->instrs[op_id]; in qcom_check_op()
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| D | mxic_nand.c | 402 instr = &op->instrs[op_id]; in mxic_nfc_exec_op()
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| D | davinci_nand.c | 759 ret = davinci_nand_exec_instr(info, &op->instrs[i]); in davinci_nand_exec_op()
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| D | intel-nand-controller.c | 526 instr = &op->instrs[op_id]; in ebu_nand_exec_op()
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| D | meson_nand.c | 1010 instr = &op->instrs[op_id]; in meson_nfc_check_op()
1047 instr = &op->instrs[op_id]; in meson_nfc_exec_op()
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| D | marvell_nand.c | 1727 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1909 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1956 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
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| /linux-6.12.1/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_nand_drv.c | 327 ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]); in ingenic_nand_exec_op()
331 if (op->instrs[i].delay_ns) in ingenic_nand_exec_op()
332 ndelay(op->instrs[i].delay_ns); in ingenic_nand_exec_op()
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| /linux-6.12.1/include/linux/mtd/ |
| D | rawnand.h | 863 const struct nand_op_instr *instrs; member
1016 const struct nand_op_instr *instrs; member
1023 .instrs = _instrs, \
1031 .instrs = _instrs, \
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| /linux-6.12.1/drivers/mtd/nand/raw/brcmnand/ |
| D | brcmnand.c | 2411 const struct nand_op_instr *instr = &op->instrs[i]; in brcmnand_exec_instr()
2423 ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR)); in brcmnand_exec_instr()
2469 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_status()
2470 op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS && in brcmnand_op_is_status()
2471 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in brcmnand_op_is_status()
2480 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_reset()
2481 op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET && in brcmnand_op_is_reset()
2482 op->instrs[1].type == NAND_OP_WAITRDY_INSTR) in brcmnand_op_is_reset()
2502 status = op->instrs[1].ctx.data.buf.in; in brcmnand_exec_op()
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| /linux-6.12.1/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); in atmel_smc_nand_exec_op()
643 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
663 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
681 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()
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| /linux-6.12.1/tools/arch/x86/kcpuid/ |
| D | cpuid.csv | 215 7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instrs
216 7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instrs
221 … 7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instrs
226 … 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instrs group 2
229 7, 0, ecx, 9, vaes , Vector AES instrs
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