Searched refs:inst_offset (Results 1 – 4 of 4) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
D | dm_services.h | 151 #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ argument 152 …dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __… 154 #define dm_read_reg_soc15(ctx, reg, inst_offset) \ argument 155 dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) 157 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument 158 …date_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ 161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument 162 …et_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v9_4_3.c | 4590 uint32_t xcc_id, xcc_offset, inst_offset; in gfx_v9_4_3_ip_print() local 4624 inst_offset = 0; in gfx_v9_4_3_ip_print() 4636 [xcc_offset + inst_offset + in gfx_v9_4_3_ip_print() 4639 inst_offset += reg_count; in gfx_v9_4_3_ip_print() 4651 uint32_t xcc_id, xcc_offset, inst_offset; in gfx_v9_4_3_ip_dump() local 4680 inst_offset = 0; in gfx_v9_4_3_ip_dump() 4691 inst_offset + reg] = in gfx_v9_4_3_ip_dump() 4696 inst_offset += reg_count; in gfx_v9_4_3_ip_dump()
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/linux-6.12.1/drivers/gpu/drm/amd/amdkfd/ |
D | cwsr_trap_handler_gfx10.asm | 570 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 V_COHERENCE
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
D | dcn10_hwseq.c | 1016 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()
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