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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dinit.c42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
59 init_exec(struct nvbios_init *init) in init_exec() argument
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
65 init_exec_set(struct nvbios_init *init, bool exec) in init_exec_set() argument
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
72 init_exec_inv(struct nvbios_init *init) in init_exec_inv() argument
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dbase.c30 nvkm_devinit_mmio(struct nvkm_devinit *init, u32 addr) in nvkm_devinit_mmio() argument
32 if (init->func->mmio) in nvkm_devinit_mmio()
33 addr = init->func->mmio(init, addr); in nvkm_devinit_mmio()
38 nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz) in nvkm_devinit_pll_set() argument
40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
44 nvkm_devinit_meminit(struct nvkm_devinit *init) in nvkm_devinit_meminit() argument
46 if (init->func->meminit) in nvkm_devinit_meminit()
47 init->func->meminit(init); in nvkm_devinit_meminit()
51 nvkm_devinit_disable(struct nvkm_devinit *init) in nvkm_devinit_disable() argument
53 if (init && init->func->disable) in nvkm_devinit_disable()
[all …]
Dgm200.c33 pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec) in pmu_code() argument
35 struct nvkm_device *device = init->base.subdev.device; in pmu_code()
53 pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len) in pmu_data() argument
55 struct nvkm_device *device = init->base.subdev.device; in pmu_data()
65 pmu_args(struct nv50_devinit *init, u32 argp, u32 argi) in pmu_args() argument
67 struct nvkm_device *device = init->base.subdev.device; in pmu_args()
74 pmu_exec(struct nv50_devinit *init, u32 init_addr) in pmu_exec() argument
76 struct nvkm_device *device = init->base.subdev.device; in pmu_exec()
83 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
86 struct nvkm_subdev *subdev = &init->base.subdev; in pmu_load()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgf100.c28 #define pack_for_each_init(init, pack, head) \ argument
29 for (pack = head; pack && pack->init; pack++) \
30 for (init = pack->init; init && init->count; init++)
37 const struct nvkm_therm_clkgate_init *init; in gf100_clkgate_init() local
40 pack_for_each_init(init, pack, p) { in gf100_clkgate_init()
41 next = init->addr + init->count * 8; in gf100_clkgate_init()
42 addr = init->addr; in gf100_clkgate_init()
45 init->addr, init->count, init->data); in gf100_clkgate_init()
48 addr, init->data); in gf100_clkgate_init()
49 nvkm_wr32(device, addr, init->data); in gf100_clkgate_init()
/linux-6.12.1/arch/um/drivers/
Dumcast_kern.c31 struct umcast_init *init = data; in umcast_init() local
35 dpri->addr = init->addr; in umcast_init()
36 dpri->lport = init->lport; in umcast_init()
37 dpri->rport = init->rport; in umcast_init()
38 dpri->unicast = init->unicast; in umcast_init()
39 dpri->ttl = init->ttl; in umcast_init()
64 .init = umcast_init,
72 struct umcast_init *init = data; in mcast_setup() local
76 *init = ((struct umcast_init) in mcast_setup()
81 remain = split_if_spec(str, mac_out, &init->addr, &port_str, &ttl_str, in mcast_setup()
[all …]
/linux-6.12.1/drivers/clk/stm32/
Dclk-stm32mp25.c484 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc12", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
491 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc12", adc12_src, &clk_stm32_composite_ops, 0),
496 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
503 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc3", adc3_src, &clk_stm32_composite_ops, 0),
509 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
514 .hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),
520 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cci", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
526 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),
531 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),
536 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),
[all …]
/linux-6.12.1/drivers/clk/socfpga/
Dclk-periph-s10.c106 struct clk_init_data init; in s10_register_periph() local
117 init.name = name; in s10_register_periph()
118 init.ops = &peri_c_clk_ops; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
122 init.parent_names = parent_name ? &parent_name : NULL; in s10_register_periph()
123 if (init.parent_names == NULL) in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
126 periph_clk->hw.hw.init = &init; in s10_register_periph()
142 struct clk_init_data init; in n5x_register_periph() local
[all …]
Dclk-pll-s10.c195 struct clk_init_data init; in s10_register_pll() local
206 init.ops = &clk_boot_ops; in s10_register_pll()
208 init.ops = &clk_pll_ops; in s10_register_pll()
210 init.name = name; in s10_register_pll()
211 init.flags = clks->flags; in s10_register_pll()
213 init.num_parents = clks->num_parents; in s10_register_pll()
214 init.parent_names = NULL; in s10_register_pll()
215 init.parent_data = clks->parent_data; in s10_register_pll()
216 pll_clk->hw.hw.init = &init; in s10_register_pll()
235 struct clk_init_data init; in agilex_register_pll() local
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_module.c53 int (*init)(void); member
56 { .init = i915_check_nomodeset },
57 { .init = i915_active_module_init,
59 { .init = i915_context_module_init,
61 { .init = i915_gem_context_module_init,
63 { .init = i915_objects_module_init,
65 { .init = i915_request_module_init,
67 { .init = i915_scheduler_module_init,
69 { .init = i915_vma_module_init,
71 { .init = i915_vma_resource_module_init,
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgcc-msm8998.c43 .hw.init = &(struct clk_init_data){
57 .clkr.hw.init = &(struct clk_init_data){
70 .clkr.hw.init = &(struct clk_init_data){
83 .clkr.hw.init = &(struct clk_init_data){
96 .clkr.hw.init = &(struct clk_init_data){
114 .hw.init = &(struct clk_init_data){
128 .clkr.hw.init = &(struct clk_init_data){
141 .clkr.hw.init = &(struct clk_init_data){
154 .clkr.hw.init = &(struct clk_init_data){
167 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-x1e80100.c57 .hw.init = &(const struct clk_init_data) {
80 .clkr.hw.init = &(const struct clk_init_data) {
96 .hw.init = &(const struct clk_init_data) {
113 .hw.init = &(const struct clk_init_data) {
130 .hw.init = &(const struct clk_init_data) {
147 .hw.init = &(const struct clk_init_data) {
329 .clkr.hw.init = &(const struct clk_init_data) {
344 .clkr.hw.init = &(const struct clk_init_data) {
359 .clkr.hw.init = &(const struct clk_init_data) {
379 .clkr.hw.init = &(const struct clk_init_data) {
[all …]
Dgcc-sc8280xp.c118 .hw.init = &(const struct clk_init_data) {
139 .clkr.hw.init = &(const struct clk_init_data) {
155 .hw.init = &(const struct clk_init_data) {
170 .hw.init = &(const struct clk_init_data) {
185 .hw.init = &(const struct clk_init_data) {
200 .hw.init = &(const struct clk_init_data) {
215 .hw.init = &(const struct clk_init_data) {
453 .hw.init = &(const struct clk_init_data) {
468 .hw.init = &(const struct clk_init_data) {
557 .hw.init = &(const struct clk_init_data) {
[all …]
Dgcc-msm8996.c38 .hw.init = &(struct clk_init_data){
54 .hw.init = &(struct clk_init_data){
68 .hw.init = &(struct clk_init_data){
81 .clkr.hw.init = &(struct clk_init_data){
96 .hw.init = &(struct clk_init_data){
113 .hw.init = &(struct clk_init_data){
131 .hw.init = &(struct clk_init_data){
145 .clkr.hw.init = &(struct clk_init_data){
260 .clkr.hw.init = &(struct clk_init_data){
278 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-sm8250.c41 .hw.init = &(struct clk_init_data){
64 .clkr.hw.init = &(struct clk_init_data){
80 .hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
199 .clkr.hw.init = &(struct clk_init_data){
223 .clkr.hw.init = &(struct clk_init_data){
237 .clkr.hw.init = &(struct clk_init_data){
251 .clkr.hw.init = &(struct clk_init_data){
271 .clkr.hw.init = &(struct clk_init_data){
285 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-apq8084.c46 .clkr.hw.init = &(struct clk_init_data){
59 .hw.init = &(struct clk_init_data){
77 .clkr.hw.init = &(struct clk_init_data){
90 .hw.init = &(struct clk_init_data){
108 .clkr.hw.init = &(struct clk_init_data){
121 .hw.init = &(struct clk_init_data){
197 .clkr.hw.init = &(struct clk_init_data){
209 .clkr.hw.init = &(struct clk_init_data){
221 .clkr.hw.init = &(struct clk_init_data){
242 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-msm8917.c60 .hw.init = &(struct clk_init_data){
77 .hw.init = &(struct clk_init_data) {
91 .clkr.hw.init = &(struct clk_init_data){
120 .hw.init = &(struct clk_init_data){
134 .clkr.hw.init = &(struct clk_init_data){
151 .hw.init = &(struct clk_init_data){
165 .clkr.hw.init = &(struct clk_init_data){
183 .clkr.hw.init = &(struct clk_init_data){
196 .hw.init = &(struct clk_init_data){
262 .clkr.hw.init = &(struct clk_init_data) {
[all …]
Dgcc-msm8976.c63 .clkr.hw.init = &(struct clk_init_data){
76 .hw.init = &(struct clk_init_data){
96 .clkr.hw.init = &(struct clk_init_data){
109 .hw.init = &(struct clk_init_data){
133 .clkr.hw.init = &(struct clk_init_data) {
146 .hw.init = &(struct clk_init_data){
180 .clkr.hw.init = &(struct clk_init_data){
193 .hw.init = &(struct clk_init_data){
211 .clkr.hw.init = &(struct clk_init_data){
224 .hw.init = &(struct clk_init_data){
[all …]
Decpricc-qdu1000.c68 .hw.init = &(const struct clk_init_data) {
98 .hw.init = &(const struct clk_init_data) {
178 .clkr.hw.init = &(const struct clk_init_data) {
198 .clkr.hw.init = &(const struct clk_init_data) {
218 .clkr.hw.init = &(const struct clk_init_data) {
237 .clkr.hw.init = &(const struct clk_init_data) {
258 .clkr.hw.init = &(const struct clk_init_data) {
278 .clkr.hw.init = &(const struct clk_init_data) {
292 .clkr.hw.init = &(const struct clk_init_data) {
306 .clkr.hw.init = &(const struct clk_init_data) {
[all …]
Dgcc-mdm9607.c42 .hw.init = &(struct clk_init_data)
57 .clkr.hw.init = &(struct clk_init_data)
84 .clkr.hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
125 .hw.init = &(struct clk_init_data)
140 .clkr.hw.init = &(struct clk_init_data)
187 .clkr.hw.init = &(struct clk_init_data){
203 .clkr.hw.init = &(struct clk_init_data){
216 .hw.init = &(struct clk_init_data){
248 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-sm8450.c45 .hw.init = &(struct clk_init_data){
68 .clkr.hw.init = &(struct clk_init_data){
84 .hw.init = &(struct clk_init_data){
101 .hw.init = &(struct clk_init_data){
225 .hw.init = &(struct clk_init_data){
242 .hw.init = &(struct clk_init_data){
254 .hw.init = &(struct clk_init_data){
271 .hw.init = &(struct clk_init_data){
286 .hw.init = &(struct clk_init_data){
301 .hw.init = &(struct clk_init_data){
[all …]
Dgcc-ipq9574.c75 .hw.init = &(const struct clk_init_data) {
87 .hw.init = &(const struct clk_init_data) {
101 .clkr.hw.init = &(const struct clk_init_data) {
117 .hw.init = &(const struct clk_init_data) {
130 .clkr.hw.init = &(const struct clk_init_data) {
146 .hw.init = &(const struct clk_init_data) {
159 .clkr.hw.init = &(const struct clk_init_data) {
174 .hw.init = &(const struct clk_init_data) {
422 .clkr.hw.init = &(const struct clk_init_data) {
440 .clkr.hw.init = &(const struct clk_init_data) {
[all …]
Dgcc-sm8550.c61 .hw.init = &(struct clk_init_data){
84 .clkr.hw.init = &(struct clk_init_data){
100 .hw.init = &(struct clk_init_data){
117 .hw.init = &(struct clk_init_data){
134 .hw.init = &(struct clk_init_data){
286 .hw.init = &(struct clk_init_data){
303 .hw.init = &(struct clk_init_data){
315 .hw.init = &(struct clk_init_data){
332 .hw.init = &(struct clk_init_data){
347 .hw.init = &(struct clk_init_data){
[all …]
/linux-6.12.1/rust/kernel/
Dinit.rs277 let mut $var = ::core::pin::pin!($crate::init::__internal::StackInit$(::<$t>)?::uninit());
278 let mut $var = match $crate::init::__internal::StackInit::init($var, val) {
353 let mut $var = ::core::pin::pin!($crate::init::__internal::StackInit$(::<$t>)?::uninit());
354 let mut $var = $crate::init::__internal::StackInit::init($var, val);
358 let mut $var = ::core::pin::pin!($crate::init::__internal::StackInit$(::<$t>)?::uninit());
359 let mut $var = $crate::init::__internal::StackInit::init($var, val)?;
664 macro_rules! init { macro
800 let data = unsafe { <$ty as $crate::init::__internal::HasPinData>::__pin_data() };
801 let init = $crate::init::__internal::AlwaysFail::<$field_ty>::new(); localVariable
803 unsafe { data.$field(ptr, init) }.ok();
[all …]
/linux-6.12.1/arch/arm/mach-omap1/
Dclock_data.c77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
[all …]
/linux-6.12.1/drivers/clk/
Dclk-versaclock5.c947 struct clk_init_data init; in vc5_probe() local
1000 memset(&init, 0, sizeof(init)); in vc5_probe()
1004 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1012 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1017 parent_names[init.num_parents++] = in vc5_probe()
1021 if (!init.num_parents) in vc5_probe()
1032 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node); in vc5_probe()
1033 if (!init.name) { in vc5_probe()
1038 init.ops = &vc5_mux_ops; in vc5_probe()
1039 init.flags = 0; in vc5_probe()
[all …]

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