Home
last modified time | relevance | path

Searched refs:imx_clk_hw_fixup_mux (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/imx/
Dclk-imx6sl.c304 …hws[IMX6SL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_se… in imx6sl_clocks_init()
305 …hws[IMX6SL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_se… in imx6sl_clocks_init()
306 …hws[IMX6SL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_se… in imx6sl_clocks_init()
307 …hws[IMX6SL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_se… in imx6sl_clocks_init()
308 …hws[IMX6SL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels… in imx6sl_clocks_init()
309 …hws[IMX6SL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels… in imx6sl_clocks_init()
310 …hws[IMX6SL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels… in imx6sl_clocks_init()
311 …hws[IMX6SL_CLK_PERCLK_SEL] = imx_clk_hw_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_s… in imx6sl_clocks_init()
Dclk-imx6q.c691 …hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sel… in imx6q_clocks_init()
692 …hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sel… in imx6q_clocks_init()
693 …hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sel… in imx6q_clocks_init()
694 …hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_s… in imx6q_clocks_init()
695 …hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_s… in imx6q_clocks_init()
696 …hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_s… in imx6q_clocks_init()
697 …hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_s… in imx6q_clocks_init()
699 …hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_s… in imx6q_clocks_init()
700 …hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_s… in imx6q_clocks_init()
Dclk-fixup-mux.c68 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, in imx_clk_hw_fixup_mux() function
Dclk.h333 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,