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Searched refs:icache (Results 1 – 25 of 51) sorted by relevance

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/linux-6.12.1/arch/mips/mm/
Dc-octeon.c182 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
185 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
188 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
202 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
203 c->icache.sets = 8; in probe_octeon()
204 c->icache.ways = 37; in probe_octeon()
205 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
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Dc-r4k.c231 unsigned long end = start + current_cpu_data.icache.waysize; in tx49_blast_icache32()
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; in tx49_blast_icache32()
233 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
234 current_cpu_data.icache.waybit; in tx49_blast_icache32()
1009 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1010 c->icache.ways = 2; in probe_pcache()
1011 c->icache.waybit = __ffs(icache_size/2); in probe_pcache()
1023 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1024 c->icache.ways = 2; in probe_pcache()
1025 c->icache.waybit= 0; in probe_pcache()
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/linux-6.12.1/arch/sh/kernel/cpu/sh4/
Dprobe.c35 boot_cpu_data.icache.way_incr = (1 << 13); in cpu_probe()
36 boot_cpu_data.icache.entry_shift = 5; in cpu_probe()
37 boot_cpu_data.icache.sets = 256; in cpu_probe()
38 boot_cpu_data.icache.ways = 1; in cpu_probe()
39 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
202 if (boot_cpu_data.icache.ways > 1) { in cpu_probe()
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/linux-6.12.1/arch/mips/include/asm/
Dr4kcache.h245 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
248 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
249 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
252 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
255 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
279 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
282 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
285 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
305 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
307 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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Dcpu-features.h249 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
255 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
274 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
511 #define cpu_icache_line_size() cpu_data[0].icache.linesz
/linux-6.12.1/arch/sh/kernel/cpu/
Dinit.c209 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); in detect_cache_shape()
306 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - in cpu_init()
307 current_cpu_data.icache.linesz; in cpu_init()
309 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * in cpu_init()
310 current_cpu_data.icache.linesz; in cpu_init()
Dproc.c111 if (c->icache.flags & SH_CACHE_COMBINED) { in show_cpuinfo()
113 show_cacheinfo(m, "cache", c->icache); in show_cpuinfo()
116 show_cacheinfo(m, "icache", c->icache); in show_cpuinfo()
/linux-6.12.1/Documentation/arch/riscv/
Dcmodx.rst9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
15 migration occurs after the userspace synchronized the icache and instruction
16 storage with fence.i, the icache on the new hart will no longer be clean. This
19 instruction storage and icache.
23 userspace. The syscall performs a one-off icache flushing operation. The prctl
24 changes the Linux ABI to allow userspace to emit icache flushing operations.
26 As an aside, "deferred" icache flushes can sometimes be triggered in the kernel.
30 an icache flush, this deferred icache flush will be skipped as it is redundant.
/linux-6.12.1/arch/sh/mm/
Dcache.c268 boot_cpu_data.icache.ways, in emit_cache_params()
269 boot_cpu_data.icache.sets, in emit_cache_params()
270 boot_cpu_data.icache.way_incr); in emit_cache_params()
272 boot_cpu_data.icache.entry_mask, in emit_cache_params()
273 boot_cpu_data.icache.alias_mask, in emit_cache_params()
274 boot_cpu_data.icache.n_aliases); in emit_cache_params()
307 compute_alias(&boot_cpu_data.icache); in cpu_cache_init()
Dcache-shx3.c28 if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { in shx3_cache_init()
31 boot_cpu_data.icache.n_aliases = 0; in shx3_cache_init()
Dcache-sh4.c74 cpu_data->icache.entry_mask); in sh4_flush_icache_range()
77 n = boot_cpu_data.icache.n_aliases; in sh4_flush_icache_range()
78 for (i = 0; i < cpu_data->icache.ways; i++) { in sh4_flush_icache_range()
81 icacheaddr += cpu_data->icache.way_incr; in sh4_flush_icache_range()
Dcache-debugfs.c52 cache = &current_cpu_data.icache; in cache_debugfs_show()
/linux-6.12.1/Documentation/devicetree/bindings/nios2/
Dnios2.txt18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
47 icache-line-size = <32>;
49 icache-size = <32768>;
/linux-6.12.1/arch/mips/kernel/
Dcacheinfo.c36 leaves += (c->icache.waysize) ? 2 : 1; in init_cache_level()
84 if (c->icache.waysize) { in populate_cache_leaves()
89 populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); in populate_cache_leaves()
/linux-6.12.1/arch/powerpc/perf/
Dpower8-pmu.c138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
Dpower9-pmu.c181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
Dpower10-pmu.c137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
/linux-6.12.1/arch/nios2/boot/dts/
D3c120_devboard.dts28 icache-line-size = <32>;
30 icache-size = <32768>;
D10m50_devboard.dts39 icache-line-size = <32>;
40 icache-size = <32768>;
/linux-6.12.1/arch/microblaze/boot/dts/
Dsystem.dts55 xlnx,allow-icache-wr = <0x1>;
81 xlnx,icache-always-used = <0x1>;
82 xlnx,icache-line-len = <0x4>;
83 xlnx,icache-use-fsl = <0x1>;
111 xlnx,use-icache = <0x1>;
/linux-6.12.1/arch/powerpc/kernel/
Dcacheinfo.c372 struct cache *dcache, *icache; in cache_do_one_devnode_split() local
378 icache = new_cache(CACHE_TYPE_INSTRUCTION, level, node, group_id); in cache_do_one_devnode_split()
380 if (!dcache || !icache) in cache_do_one_devnode_split()
383 dcache->next_local = icache; in cache_do_one_devnode_split()
388 release_cache(icache); in cache_do_one_devnode_split()
/linux-6.12.1/arch/sh/kernel/cpu/sh2/
Dprobe.c69 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-6.12.1/arch/sh/kernel/cpu/sh2a/
Dprobe.c56 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-6.12.1/arch/sh/kernel/cpu/sh3/
Dprobe.c105 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/linux-6.12.1/arch/sh/include/asm/
Dprocessor.h77 struct cache_info icache; /* Primary I-cache */ member

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