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Searched refs:i915_ggtt_offset (Results 1 – 25 of 44) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_lrc.c870 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in init_wa_bb_regs()
879 i915_ggtt_offset(wa_ctx->vma) + in init_wa_bb_regs()
1042 return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce); in lrc_indirect_bb()
1264 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
1292 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
1308 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
1530 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor()
1543 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in lrc_update_regs()
1587 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in lrc_check_regs()
1591 i915_ggtt_offset(ring->vma)); in lrc_check_regs()
[all …]
Dselftest_lrc.c81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
445 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
448 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
452 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
567 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
598 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
740 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
1108 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1241 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1589 *cs++ = i915_ggtt_offset(ce->state) + in emit_wabb_ctx_canary()
Dintel_timeline.c209 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno()
354 *hwsp = i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_read_hwsp()
Dintel_context_sseu.c27 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
Dselftest_mocs.c235 offset = i915_ggtt_offset(vma); in check_mocs_engine()
240 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
Dintel_ring_submission.c139 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
223 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
271 i915_ggtt_offset(ring->vma)); in xcs_resume()
760 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
767 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
Dselftest_timeline.c854 w->addr = i915_ggtt_offset(vma); in setup_watcher()
889 w->addr = i915_ggtt_offset(w->vma); in create_watcher()
903 GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size); in check_watcher()
916 end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map); in check_watcher()
Dintel_renderstate.c89 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
Dintel_gt.h158 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
Dgen8_engine_cs.c418 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address()
748 return i915_ggtt_offset(rq->context->state) + in hold_switchout_semaphore_offset()
Dselftest_execlists.c835 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
840 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
909 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
1054 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1620 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1631 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1670 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
3229 *cs++ = i915_ggtt_offset(global); in preempt_user()
4246 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
/linux-6.12.1/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c224 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
225 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
230 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
234 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/linux-6.12.1/drivers/gpu/drm/xe/compat-i915-headers/
Di915_vma.h30 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
/linux-6.12.1/drivers/gpu/drm/i915/selftests/
Di915_perf.c245 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay()
352 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr()
378 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dsb_buffer.c15 return i915_ggtt_offset(dsb_buf->vma); in intel_dsb_buffer_ggtt_offset()
Dintel_fbdev_fb.c90 (unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma)); in intel_fbdev_fb_fill_info()
Dintel_overlay.c850 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
867 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
869 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1376 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
Dintel_hdcp_gsc.c239 addr_in = i915_ggtt_offset(hdcp_message->vma); in intel_hdcp_gsc_msg_send()
Dintel_plane_initial.c259 i915_ggtt_offset(vma), plane_config->base); in initial_plane_vma()
/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_gsc_fw.c265 u32 offset = i915_ggtt_offset(gsc->local); in emit_gsc_fw_load()
406 offset = i915_ggtt_offset(vma); in gsc_fw_query_compatibility_version()
Dintel_huc_fw.c42 pkt_offset = i915_ggtt_offset(huc->heci_pkt); in intel_huc_fw_auth_via_gsccs()
Dintel_guc.h419 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
Dintel_gsc_proxy.c127 u64 addr_in = i915_ggtt_offset(gsc->proxy.vma); in proxy_send_to_gsc()
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_perf.c544 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked()
732 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
1042 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1381 i915_ggtt_offset(scratch)); in gen12_guc_sw_ctx_id()
1553 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1699 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1744 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
1797 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen12_init_oa_buffer()
1925 *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d; in save_restore_register()
2073 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/gem/
Di915_gem_tiling.c175 if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment)) in i915_vma_fence_prepare()

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