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Searched refs:hwpwm (Results 1 – 25 of 50) sorted by relevance

12

/linux-6.12.1/drivers/pwm/
Dpwm-jz4740.c56 if (!jz4740_pwm_can_use_chn(chip, pwm->hwpwm)) in jz4740_pwm_request()
59 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); in jz4740_pwm_request()
74 jz->clk[pwm->hwpwm] = clk; in jz4740_pwm_request()
82 struct clk *clk = jz->clk[pwm->hwpwm]; in jz4740_pwm_free()
93 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_enable()
96 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); in jz4740_pwm_enable()
109 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); in jz4740_pwm_disable()
110 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); in jz4740_pwm_disable()
117 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_disable()
120 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); in jz4740_pwm_disable()
[all …]
Dpwm-vt8500.c108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
109 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
112 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
115 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
120 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all …]
Dpwm-sunplus.c68 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
72 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
100 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); in sunplus_pwm_apply()
104 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
106 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
109 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
112 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
[all …]
Dpwm-sun4i.c129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
158 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
[all …]
Dpwm-bcm-iproc.c79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
84 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
97 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
102 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
106 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
154 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
158 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
159 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
163 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
164 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all …]
Dpwm-sprd.c75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
87 pwm->hwpwm); in sprd_pwm_get_state()
91 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
105 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
110 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
126 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
158 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all …]
Dpwm-atmel.c246 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
248 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
253 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
262 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
264 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
274 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
276 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
284 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
306 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
[all …]
Dpwm-dwc-core.c70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in __dwc_pwm_configure_timer()
78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); in __dwc_pwm_configure_timer()
79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); in __dwc_pwm_configure_timer()
88 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); in __dwc_pwm_configure_timer()
93 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); in __dwc_pwm_configure_timer()
112 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in dwc_pwm_apply()
129 ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); in dwc_pwm_get_state()
130 ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); in dwc_pwm_get_state()
131 ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); in dwc_pwm_get_state()
Dpwm-stmpe.c47 pwm->hwpwm); in stmpe_24xx_pwm_enable()
51 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
56 pwm->hwpwm); in stmpe_24xx_pwm_enable()
73 pwm->hwpwm); in stmpe_24xx_pwm_disable()
77 value = ret & ~BIT(pwm->hwpwm); in stmpe_24xx_pwm_disable()
82 pwm->hwpwm); in stmpe_24xx_pwm_disable()
117 pin = pwm->hwpwm; in stmpe_24xx_pwm_config()
128 pwm->hwpwm); in stmpe_24xx_pwm_config()
134 switch (pwm->hwpwm) { in stmpe_24xx_pwm_config()
153 pwm->hwpwm, duty_ns, period_ns); in stmpe_24xx_pwm_config()
[all …]
Dpwm-microchip-core.c81 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
82 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()
89 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); in mchp_core_pwm_enable()
90 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; in mchp_core_pwm_enable()
97 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) in mchp_core_pwm_enable()
180 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
181 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
310 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); in mchp_core_pwm_apply_locked()
367 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_apply()
386 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_get_state()
[all …]
Dpwm-bcm2835.c43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_free()
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm)); in bcm2835_pwm_apply()
100 writel(val, pc->base + DUTY(pwm->hwpwm)); in bcm2835_pwm_apply()
106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
Dpwm-twl.c82 base = pwm->hwpwm * 3; in twl_pwm_config()
106 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
112 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
136 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
142 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
158 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
196 if (pwm->hwpwm == 1) in twl4030_pwm_free()
228 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
229 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
251 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_disable()
[all …]
Dpwm-visconti.c52 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
98 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_apply()
99 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_apply()
100 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
111 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_get_state()
112 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_get_state()
113 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_get_state()
Dpwm-berlin.c100 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
105 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
107 berlin_pwm_writel(bpc, pwm->hwpwm, duty, BERLIN_PWM_DUTY); in berlin_pwm_config()
108 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT); in berlin_pwm_config()
120 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
127 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
137 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); in berlin_pwm_enable()
139 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_enable()
150 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); in berlin_pwm_disable()
152 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_disable()
Dpwm-sti.c184 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || in sti_pwm_config()
185 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || in sti_pwm_config()
222 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); in sti_pwm_config()
228 set_bit(pwm->hwpwm, &pc->configured); in sti_pwm_config()
267 pwm->hwpwm, ret); in sti_pwm_enable()
302 clear_bit(pwm->hwpwm, &pc->configured); in sti_pwm_free()
309 struct sti_cpt_ddata *ddata = &pc->ddata[pwm->hwpwm]; in sti_pwm_capture()
315 if (pwm->hwpwm >= pc->cpt_num_devs) { in sti_pwm_capture()
316 dev_err(dev, "device %u is not valid\n", pwm->hwpwm); in sti_pwm_capture()
324 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); in sti_pwm_capture()
[all …]
Dpwm-rz-mtu3.c132 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) in rz_mtu3_get_channel() argument
138 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) in rz_mtu3_get_channel()
146 u32 hwpwm) in rz_mtu3_pwm_is_ch_enabled() argument
152 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); in rz_mtu3_pwm_is_ch_enabled()
157 if (priv->map->base_pwm_number == hwpwm) in rz_mtu3_pwm_is_ch_enabled()
172 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_request()
201 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_free()
224 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_enable()
229 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_enable()
250 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_disable()
[all …]
Dpwm-lp3943.c34 lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) in lp3943_pwm_request_map() argument
38 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[hwpwm]; in lp3943_pwm_request_map()
41 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
42 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
60 pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm); in lp3943_pwm_request()
82 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_free()
105 if (pwm->hwpwm == 0) { in lp3943_pwm_config()
154 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_enable()
157 if (pwm->hwpwm == 0) in lp3943_pwm_enable()
173 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm]; in lp3943_pwm_disable()
Dpwm-samsung.c123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in __pwm_samsung_manual_update()
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()
236 pwm->hwpwm); in pwm_samsung_request()
240 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm])); in pwm_samsung_request()
248 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_enable()
264 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); in pwm_samsung_enable()
274 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_disable()
288 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) in pwm_samsung_disable()
291 our_chip->disabled_mask |= BIT(pwm->hwpwm); in pwm_samsung_disable()
312 struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm]; in __pwm_samsung_config()
[all …]
Dpwm-lpc18xx-sct.c140 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); in lpc18xx_pwm_set_conflict_res()
141 val |= LPC18XX_PWM_RES(pwm->hwpwm, action); in lpc18xx_pwm_set_conflict_res()
173 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_config_duty()
216 pwm->hwpwm); in lpc18xx_pwm_config()
237 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_enable()
260 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), in lpc18xx_pwm_enable()
262 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), in lpc18xx_pwm_enable()
272 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_disable()
276 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
277 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
[all …]
Dpwm-hibvt.c86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
109 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
112 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
123 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
126 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
140 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
143 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
146 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
Dpwm-spear.c126 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, in spear_pwm_config()
128 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); in spear_pwm_config()
129 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); in spear_pwm_config()
145 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_enable()
147 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_enable()
157 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_disable()
159 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_disable()
Dpwm-mediatek.c87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
138 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); in pwm_mediatek_config()
154 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { in pwm_mediatek_config()
164 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
165 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); in pwm_mediatek_config()
166 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); in pwm_mediatek_config()
184 value |= BIT(pwm->hwpwm); in pwm_mediatek_enable()
196 value &= ~BIT(pwm->hwpwm); in pwm_mediatek_disable()
Dpwm-pca9685.c386 pca9685_pwm_set_duty(chip, pwm->hwpwm, 0); in __pca9685_pwm_apply()
392 if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) { in __pca9685_pwm_apply()
416 pca9685_pwm_set_duty(chip, pwm->hwpwm, duty); in __pca9685_pwm_apply()
430 set_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_apply()
432 clear_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_apply()
458 if (pwm->hwpwm >= PCA9685_MAXCHAN) { in pca9685_pwm_get_state()
469 duty = pca9685_pwm_get_duty(chip, pwm->hwpwm); in pca9685_pwm_get_state()
479 if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm)) in pca9685_pwm_request()
482 if (pwm->hwpwm < PCA9685_MAXCHAN) { in pca9685_pwm_request()
485 set_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_request()
[all …]
/linux-6.12.1/include/trace/events/
Dpwm.h19 __field(unsigned int, hwpwm)
29 __entry->hwpwm = pwm->hwpwm;
38 __entry->chipid, __entry->hwpwm, __entry->period, __entry->duty_cycle,
/linux-6.12.1/drivers/hwmon/
Daspeed-g6-pwm-tach.c153 u32 hwpwm = pwm->hwpwm; in aspeed_pwm_get_state() local
158 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm)); in aspeed_pwm_get_state()
164 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); in aspeed_pwm_get_state()
191 u32 hwpwm = pwm->hwpwm, duty_pt, val; in aspeed_pwm_apply() local
233 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); in aspeed_pwm_apply()
237 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); in aspeed_pwm_apply()
246 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); in aspeed_pwm_apply()
250 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); in aspeed_pwm_apply()
253 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm)); in aspeed_pwm_apply()
262 writel(val, priv->base + PWM_ASPEED_CTRL(hwpwm)); in aspeed_pwm_apply()

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