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Searched refs:gvt_dbg_core (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dvgpu.c67 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); in populate_pvinfo_page()
68 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", in populate_pvinfo_page()
70 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", in populate_pvinfo_page()
72 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); in populate_pvinfo_page()
134 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n", in intel_gvt_init_vgpu_types()
319 gvt_dbg_core("low %u MB high %u MB fence %u\n", in intel_gvt_create_vgpu()
442 gvt_dbg_core("------------------------------------------\n"); in intel_gvt_reset_vgpu_locked()
443 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", in intel_gvt_reset_vgpu_locked()
495 gvt_dbg_core("reset vgpu%d done\n", vgpu->id); in intel_gvt_reset_vgpu_locked()
496 gvt_dbg_core("------------------------------------------\n"); in intel_gvt_reset_vgpu_locked()
Dfirmware.c173 gvt_dbg_core("Invalid firmware: %s [file] 0x%llx [request] 0x%llx\n", in verify_firmware()
221 gvt_dbg_core("request hw state firmware %s...\n", path); in intel_gvt_load_firmware()
229 gvt_dbg_core("success.\n"); in intel_gvt_load_firmware()
235 gvt_dbg_core("verified.\n"); in intel_gvt_load_firmware()
Dopregion.c227 gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); in intel_vgpu_init_opregion()
272 gvt_dbg_core("emulate opregion from kernel\n"); in intel_vgpu_opregion_base_write_handler()
286 gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); in intel_vgpu_clean_opregion()
Dfb_decoder.c178 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); in intel_vgpu_get_stride()
181 gvt_dbg_core("skl: unsupported tile format:%x\n", in intel_vgpu_get_stride()
374 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", in intel_vgpu_decode_cursor_plane()
Dmmio_context.c238 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_context_mmio_for_inhibit()
268 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_render_mocs_control_for_inhibit()
295 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", in restore_render_mocs_l3cc_for_inhibit()
404 gvt_dbg_core("invalidate TLB for ring %s\n", engine->name); in handle_tlb_pending_event()
Ddebug.h38 #define gvt_dbg_core(fmt, args...) \ macro
Daperture_gm.c94 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
97 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id, in alloc_vgpu_gm()
Dkvmgt.c1149 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); in intel_vgpu_ioctl()
1238 gvt_dbg_core("get region info bar:%d\n", info.index); in intel_vgpu_ioctl()
1247 gvt_dbg_core("get region info index:%d\n", info.index); in intel_vgpu_ioctl()
1502 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", in intel_vgpu_probe()
1765 gvt_dbg_core("service thread start\n"); in gvt_service_thread()
1864 gvt_dbg_core("init gvt device\n"); in intel_gvt_init_device()
1929 gvt_dbg_core("gvt device initialization is done\n"); in intel_gvt_init_device()
Dsched_policy.c430 gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id); in intel_vgpu_start_schedule()
455 gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id); in intel_vgpu_stop_schedule()
Dscheduler.c1161 gvt_dbg_core("workload thread for ring %s started\n", engine->name); in workload_thread()
1248 gvt_dbg_core("clean workload scheduler\n"); in intel_gvt_clean_workload_scheduler()
1265 gvt_dbg_core("init workload scheduler\n"); in intel_gvt_init_workload_scheduler()
1492 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); in intel_vgpu_select_submission_ops()
1504 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", in intel_vgpu_select_submission_ops()
Dinterrupt.c485 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", in handle_default_event_virt()
718 gvt_dbg_core("init irq framework\n"); in intel_gvt_init_irq()
Dcfg_space.c102 gvt_dbg_core("vgpu-%d power status changed to %d\n", in vgpu_pci_cfg_mem_write()
Ddmabuf.c234 gvt_dbg_core("invalid drm_format_mod %llx for tiling\n", in vgpu_create_gem()
Dhandlers.c228 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); in gamw_echo_dev_rw_ia_write()
230 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); in gamw_echo_dev_rw_ia_write()
1351 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, in vga_control_mmio_write()
1728 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", in mailbox_write()
2057 gvt_dbg_core("EXECLIST %s on ring %s\n", in ring_mode_mmio_write()
Dgtt.c2126 gvt_dbg_core("GMA 0x%lx is not present\n", gma); in intel_vgpu_gma_to_gpa()
2695 gvt_dbg_core("init gtt\n"); in intel_gvt_init_gtt()