Searched refs:gfx_v9_4_3_ce_reg_list (Results 1 – 1 of 1) sorted by relevance
4270 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { variable4408 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { in gfx_v9_4_3_inst_query_ras_err_count()4409 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { in gfx_v9_4_3_inst_query_ras_err_count()4410 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { in gfx_v9_4_3_inst_query_ras_err_count()4412 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || in gfx_v9_4_3_inst_query_ras_err_count()4413 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()4417 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()4419 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, in gfx_v9_4_3_inst_query_ras_err_count()4420 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, in gfx_v9_4_3_inst_query_ras_err_count()4476 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { in gfx_v9_4_3_inst_reset_ras_err_count()[all …]