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Searched refs:gce (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
447 gce: mailbox@10212000 { label
448 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
452 clock-names = "gce";
727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
728 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
739 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
749 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
[all …]
Dmt8183.dtsi9 #include <dt-bindings/gce/mt8183-gce.h>
1064 gce: mailbox@10238000 { label
1065 compatible = "mediatek,mt8183-gce";
1070 clock-names = "gce";
1666 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1667 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1668 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1674 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1675 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1681 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
[all …]
Dmt8173.dtsi14 #include <dt-bindings/gce/mt8173-gce.h>
626 gce: mailbox@10212000 { label
627 compatible = "mediatek,mt8173-gce";
631 clock-names = "gce";
1004 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1005 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1006 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1081 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1091 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1101 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
[all …]
Dmt8195.dtsi9 #include <dt-bindings/gce/mt8195-gce.h>
913 compatible = "mediatek,mt8195-gce";
921 compatible = "mediatek,mt8195-gce";
2031 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2055 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2062 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2069 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2077 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
Dmt8192.dtsi9 #include <dt-bindings/gce/mt8192-gce.h>
744 gce: mailbox@10228000 { label
745 compatible = "mediatek,mt8192-gce";
750 clock-names = "gce";
1457 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1458 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1459 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1467 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1468 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
Dmt8186.dtsi8 #include <dt-bindings/gce/mt8186-gce.h>
1138 gce: mailbox@1022c000 { label
1139 compatible = "mediatek,mt8186-gce";
1142 clock-names = "gce";
1768 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1769 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1778 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1779 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1821 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
Dmt8188.dtsi11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
1295 compatible = "mediatek,mt8188-gce";
1303 compatible = "mediatek,mt8188-gce";
1906 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
1915 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_psfp.c135 const struct sparx5_psfp_gce *gce; in sparx5_psfp_sg_set() local
167 gce = &sg->gce[i]; in sparx5_psfp_sg_set()
168 ips = sparx5_psfp_ipv_to_ips(gce->ipv); in sparx5_psfp_sg_set()
170 accum_time_interval += gce->interval; in sparx5_psfp_sg_set()
173 ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(gce->gate_state), in sparx5_psfp_sg_set()
181 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); in sparx5_psfp_sg_set()
Dsparx5_tc_flower.c736 sg->gce[i].gate_state = !!act->gate.entries[i].gate_state; in sparx5_tc_flower_parse_act_gate()
737 sg->gce[i].interval = act->gate.entries[i].interval; in sparx5_tc_flower_parse_act_gate()
738 sg->gce[i].ipv = act->gate.entries[i].ipv; in sparx5_tc_flower_parse_act_gate()
739 sg->gce[i].maxoctets = act->gate.entries[i].maxoctets; in sparx5_tc_flower_parse_act_gate()
794 sg->gce[0].gate_state = 1; in sparx5_tc_flower_psfp_setup()
795 sg->gce[0].interval = SPX5_PSFP_SG_CYCLE_TIME_DEFAULT; in sparx5_tc_flower_psfp_setup()
796 sg->gce[0].ipv = 0; in sparx5_tc_flower_psfp_setup()
797 sg->gce[0].maxoctets = 0; /* Disabled */ in sparx5_tc_flower_psfp_setup()
Dsparx5_main.h506 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; member
/linux-6.12.1/drivers/net/ethernet/freescale/enetc/
Denetc_qos.c54 struct gce *gce; in enetc_setup_taprio() local
86 gce = (struct gce *)(gcl_data + 1); in enetc_setup_taprio()
99 struct gce *temp_gce = gce + i; in enetc_setup_taprio()
Denetc_hw.h764 struct gce { struct
776 struct gce entry[]; argument
/linux-6.12.1/Documentation/filesystems/
Dfscrypt.rst1502 much longer to run; so also consider using `gce-xfstests
1503 <https://github.com/tytso/xfstests-bld/blob/master/Documentation/gce-xfstests.md>`_
1506 gce-xfstests -c ext4/encrypt,f2fs/encrypt -g auto
1507 gce-xfstests -c ext4/encrypt,f2fs/encrypt -g auto -m inlinecrypt