| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-periph-gate.c | 19 #define read_enb(gate) \ argument
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \ argument
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \ argument
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \ argument
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \ argument
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
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| /linux-6.12.1/drivers/clk/mmp/ |
| D | clk-gate.c | 26 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); in mmp_clk_gate_enable() local
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
40 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
42 if (gate->flags & MMP_CLK_GATE_NEED_DELAY) { in mmp_clk_gate_enable()
[all …]
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-gate-93.c | 49 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_do_hardware() local
52 val = readl(gate->reg + AUTHEN_OFFSET); in imx93_clk_gate_do_hardware()
55 writel(val, gate->reg + LPM_CUR_OFFSET); in imx93_clk_gate_do_hardware()
57 val = readl(gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
61 writel(val, gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
67 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_enable() local
70 spin_lock_irqsave(gate->lock, flags); in imx93_clk_gate_enable()
72 if (gate->share_count && (*gate->share_count)++ > 0) in imx93_clk_gate_enable()
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| D | clk-gate2.c | 43 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_do_shared_clks() local
46 reg = readl(gate->reg); in clk_gate2_do_shared_clks()
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
50 writel(reg, gate->reg); in clk_gate2_do_shared_clks()
55 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
58 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
65 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
72 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_disable() local
[all …]
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| D | clk-gate-exclusive.c | 25 struct clk_gate gate; member
31 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_exclusive_enable() local
32 struct clk_gate_exclusive *exgate = container_of(gate, in clk_gate_exclusive_enable()
33 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
34 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive() local
73 gate = &exgate->gate; in imx_clk_hw_gate_exclusive()
81 gate->reg = reg; in imx_clk_hw_gate_exclusive()
82 gate->bit_idx = shift; in imx_clk_hw_gate_exclusive()
83 gate->lock = &imx_ccm_lock; in imx_clk_hw_gate_exclusive()
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| D | clk-composite-93.c | 48 struct clk_gate *gate = to_clk_gate(hw); in imx93_clk_composite_gate_endisable() local
52 if (gate->lock) in imx93_clk_composite_gate_endisable()
53 spin_lock_irqsave(gate->lock, flags); in imx93_clk_composite_gate_endisable()
55 reg = readl(gate->reg); in imx93_clk_composite_gate_endisable()
58 reg &= ~BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
60 reg |= BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
62 writel(reg, gate->reg); in imx93_clk_composite_gate_endisable()
64 imx93_clk_composite_wait_ready(hw, gate->reg); in imx93_clk_composite_gate_endisable()
66 if (gate->lock) in imx93_clk_composite_gate_endisable()
67 spin_unlock_irqrestore(gate->lock, flags); in imx93_clk_composite_gate_endisable()
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| D | clk-composite-7ulp.c | 30 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable() local
39 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
44 val = readl(gate->reg); in pcc_gate_enable()
46 writel(val, gate->reg); in pcc_gate_enable()
48 spin_unlock_irqrestore(gate->lock, flags); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx_ulp_clk_hw_composite()
119 if (!gate) { in imx_ulp_clk_hw_composite()
124 gate_hw = &gate->hw; in imx_ulp_clk_hw_composite()
125 gate->reg = reg; in imx_ulp_clk_hw_composite()
[all …]
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| /linux-6.12.1/drivers/clk/ |
| D | clk-gate.c | 27 static inline u32 clk_gate_readl(struct clk_gate *gate) in clk_gate_readl() argument
29 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_readl()
30 return ioread32be(gate->reg); in clk_gate_readl()
32 return readl(gate->reg); in clk_gate_readl()
35 static inline void clk_gate_writel(struct clk_gate *gate, u32 val) in clk_gate_writel() argument
37 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_writel()
38 iowrite32be(val, gate->reg); in clk_gate_writel()
40 writel(val, gate->reg); in clk_gate_writel()
58 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable() local
59 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_gate_endisable()
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| D | clk-ast2600.c | 271 static u32 get_reset_reg(struct aspeed_clk_gate *gate) in get_reset_reg() argument
273 if (gate->reset_idx < 32) in get_reset_reg()
279 static u32 get_clock_reg(struct aspeed_clk_gate *gate) in get_clock_reg() argument
281 if (gate->clock_idx < 32) in get_clock_reg()
289 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_g6_clk_is_enabled() local
290 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_is_enabled()
291 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_is_enabled()
301 if (gate->reset_idx >= 0) { in aspeed_g6_clk_is_enabled()
302 regmap_read(gate->map, get_reset_reg(gate), ®); in aspeed_g6_clk_is_enabled()
308 regmap_read(gate->map, get_clock_reg(gate), ®); in aspeed_g6_clk_is_enabled()
[all …]
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| D | clk-aspeed.c | 186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_is_enabled() local
187 u32 clk = BIT(gate->clock_idx); in aspeed_clk_is_enabled()
188 u32 rst = BIT(gate->reset_idx); in aspeed_clk_is_enabled()
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_is_enabled()
198 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
199 regmap_read(gate->map, ASPEED_RESET_CTRL, ®); in aspeed_clk_is_enabled()
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); in aspeed_clk_is_enabled()
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_enable() local
213 u32 clk = BIT(gate->clock_idx); in aspeed_clk_enable()
214 u32 rst = BIT(gate->reset_idx); in aspeed_clk_enable()
[all …]
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| /linux-6.12.1/drivers/staging/sm750fb/ |
| D | ddk750_power.c | 75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
94 gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
96 sm750_set_current_gate(gate); in sm750_enable_2d_engine()
101 u32 gate; in sm750_enable_dma() local
104 gate = peek32(CURRENT_GATE); in sm750_enable_dma()
[all …]
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| /linux-6.12.1/drivers/clk/visconti/ |
| D | clkc.c | 30 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_is_enabled() local
31 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_is_enabled()
34 regmap_read(gate->regmap, gate->ckon_offset, &val); in visconti_gate_clk_is_enabled()
40 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_disable() local
41 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_disable()
44 spin_lock_irqsave(gate->lock, flags); in visconti_gate_clk_disable()
47 spin_unlock_irqrestore(gate->lock, flags); in visconti_gate_clk_disable()
51 regmap_update_bits(gate->regmap, gate->ckoff_offset, clk, clk); in visconti_gate_clk_disable()
52 spin_unlock_irqrestore(gate->lock, flags); in visconti_gate_clk_disable()
57 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_enable() local
[all …]
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| /linux-6.12.1/drivers/clk/uniphier/ |
| D | clk-uniphier-gate.c | 25 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_endisable() local
27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
28 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
44 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_is_enabled() local
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
50 return !!(val & BIT(gate->bit)); in uniphier_clk_gate_is_enabled()
64 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
68 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
69 if (!gate) in uniphier_clk_register_gate()
78 gate->regmap = regmap; in uniphier_clk_register_gate()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 1 Binding for Texas Instruments gate clock.
4 quite much similar to the basic gate-clock [2], however,
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
24 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
26 "ti,composite-gate-clock" - composite gate clock, to be part of composite
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| /linux-6.12.1/drivers/clk/ingenic/ |
| D | jz4755-cgu.c | 144 .gate = { CGU_REG_CLKGR, 10 },
151 .gate = { CGU_REG_CLKGR, 9 },
171 .gate = { CGU_REG_CLKGR, 4 },
178 .gate = { CGU_REG_CLKGR, 18 },
185 .gate = { CGU_REG_CLKGR, 2 },
192 .gate = { CGU_REG_CLKGR, 8 },
200 .gate = { CGU_REG_CLKGR, 0 },
206 .gate = { CGU_REG_CLKGR, 14 },
212 .gate = { CGU_REG_CLKGR, 15 },
218 .gate = { CGU_REG_CLKGR, 7 },
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| D | jz4770-cgu.c | 178 .gate = { CGU_REG_CLKGR1, 7 },
195 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
213 .gate = { CGU_REG_MSC0CDR, 31 },
220 .gate = { CGU_REG_MSC1CDR, 31 },
227 .gate = { CGU_REG_MSC2CDR, 31 },
234 .gate = { CGU_REG_CLKGR0, 26 },
241 .gate = { CGU_REG_CLKGR0, 24 },
248 .gate = { CGU_REG_CLKGR1, 9 },
255 .gate = { CGU_REG_CLKGR0, 1 },
262 .gate = { CGU_REG_CLKGR0, 28 },
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| D | jz4760-cgu.c | 219 .gate = { CGU_REG_CLKGR0, 24 },
226 .gate = { CGU_REG_CLKGR1, 9 },
238 .gate = { CGU_REG_CLKGR0, 27 },
244 .gate = { CGU_REG_CLKGR0, 28 },
251 .gate = { CGU_REG_CLKGR0, 22 },
262 .gate = { CGU_REG_CLKGR1, 8 },
277 .gate = { CGU_REG_CLKGR0, 2 },
299 .gate = { CGU_REG_CLKGR0, 26 },
307 .gate = { CGU_REG_CLKGR0, 4 },
312 .gate = { CGU_REG_CLKGR0, 19 },
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| D | jz4780-cgu.c | 409 .gate = { CGU_REG_CLKGR1, 2 },
451 .gate = { CGU_REG_CLKGR0, 3 },
458 .gate = { CGU_REG_CLKGR0, 11 },
465 .gate = { CGU_REG_CLKGR0, 12 },
474 .gate = { CGU_REG_CLKGR0, 24 },
509 .gate = { CGU_REG_CLKGR1, 3 },
518 .gate = { CGU_REG_CLKGR1, 4 },
527 .gate = { CGU_REG_CLKGR1, 9 },
536 .gate = { CGU_REG_CLKGR0, 1 },
556 .gate = { CGU_REG_CLKGR0, 0 },
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| D | x1830-cgu.c | 231 .gate = { CGU_REG_CLKGR1, 15 },
268 .gate = { CGU_REG_CLKGR1, 14 },
281 .gate = { CGU_REG_CLKGR0, 31 },
290 .gate = { CGU_REG_CLKGR1, 4 },
299 .gate = { CGU_REG_CLKGR1, 9 },
313 .gate = { CGU_REG_CLKGR0, 4 },
320 .gate = { CGU_REG_CLKGR0, 5 },
353 .gate = { CGU_REG_CLKGR0, 29 },
361 .gate = { CGU_REG_CLKGR0, 0 },
367 .gate = { CGU_REG_CLKGR0, 1 },
[all …]
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| D | jz4740-cgu.c | 156 .gate = { CGU_REG_CLKGR, 10 },
170 .gate = { CGU_REG_CLKGR, 6 },
178 .gate = { CGU_REG_CLKGR, 4 },
185 .gate = { CGU_REG_CLKGR, 7 },
192 .gate = { CGU_REG_CLKGR, 14 },
200 .gate = { CGU_REG_SCR, 6, true },
208 .gate = { CGU_REG_CLKGR, 0 },
214 .gate = { CGU_REG_CLKGR, 15 },
220 .gate = { CGU_REG_CLKGR, 12 },
226 .gate = { CGU_REG_CLKGR, 13 },
[all …]
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| /linux-6.12.1/drivers/clk/zynqmp/ |
| D | clk-gate-zynqmp.c | 36 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_enable() local
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable()
56 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_disable() local
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable()
76 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_is_enabled() local
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled()
112 struct zynqmp_clk_gate *gate; in zynqmp_clk_register_gate() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in zynqmp_clk_register_gate()
119 if (!gate) in zynqmp_clk_register_gate()
131 gate->flags = nodes->type_flag; in zynqmp_clk_register_gate()
[all …]
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-kona.c | 350 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __is_clk_gate_enabled() argument
356 if (!gate_exists(gate)) in __is_clk_gate_enabled()
359 bit_mask = 1 << gate->status_bit; in __is_clk_gate_enabled()
360 reg_val = __ccu_read(ccu, gate->offset); in __is_clk_gate_enabled()
367 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in is_clk_gate_enabled() argument
373 if (!gate_exists(gate)) in is_clk_gate_enabled()
377 ret = __is_clk_gate_enabled(ccu, gate); in is_clk_gate_enabled()
388 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __gate_commit() argument
394 BUG_ON(!gate_exists(gate)); in __gate_commit()
395 if (!gate_is_sw_controllable(gate)) in __gate_commit()
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| D | clk-bcm281xx.c | 16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
76 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
95 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
107 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
119 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
131 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
143 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
154 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
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| D | clk-bcm21664.c | 16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
70 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
82 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
94 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
107 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
112 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
117 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
122 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-gate.c | 223 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates() local
225 if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) { in mtk_clk_register_gates()
227 node, gate->id); in mtk_clk_register_gates()
231 hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, in mtk_clk_register_gates()
233 gate->regs->set_ofs, in mtk_clk_register_gates()
234 gate->regs->clr_ofs, in mtk_clk_register_gates()
235 gate->regs->sta_ofs, in mtk_clk_register_gates()
236 gate->shift, gate->ops, in mtk_clk_register_gates()
237 gate->flags); in mtk_clk_register_gates()
240 pr_err("Failed to register clk %s: %pe\n", gate->name, in mtk_clk_register_gates()
[all …]
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