| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | stb6000.c | 70 u32 freq_mhz; in stb6000_set_params() local
82 freq_mhz = p->frequency / 1000; in stb6000_set_params()
88 if ((freq_mhz > 949) && (freq_mhz < 2151)) { in stb6000_set_params()
91 if (freq_mhz < 1950) in stb6000_set_params()
93 if (freq_mhz < 1800) in stb6000_set_params()
95 if (freq_mhz < 1650) in stb6000_set_params()
97 if (freq_mhz < 1530) in stb6000_set_params()
99 if (freq_mhz < 1470) in stb6000_set_params()
101 if (freq_mhz < 1370) in stb6000_set_params()
103 if (freq_mhz < 1300) in stb6000_set_params()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr_smu_msg.c | 212 …t dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) in dcn30_smu_set_hard_min_by_freq() argument
217 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
219 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
230 …t dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) in dcn30_smu_set_hard_max_by_freq() argument
235 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_max_by_freq()
237 smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_max_by_freq()
296 void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz) in dcn30_smu_set_min_deep_sleep_dcef_clk() argument
298 smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz); in dcn30_smu_set_min_deep_sleep_dcef_clk()
301 DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL); in dcn30_smu_set_min_deep_sleep_dcef_clk()
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| D | dcn30_clk_mgr_smu_msg.h | 41 … dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
42 … dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
45 … dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| D | dcn401_clk_mgr_smu_msg.c | 220 … dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) in dcn401_smu_set_hard_min_by_freq() argument
226 uint32_t param = (clk << 16) | freq_mhz; in dcn401_smu_set_hard_min_by_freq()
228 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn401_smu_set_hard_min_by_freq()
299 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz) in dcn401_smu_set_min_deep_sleep_dcef_clk() argument
301 smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz); in dcn401_smu_set_min_deep_sleep_dcef_clk()
304 DALSMC_MSG_SetMinDeepSleepDcfclk, freq_mhz, NULL); in dcn401_smu_set_min_deep_sleep_dcef_clk()
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| D | dcn401_clk_mgr_smu_msg.h | 17 …dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
26 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
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| D | dcn401_clk_mgr.h | 18 uint16_t freq_mhz; member
36 uint16_t freq_mhz; member
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| D | dcn401_clk_mgr.c | 843 params->update_hardmin_params.freq_mhz); in dcn401_execute_block_sequence()
847 params->update_hardmin_params.freq_mhz); in dcn401_execute_block_sequence()
875 params->update_deep_sleep_dcfclk_params.freq_mhz); in dcn401_execute_block_sequence()
1012 …block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->cl… in dcn401_build_update_bandwidth_clocks_sequence()
1023 …block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mg… in dcn401_build_update_bandwidth_clocks_sequence()
1153 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence()
1266 …block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_… in dcn401_build_update_display_clocks_sequence()
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 86 u32 freq_mhz = req->rate / 1000000; in sun6i_a31_get_pll1_factors() local
93 u32 round_freq_6 = rounddown(freq_mhz, 6); in sun6i_a31_get_pll1_factors()
94 u32 round_freq_16 = round_down(freq_mhz, 16); in sun6i_a31_get_pll1_factors()
97 freq_mhz = round_freq_6; in sun6i_a31_get_pll1_factors()
99 freq_mhz = round_freq_16; in sun6i_a31_get_pll1_factors()
101 req->rate = freq_mhz * 1000000; in sun6i_a31_get_pll1_factors()
104 if (!(freq_mhz % 32)) in sun6i_a31_get_pll1_factors()
107 else if (!(freq_mhz % 9)) in sun6i_a31_get_pll1_factors()
110 else if (!(freq_mhz % 8)) in sun6i_a31_get_pll1_factors()
124 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) in sun6i_a31_get_pll1_factors()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr_smu_msg.c | 280 …t dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) in dcn32_smu_set_hard_min_by_freq() argument
286 uint32_t param = (clk << 16) | freq_mhz; in dcn32_smu_set_hard_min_by_freq()
288 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn32_smu_set_hard_min_by_freq()
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| D | dcn32_clk_mgr_smu_msg.h | 43 … dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
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| /linux-6.12.1/drivers/memory/samsung/ |
| D | exynos5422-dmc.c | 1182 u32 freq_mhz, clk_period_ps; in of_get_dram_timings() local
1222 freq_mhz = dmc->opp[idx].freq_hz / 1000000; in of_get_dram_timings()
1223 clk_period_ps = 1000000 / freq_mhz; in of_get_dram_timings()
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| /linux-6.12.1/drivers/net/wireless/ath/wil6210/ |
| D | wmi.h | 721 __le32 freq_mhz; member
|