1  /*
2   * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3   *
4   * This software is available to you under a choice of one of two
5   * licenses.  You may choose to be licensed under the terms of the GNU
6   * General Public License (GPL) Version 2, available from the file
7   * COPYING in the main directory of this source tree, or the
8   * OpenIB.org BSD license below:
9   *
10   *     Redistribution and use in source and binary forms, with or
11   *     without modification, are permitted provided that the following
12   *     conditions are met:
13   *
14   *      - Redistributions of source code must retain the above
15   *        copyright notice, this list of conditions and the following
16   *        disclaimer.
17   *
18   *      - Redistributions in binary form must reproduce the above
19   *        copyright notice, this list of conditions and the following
20   *        disclaimer in the documentation and/or other materials
21   *        provided with the distribution.
22   *
23   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24   * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26   * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27   * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28   * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29   * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30   * SOFTWARE.
31  */
32  #ifndef MLX5_IFC_H
33  #define MLX5_IFC_H
34  
35  #include "mlx5_ifc_fpga.h"
36  
37  enum {
38  	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39  	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40  	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41  	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42  	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43  	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44  	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45  	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46  	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47  	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48  	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49  	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50  	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51  	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52  	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53  	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54  	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55  	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56  	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57  	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58  	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59  	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60  	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61  	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62  	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63  	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64  };
65  
66  enum {
67  	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68  	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69  	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70  	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71  	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72  	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73  	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74  	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75  };
76  
77  enum {
78  	MLX5_SHARED_RESOURCE_UID = 0xffff,
79  };
80  
81  enum {
82  	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83  	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84  	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85  	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86  	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87  	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88  	MLX5_OBJ_TYPE_STC = 0x0040,
89  	MLX5_OBJ_TYPE_RTC = 0x0041,
90  	MLX5_OBJ_TYPE_STE = 0x0042,
91  	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92  	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93  	MLX5_OBJ_TYPE_MKEY = 0xff01,
94  	MLX5_OBJ_TYPE_QP = 0xff02,
95  	MLX5_OBJ_TYPE_PSV = 0xff03,
96  	MLX5_OBJ_TYPE_RMP = 0xff04,
97  	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98  	MLX5_OBJ_TYPE_RQ = 0xff06,
99  	MLX5_OBJ_TYPE_SQ = 0xff07,
100  	MLX5_OBJ_TYPE_TIR = 0xff08,
101  	MLX5_OBJ_TYPE_TIS = 0xff09,
102  	MLX5_OBJ_TYPE_DCT = 0xff0a,
103  	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104  	MLX5_OBJ_TYPE_RQT = 0xff0e,
105  	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106  	MLX5_OBJ_TYPE_CQ = 0xff10,
107  	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108  };
109  
110  enum {
111  	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112  	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113  	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114  	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115  		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116  	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117  };
118  
119  enum {
120  	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121  	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122  	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123  	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124  	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125  	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126  	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127  	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128  	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129  	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130  	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131  	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132  	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133  	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134  	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135  	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136  	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137  	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138  	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139  	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140  	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141  	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142  	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143  	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144  	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145  	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146  	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147  	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148  	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149  	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150  	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151  	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152  	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153  	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154  	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155  	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156  	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157  	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158  	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159  	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160  	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161  	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162  	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163  	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164  	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165  	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166  	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167  	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168  	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169  	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170  	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171  	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172  	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173  	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174  	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175  	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176  	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177  	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178  	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179  	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180  	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181  	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182  	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183  	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184  	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185  	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186  	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187  	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188  	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189  	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190  	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191  	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192  	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
193  	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
194  	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
195  	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
196  	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
197  	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
198  	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
199  	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
200  	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
201  	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
202  	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
203  	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
204  	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
205  	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
206  	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
207  	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
208  	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
209  	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
210  	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
211  	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
212  	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
213  	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
214  	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
215  	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
216  	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
217  	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
218  	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
219  	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
220  	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
221  	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
222  	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
223  	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
224  	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
225  	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
226  	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
227  	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
228  	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
229  	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
230  	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
231  	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
232  	MLX5_CMD_OP_NOP                           = 0x80d,
233  	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
234  	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
235  	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
236  	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
237  	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
238  	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
239  	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
240  	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
241  	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
242  	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
243  	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
244  	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
245  	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
246  	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
247  	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
248  	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
249  	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
250  	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
251  	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
252  	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
253  	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
254  	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
255  	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
256  	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
257  	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
258  	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
259  	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
260  	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
261  	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
262  	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
263  	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
264  	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
265  	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
266  	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
267  	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
268  	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
269  	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
270  	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
271  	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
272  	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
273  	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
274  	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
275  	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
276  	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
277  	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
278  	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
279  	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
280  	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
281  	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
282  	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
283  	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
284  	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
285  	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
286  	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
287  	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
288  	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
289  	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
290  	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
291  	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
292  	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
293  	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
294  	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
295  	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
296  	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
297  	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
298  	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
299  	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
300  	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
301  	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
302  	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
303  	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
304  	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
305  	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
306  	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
307  	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
308  	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
309  	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
310  	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
311  	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
312  	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
313  	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
314  	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
315  	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
316  	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
317  	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
318  	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
319  	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
320  	MLX5_CMD_OP_MAX
321  };
322  
323  /* Valid range for general commands that don't work over an object */
324  enum {
325  	MLX5_CMD_OP_GENERAL_START = 0xb00,
326  	MLX5_CMD_OP_GENERAL_END = 0xd00,
327  };
328  
329  enum {
330  	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331  	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
332  };
333  
334  enum {
335  	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
336  };
337  
338  struct mlx5_ifc_flow_table_fields_supported_bits {
339  	u8         outer_dmac[0x1];
340  	u8         outer_smac[0x1];
341  	u8         outer_ether_type[0x1];
342  	u8         outer_ip_version[0x1];
343  	u8         outer_first_prio[0x1];
344  	u8         outer_first_cfi[0x1];
345  	u8         outer_first_vid[0x1];
346  	u8         outer_ipv4_ttl[0x1];
347  	u8         outer_second_prio[0x1];
348  	u8         outer_second_cfi[0x1];
349  	u8         outer_second_vid[0x1];
350  	u8         reserved_at_b[0x1];
351  	u8         outer_sip[0x1];
352  	u8         outer_dip[0x1];
353  	u8         outer_frag[0x1];
354  	u8         outer_ip_protocol[0x1];
355  	u8         outer_ip_ecn[0x1];
356  	u8         outer_ip_dscp[0x1];
357  	u8         outer_udp_sport[0x1];
358  	u8         outer_udp_dport[0x1];
359  	u8         outer_tcp_sport[0x1];
360  	u8         outer_tcp_dport[0x1];
361  	u8         outer_tcp_flags[0x1];
362  	u8         outer_gre_protocol[0x1];
363  	u8         outer_gre_key[0x1];
364  	u8         outer_vxlan_vni[0x1];
365  	u8         outer_geneve_vni[0x1];
366  	u8         outer_geneve_oam[0x1];
367  	u8         outer_geneve_protocol_type[0x1];
368  	u8         outer_geneve_opt_len[0x1];
369  	u8         source_vhca_port[0x1];
370  	u8         source_eswitch_port[0x1];
371  
372  	u8         inner_dmac[0x1];
373  	u8         inner_smac[0x1];
374  	u8         inner_ether_type[0x1];
375  	u8         inner_ip_version[0x1];
376  	u8         inner_first_prio[0x1];
377  	u8         inner_first_cfi[0x1];
378  	u8         inner_first_vid[0x1];
379  	u8         reserved_at_27[0x1];
380  	u8         inner_second_prio[0x1];
381  	u8         inner_second_cfi[0x1];
382  	u8         inner_second_vid[0x1];
383  	u8         reserved_at_2b[0x1];
384  	u8         inner_sip[0x1];
385  	u8         inner_dip[0x1];
386  	u8         inner_frag[0x1];
387  	u8         inner_ip_protocol[0x1];
388  	u8         inner_ip_ecn[0x1];
389  	u8         inner_ip_dscp[0x1];
390  	u8         inner_udp_sport[0x1];
391  	u8         inner_udp_dport[0x1];
392  	u8         inner_tcp_sport[0x1];
393  	u8         inner_tcp_dport[0x1];
394  	u8         inner_tcp_flags[0x1];
395  	u8         reserved_at_37[0x9];
396  
397  	u8         geneve_tlv_option_0_data[0x1];
398  	u8         geneve_tlv_option_0_exist[0x1];
399  	u8         reserved_at_42[0x3];
400  	u8         outer_first_mpls_over_udp[0x4];
401  	u8         outer_first_mpls_over_gre[0x4];
402  	u8         inner_first_mpls[0x4];
403  	u8         outer_first_mpls[0x4];
404  	u8         reserved_at_55[0x2];
405  	u8	   outer_esp_spi[0x1];
406  	u8         reserved_at_58[0x2];
407  	u8         bth_dst_qp[0x1];
408  	u8         reserved_at_5b[0x5];
409  
410  	u8         reserved_at_60[0x18];
411  	u8         metadata_reg_c_7[0x1];
412  	u8         metadata_reg_c_6[0x1];
413  	u8         metadata_reg_c_5[0x1];
414  	u8         metadata_reg_c_4[0x1];
415  	u8         metadata_reg_c_3[0x1];
416  	u8         metadata_reg_c_2[0x1];
417  	u8         metadata_reg_c_1[0x1];
418  	u8         metadata_reg_c_0[0x1];
419  };
420  
421  /* Table 2170 - Flow Table Fields Supported 2 Format */
422  struct mlx5_ifc_flow_table_fields_supported_2_bits {
423  	u8         reserved_at_0[0x2];
424  	u8         inner_l4_type[0x1];
425  	u8         outer_l4_type[0x1];
426  	u8         reserved_at_4[0xa];
427  	u8         bth_opcode[0x1];
428  	u8         reserved_at_f[0x1];
429  	u8         tunnel_header_0_1[0x1];
430  	u8         reserved_at_11[0xf];
431  
432  	u8         reserved_at_20[0x60];
433  };
434  
435  struct mlx5_ifc_flow_table_prop_layout_bits {
436  	u8         ft_support[0x1];
437  	u8         reserved_at_1[0x1];
438  	u8         flow_counter[0x1];
439  	u8	   flow_modify_en[0x1];
440  	u8         modify_root[0x1];
441  	u8         identified_miss_table_mode[0x1];
442  	u8         flow_table_modify[0x1];
443  	u8         reformat[0x1];
444  	u8         decap[0x1];
445  	u8         reset_root_to_default[0x1];
446  	u8         pop_vlan[0x1];
447  	u8         push_vlan[0x1];
448  	u8         reserved_at_c[0x1];
449  	u8         pop_vlan_2[0x1];
450  	u8         push_vlan_2[0x1];
451  	u8	   reformat_and_vlan_action[0x1];
452  	u8	   reserved_at_10[0x1];
453  	u8         sw_owner[0x1];
454  	u8	   reformat_l3_tunnel_to_l2[0x1];
455  	u8	   reformat_l2_to_l3_tunnel[0x1];
456  	u8	   reformat_and_modify_action[0x1];
457  	u8	   ignore_flow_level[0x1];
458  	u8         reserved_at_16[0x1];
459  	u8	   table_miss_action_domain[0x1];
460  	u8         termination_table[0x1];
461  	u8         reformat_and_fwd_to_table[0x1];
462  	u8         reserved_at_1a[0x2];
463  	u8         ipsec_encrypt[0x1];
464  	u8         ipsec_decrypt[0x1];
465  	u8         sw_owner_v2[0x1];
466  	u8         reserved_at_1f[0x1];
467  
468  	u8         termination_table_raw_traffic[0x1];
469  	u8         reserved_at_21[0x1];
470  	u8         log_max_ft_size[0x6];
471  	u8         log_max_modify_header_context[0x8];
472  	u8         max_modify_header_actions[0x8];
473  	u8         max_ft_level[0x8];
474  
475  	u8         reformat_add_esp_trasport[0x1];
476  	u8         reformat_l2_to_l3_esp_tunnel[0x1];
477  	u8         reformat_add_esp_transport_over_udp[0x1];
478  	u8         reformat_del_esp_trasport[0x1];
479  	u8         reformat_l3_esp_tunnel_to_l2[0x1];
480  	u8         reformat_del_esp_transport_over_udp[0x1];
481  	u8         execute_aso[0x1];
482  	u8         reserved_at_47[0x19];
483  
484  	u8         reserved_at_60[0x2];
485  	u8         reformat_insert[0x1];
486  	u8         reformat_remove[0x1];
487  	u8         macsec_encrypt[0x1];
488  	u8         macsec_decrypt[0x1];
489  	u8         reserved_at_66[0x2];
490  	u8         reformat_add_macsec[0x1];
491  	u8         reformat_remove_macsec[0x1];
492  	u8         reparse[0x1];
493  	u8         reserved_at_6b[0x1];
494  	u8         cross_vhca_object[0x1];
495  	u8         reformat_l2_to_l3_audp_tunnel[0x1];
496  	u8         reformat_l3_audp_tunnel_to_l2[0x1];
497  	u8         ignore_flow_level_rtc_valid[0x1];
498  	u8         reserved_at_70[0x8];
499  	u8         log_max_ft_num[0x8];
500  
501  	u8         reserved_at_80[0x10];
502  	u8         log_max_flow_counter[0x8];
503  	u8         log_max_destination[0x8];
504  
505  	u8         reserved_at_a0[0x18];
506  	u8         log_max_flow[0x8];
507  
508  	u8         reserved_at_c0[0x40];
509  
510  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
511  
512  	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
513  };
514  
515  struct mlx5_ifc_odp_per_transport_service_cap_bits {
516  	u8         send[0x1];
517  	u8         receive[0x1];
518  	u8         write[0x1];
519  	u8         read[0x1];
520  	u8         atomic[0x1];
521  	u8         srq_receive[0x1];
522  	u8         reserved_at_6[0x1a];
523  };
524  
525  struct mlx5_ifc_ipv4_layout_bits {
526  	u8         reserved_at_0[0x60];
527  
528  	u8         ipv4[0x20];
529  };
530  
531  struct mlx5_ifc_ipv6_layout_bits {
532  	u8         ipv6[16][0x8];
533  };
534  
535  struct mlx5_ifc_ipv6_simple_layout_bits {
536  	u8         ipv6_127_96[0x20];
537  	u8         ipv6_95_64[0x20];
538  	u8         ipv6_63_32[0x20];
539  	u8         ipv6_31_0[0x20];
540  };
541  
542  union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
543  	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
544  	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
545  	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
546  	u8         reserved_at_0[0x80];
547  };
548  
549  enum {
550  	MLX5_PACKET_L4_TYPE_NONE,
551  	MLX5_PACKET_L4_TYPE_TCP,
552  	MLX5_PACKET_L4_TYPE_UDP,
553  };
554  
555  struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
556  	u8         smac_47_16[0x20];
557  
558  	u8         smac_15_0[0x10];
559  	u8         ethertype[0x10];
560  
561  	u8         dmac_47_16[0x20];
562  
563  	u8         dmac_15_0[0x10];
564  	u8         first_prio[0x3];
565  	u8         first_cfi[0x1];
566  	u8         first_vid[0xc];
567  
568  	u8         ip_protocol[0x8];
569  	u8         ip_dscp[0x6];
570  	u8         ip_ecn[0x2];
571  	u8         cvlan_tag[0x1];
572  	u8         svlan_tag[0x1];
573  	u8         frag[0x1];
574  	u8         ip_version[0x4];
575  	u8         tcp_flags[0x9];
576  
577  	u8         tcp_sport[0x10];
578  	u8         tcp_dport[0x10];
579  
580  	u8         l4_type[0x2];
581  	u8         reserved_at_c2[0xe];
582  	u8         ipv4_ihl[0x4];
583  	u8         reserved_at_c4[0x4];
584  
585  	u8         ttl_hoplimit[0x8];
586  
587  	u8         udp_sport[0x10];
588  	u8         udp_dport[0x10];
589  
590  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
591  
592  	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
593  };
594  
595  struct mlx5_ifc_nvgre_key_bits {
596  	u8 hi[0x18];
597  	u8 lo[0x8];
598  };
599  
600  union mlx5_ifc_gre_key_bits {
601  	struct mlx5_ifc_nvgre_key_bits nvgre;
602  	u8 key[0x20];
603  };
604  
605  struct mlx5_ifc_fte_match_set_misc_bits {
606  	u8         gre_c_present[0x1];
607  	u8         reserved_at_1[0x1];
608  	u8         gre_k_present[0x1];
609  	u8         gre_s_present[0x1];
610  	u8         source_vhca_port[0x4];
611  	u8         source_sqn[0x18];
612  
613  	u8         source_eswitch_owner_vhca_id[0x10];
614  	u8         source_port[0x10];
615  
616  	u8         outer_second_prio[0x3];
617  	u8         outer_second_cfi[0x1];
618  	u8         outer_second_vid[0xc];
619  	u8         inner_second_prio[0x3];
620  	u8         inner_second_cfi[0x1];
621  	u8         inner_second_vid[0xc];
622  
623  	u8         outer_second_cvlan_tag[0x1];
624  	u8         inner_second_cvlan_tag[0x1];
625  	u8         outer_second_svlan_tag[0x1];
626  	u8         inner_second_svlan_tag[0x1];
627  	u8         reserved_at_64[0xc];
628  	u8         gre_protocol[0x10];
629  
630  	union mlx5_ifc_gre_key_bits gre_key;
631  
632  	u8         vxlan_vni[0x18];
633  	u8         bth_opcode[0x8];
634  
635  	u8         geneve_vni[0x18];
636  	u8         reserved_at_d8[0x6];
637  	u8         geneve_tlv_option_0_exist[0x1];
638  	u8         geneve_oam[0x1];
639  
640  	u8         reserved_at_e0[0xc];
641  	u8         outer_ipv6_flow_label[0x14];
642  
643  	u8         reserved_at_100[0xc];
644  	u8         inner_ipv6_flow_label[0x14];
645  
646  	u8         reserved_at_120[0xa];
647  	u8         geneve_opt_len[0x6];
648  	u8         geneve_protocol_type[0x10];
649  
650  	u8         reserved_at_140[0x8];
651  	u8         bth_dst_qp[0x18];
652  	u8	   inner_esp_spi[0x20];
653  	u8	   outer_esp_spi[0x20];
654  	u8         reserved_at_1a0[0x60];
655  };
656  
657  struct mlx5_ifc_fte_match_mpls_bits {
658  	u8         mpls_label[0x14];
659  	u8         mpls_exp[0x3];
660  	u8         mpls_s_bos[0x1];
661  	u8         mpls_ttl[0x8];
662  };
663  
664  struct mlx5_ifc_fte_match_set_misc2_bits {
665  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
666  
667  	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
668  
669  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
670  
671  	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
672  
673  	u8         metadata_reg_c_7[0x20];
674  
675  	u8         metadata_reg_c_6[0x20];
676  
677  	u8         metadata_reg_c_5[0x20];
678  
679  	u8         metadata_reg_c_4[0x20];
680  
681  	u8         metadata_reg_c_3[0x20];
682  
683  	u8         metadata_reg_c_2[0x20];
684  
685  	u8         metadata_reg_c_1[0x20];
686  
687  	u8         metadata_reg_c_0[0x20];
688  
689  	u8         metadata_reg_a[0x20];
690  
691  	u8         reserved_at_1a0[0x8];
692  
693  	u8         macsec_syndrome[0x8];
694  	u8         ipsec_syndrome[0x8];
695  	u8         reserved_at_1b8[0x8];
696  
697  	u8         reserved_at_1c0[0x40];
698  };
699  
700  struct mlx5_ifc_fte_match_set_misc3_bits {
701  	u8         inner_tcp_seq_num[0x20];
702  
703  	u8         outer_tcp_seq_num[0x20];
704  
705  	u8         inner_tcp_ack_num[0x20];
706  
707  	u8         outer_tcp_ack_num[0x20];
708  
709  	u8	   reserved_at_80[0x8];
710  	u8         outer_vxlan_gpe_vni[0x18];
711  
712  	u8         outer_vxlan_gpe_next_protocol[0x8];
713  	u8         outer_vxlan_gpe_flags[0x8];
714  	u8	   reserved_at_b0[0x10];
715  
716  	u8	   icmp_header_data[0x20];
717  
718  	u8	   icmpv6_header_data[0x20];
719  
720  	u8	   icmp_type[0x8];
721  	u8	   icmp_code[0x8];
722  	u8	   icmpv6_type[0x8];
723  	u8	   icmpv6_code[0x8];
724  
725  	u8         geneve_tlv_option_0_data[0x20];
726  
727  	u8	   gtpu_teid[0x20];
728  
729  	u8	   gtpu_msg_type[0x8];
730  	u8	   gtpu_msg_flags[0x8];
731  	u8	   reserved_at_170[0x10];
732  
733  	u8	   gtpu_dw_2[0x20];
734  
735  	u8	   gtpu_first_ext_dw_0[0x20];
736  
737  	u8	   gtpu_dw_0[0x20];
738  
739  	u8	   reserved_at_1e0[0x20];
740  };
741  
742  struct mlx5_ifc_fte_match_set_misc4_bits {
743  	u8         prog_sample_field_value_0[0x20];
744  
745  	u8         prog_sample_field_id_0[0x20];
746  
747  	u8         prog_sample_field_value_1[0x20];
748  
749  	u8         prog_sample_field_id_1[0x20];
750  
751  	u8         prog_sample_field_value_2[0x20];
752  
753  	u8         prog_sample_field_id_2[0x20];
754  
755  	u8         prog_sample_field_value_3[0x20];
756  
757  	u8         prog_sample_field_id_3[0x20];
758  
759  	u8         reserved_at_100[0x100];
760  };
761  
762  struct mlx5_ifc_fte_match_set_misc5_bits {
763  	u8         macsec_tag_0[0x20];
764  
765  	u8         macsec_tag_1[0x20];
766  
767  	u8         macsec_tag_2[0x20];
768  
769  	u8         macsec_tag_3[0x20];
770  
771  	u8         tunnel_header_0[0x20];
772  
773  	u8         tunnel_header_1[0x20];
774  
775  	u8         tunnel_header_2[0x20];
776  
777  	u8         tunnel_header_3[0x20];
778  
779  	u8         reserved_at_100[0x100];
780  };
781  
782  struct mlx5_ifc_cmd_pas_bits {
783  	u8         pa_h[0x20];
784  
785  	u8         pa_l[0x14];
786  	u8         reserved_at_34[0xc];
787  };
788  
789  struct mlx5_ifc_uint64_bits {
790  	u8         hi[0x20];
791  
792  	u8         lo[0x20];
793  };
794  
795  enum {
796  	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
797  	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
798  	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
799  	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
800  	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
801  	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
802  	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
803  	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
804  	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
805  	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
806  };
807  
808  struct mlx5_ifc_ads_bits {
809  	u8         fl[0x1];
810  	u8         free_ar[0x1];
811  	u8         reserved_at_2[0xe];
812  	u8         pkey_index[0x10];
813  
814  	u8         plane_index[0x8];
815  	u8         grh[0x1];
816  	u8         mlid[0x7];
817  	u8         rlid[0x10];
818  
819  	u8         ack_timeout[0x5];
820  	u8         reserved_at_45[0x3];
821  	u8         src_addr_index[0x8];
822  	u8         reserved_at_50[0x4];
823  	u8         stat_rate[0x4];
824  	u8         hop_limit[0x8];
825  
826  	u8         reserved_at_60[0x4];
827  	u8         tclass[0x8];
828  	u8         flow_label[0x14];
829  
830  	u8         rgid_rip[16][0x8];
831  
832  	u8         reserved_at_100[0x4];
833  	u8         f_dscp[0x1];
834  	u8         f_ecn[0x1];
835  	u8         reserved_at_106[0x1];
836  	u8         f_eth_prio[0x1];
837  	u8         ecn[0x2];
838  	u8         dscp[0x6];
839  	u8         udp_sport[0x10];
840  
841  	u8         dei_cfi[0x1];
842  	u8         eth_prio[0x3];
843  	u8         sl[0x4];
844  	u8         vhca_port_num[0x8];
845  	u8         rmac_47_32[0x10];
846  
847  	u8         rmac_31_0[0x20];
848  };
849  
850  struct mlx5_ifc_flow_table_nic_cap_bits {
851  	u8         nic_rx_multi_path_tirs[0x1];
852  	u8         nic_rx_multi_path_tirs_fts[0x1];
853  	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
854  	u8	   reserved_at_3[0x4];
855  	u8	   sw_owner_reformat_supported[0x1];
856  	u8	   reserved_at_8[0x18];
857  
858  	u8	   encap_general_header[0x1];
859  	u8	   reserved_at_21[0xa];
860  	u8	   log_max_packet_reformat_context[0x5];
861  	u8	   reserved_at_30[0x6];
862  	u8	   max_encap_header_size[0xa];
863  	u8	   reserved_at_40[0x1c0];
864  
865  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
866  
867  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
868  
869  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
870  
871  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
872  
873  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
874  
875  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
876  
877  	u8         reserved_at_e00[0x600];
878  
879  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
880  
881  	u8         reserved_at_1480[0x80];
882  
883  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
884  
885  	u8         reserved_at_1580[0x280];
886  
887  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
888  
889  	u8         reserved_at_1880[0x780];
890  
891  	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
892  
893  	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
894  
895  	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
896  
897  	u8         reserved_at_20c0[0x5f40];
898  };
899  
900  struct mlx5_ifc_port_selection_cap_bits {
901  	u8         reserved_at_0[0x10];
902  	u8         port_select_flow_table[0x1];
903  	u8         reserved_at_11[0x1];
904  	u8         port_select_flow_table_bypass[0x1];
905  	u8         reserved_at_13[0xd];
906  
907  	u8         reserved_at_20[0x1e0];
908  
909  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
910  
911  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
912  
913  	u8         reserved_at_480[0x7b80];
914  };
915  
916  enum {
917  	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
918  	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
919  	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
920  	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
921  	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
922  	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
923  	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
924  	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
925  };
926  
927  struct mlx5_ifc_flow_table_eswitch_cap_bits {
928  	u8      fdb_to_vport_reg_c_id[0x8];
929  	u8      reserved_at_8[0x5];
930  	u8      fdb_uplink_hairpin[0x1];
931  	u8      fdb_multi_path_any_table_limit_regc[0x1];
932  	u8      reserved_at_f[0x1];
933  	u8      fdb_dynamic_tunnel[0x1];
934  	u8      reserved_at_11[0x1];
935  	u8      fdb_multi_path_any_table[0x1];
936  	u8      reserved_at_13[0x2];
937  	u8      fdb_modify_header_fwd_to_table[0x1];
938  	u8      fdb_ipv4_ttl_modify[0x1];
939  	u8      flow_source[0x1];
940  	u8      reserved_at_18[0x2];
941  	u8      multi_fdb_encap[0x1];
942  	u8      egress_acl_forward_to_vport[0x1];
943  	u8      fdb_multi_path_to_table[0x1];
944  	u8      reserved_at_1d[0x3];
945  
946  	u8      reserved_at_20[0x1e0];
947  
948  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
949  
950  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
951  
952  	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
953  
954  	u8      reserved_at_800[0xC00];
955  
956  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
957  
958  	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
959  
960  	u8      reserved_at_1500[0x300];
961  
962  	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
963  
964  	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
965  
966  	u8      sw_steering_uplink_icm_address_rx[0x40];
967  
968  	u8      sw_steering_uplink_icm_address_tx[0x40];
969  
970  	u8      reserved_at_1900[0x6700];
971  };
972  
973  struct mlx5_ifc_wqe_based_flow_table_cap_bits {
974  	u8         reserved_at_0[0x3];
975  	u8         log_max_num_ste[0x5];
976  	u8         reserved_at_8[0x3];
977  	u8         log_max_num_stc[0x5];
978  	u8         reserved_at_10[0x3];
979  	u8         log_max_num_rtc[0x5];
980  	u8         reserved_at_18[0x3];
981  	u8         log_max_num_header_modify_pattern[0x5];
982  
983  	u8         rtc_hash_split_table[0x1];
984  	u8         rtc_linear_lookup_table[0x1];
985  	u8         reserved_at_22[0x1];
986  	u8         stc_alloc_log_granularity[0x5];
987  	u8         reserved_at_28[0x3];
988  	u8         stc_alloc_log_max[0x5];
989  	u8         reserved_at_30[0x3];
990  	u8         ste_alloc_log_granularity[0x5];
991  	u8         reserved_at_38[0x3];
992  	u8         ste_alloc_log_max[0x5];
993  
994  	u8         reserved_at_40[0xb];
995  	u8         rtc_reparse_mode[0x5];
996  	u8         reserved_at_50[0x3];
997  	u8         rtc_index_mode[0x5];
998  	u8         reserved_at_58[0x3];
999  	u8         rtc_log_depth_max[0x5];
1000  
1001  	u8         reserved_at_60[0x10];
1002  	u8         ste_format[0x10];
1003  
1004  	u8         stc_action_type[0x80];
1005  
1006  	u8         header_insert_type[0x10];
1007  	u8         header_remove_type[0x10];
1008  
1009  	u8         trivial_match_definer[0x20];
1010  
1011  	u8         reserved_at_140[0x1b];
1012  	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1013  
1014  	u8         reserved_at_160[0x18];
1015  	u8         access_index_mode[0x8];
1016  
1017  	u8         reserved_at_180[0x10];
1018  	u8         ste_format_gen_wqe[0x10];
1019  
1020  	u8         linear_match_definer_reg_c3[0x20];
1021  
1022  	u8         fdb_jump_to_tir_stc[0x1];
1023  	u8         reserved_at_1c1[0x1f];
1024  };
1025  
1026  struct mlx5_ifc_esw_cap_bits {
1027  	u8         reserved_at_0[0x1d];
1028  	u8         merged_eswitch[0x1];
1029  	u8         reserved_at_1e[0x2];
1030  
1031  	u8         reserved_at_20[0x40];
1032  
1033  	u8         esw_manager_vport_number_valid[0x1];
1034  	u8         reserved_at_61[0xf];
1035  	u8         esw_manager_vport_number[0x10];
1036  
1037  	u8         reserved_at_80[0x780];
1038  };
1039  
1040  enum {
1041  	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1042  	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1043  };
1044  
1045  struct mlx5_ifc_e_switch_cap_bits {
1046  	u8         vport_svlan_strip[0x1];
1047  	u8         vport_cvlan_strip[0x1];
1048  	u8         vport_svlan_insert[0x1];
1049  	u8         vport_cvlan_insert_if_not_exist[0x1];
1050  	u8         vport_cvlan_insert_overwrite[0x1];
1051  	u8         reserved_at_5[0x1];
1052  	u8         vport_cvlan_insert_always[0x1];
1053  	u8         esw_shared_ingress_acl[0x1];
1054  	u8         esw_uplink_ingress_acl[0x1];
1055  	u8         root_ft_on_other_esw[0x1];
1056  	u8         reserved_at_a[0xf];
1057  	u8         esw_functions_changed[0x1];
1058  	u8         reserved_at_1a[0x1];
1059  	u8         ecpf_vport_exists[0x1];
1060  	u8         counter_eswitch_affinity[0x1];
1061  	u8         merged_eswitch[0x1];
1062  	u8         nic_vport_node_guid_modify[0x1];
1063  	u8         nic_vport_port_guid_modify[0x1];
1064  
1065  	u8         vxlan_encap_decap[0x1];
1066  	u8         nvgre_encap_decap[0x1];
1067  	u8         reserved_at_22[0x1];
1068  	u8         log_max_fdb_encap_uplink[0x5];
1069  	u8         reserved_at_21[0x3];
1070  	u8         log_max_packet_reformat_context[0x5];
1071  	u8         reserved_2b[0x6];
1072  	u8         max_encap_header_size[0xa];
1073  
1074  	u8         reserved_at_40[0xb];
1075  	u8         log_max_esw_sf[0x5];
1076  	u8         esw_sf_base_id[0x10];
1077  
1078  	u8         reserved_at_60[0x7a0];
1079  
1080  };
1081  
1082  struct mlx5_ifc_qos_cap_bits {
1083  	u8         packet_pacing[0x1];
1084  	u8         esw_scheduling[0x1];
1085  	u8         esw_bw_share[0x1];
1086  	u8         esw_rate_limit[0x1];
1087  	u8         reserved_at_4[0x1];
1088  	u8         packet_pacing_burst_bound[0x1];
1089  	u8         packet_pacing_typical_size[0x1];
1090  	u8         reserved_at_7[0x1];
1091  	u8         nic_sq_scheduling[0x1];
1092  	u8         nic_bw_share[0x1];
1093  	u8         nic_rate_limit[0x1];
1094  	u8         packet_pacing_uid[0x1];
1095  	u8         log_esw_max_sched_depth[0x4];
1096  	u8         reserved_at_10[0x10];
1097  
1098  	u8         reserved_at_20[0xb];
1099  	u8         log_max_qos_nic_queue_group[0x5];
1100  	u8         reserved_at_30[0x10];
1101  
1102  	u8         packet_pacing_max_rate[0x20];
1103  
1104  	u8         packet_pacing_min_rate[0x20];
1105  
1106  	u8         reserved_at_80[0x10];
1107  	u8         packet_pacing_rate_table_size[0x10];
1108  
1109  	u8         esw_element_type[0x10];
1110  	u8         esw_tsar_type[0x10];
1111  
1112  	u8         reserved_at_c0[0x10];
1113  	u8         max_qos_para_vport[0x10];
1114  
1115  	u8         max_tsar_bw_share[0x20];
1116  
1117  	u8         nic_element_type[0x10];
1118  	u8         nic_tsar_type[0x10];
1119  
1120  	u8         reserved_at_120[0x3];
1121  	u8         log_meter_aso_granularity[0x5];
1122  	u8         reserved_at_128[0x3];
1123  	u8         log_meter_aso_max_alloc[0x5];
1124  	u8         reserved_at_130[0x3];
1125  	u8         log_max_num_meter_aso[0x5];
1126  	u8         reserved_at_138[0x8];
1127  
1128  	u8         reserved_at_140[0x6c0];
1129  };
1130  
1131  struct mlx5_ifc_debug_cap_bits {
1132  	u8         core_dump_general[0x1];
1133  	u8         core_dump_qp[0x1];
1134  	u8         reserved_at_2[0x7];
1135  	u8         resource_dump[0x1];
1136  	u8         reserved_at_a[0x16];
1137  
1138  	u8         reserved_at_20[0x2];
1139  	u8         stall_detect[0x1];
1140  	u8         reserved_at_23[0x1d];
1141  
1142  	u8         reserved_at_40[0x7c0];
1143  };
1144  
1145  struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1146  	u8         csum_cap[0x1];
1147  	u8         vlan_cap[0x1];
1148  	u8         lro_cap[0x1];
1149  	u8         lro_psh_flag[0x1];
1150  	u8         lro_time_stamp[0x1];
1151  	u8         reserved_at_5[0x2];
1152  	u8         wqe_vlan_insert[0x1];
1153  	u8         self_lb_en_modifiable[0x1];
1154  	u8         reserved_at_9[0x2];
1155  	u8         max_lso_cap[0x5];
1156  	u8         multi_pkt_send_wqe[0x2];
1157  	u8	   wqe_inline_mode[0x2];
1158  	u8         rss_ind_tbl_cap[0x4];
1159  	u8         reg_umr_sq[0x1];
1160  	u8         scatter_fcs[0x1];
1161  	u8         enhanced_multi_pkt_send_wqe[0x1];
1162  	u8         tunnel_lso_const_out_ip_id[0x1];
1163  	u8         tunnel_lro_gre[0x1];
1164  	u8         tunnel_lro_vxlan[0x1];
1165  	u8         tunnel_stateless_gre[0x1];
1166  	u8         tunnel_stateless_vxlan[0x1];
1167  
1168  	u8         swp[0x1];
1169  	u8         swp_csum[0x1];
1170  	u8         swp_lso[0x1];
1171  	u8         cqe_checksum_full[0x1];
1172  	u8         tunnel_stateless_geneve_tx[0x1];
1173  	u8         tunnel_stateless_mpls_over_udp[0x1];
1174  	u8         tunnel_stateless_mpls_over_gre[0x1];
1175  	u8         tunnel_stateless_vxlan_gpe[0x1];
1176  	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1177  	u8         tunnel_stateless_ip_over_ip[0x1];
1178  	u8         insert_trailer[0x1];
1179  	u8         reserved_at_2b[0x1];
1180  	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1181  	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1182  	u8         reserved_at_2e[0x2];
1183  	u8         max_vxlan_udp_ports[0x8];
1184  	u8         swp_csum_l4_partial[0x1];
1185  	u8         reserved_at_39[0x5];
1186  	u8         max_geneve_opt_len[0x1];
1187  	u8         tunnel_stateless_geneve_rx[0x1];
1188  
1189  	u8         reserved_at_40[0x10];
1190  	u8         lro_min_mss_size[0x10];
1191  
1192  	u8         reserved_at_60[0x120];
1193  
1194  	u8         lro_timer_supported_periods[4][0x20];
1195  
1196  	u8         reserved_at_200[0x600];
1197  };
1198  
1199  enum {
1200  	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1201  	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1202  	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1203  };
1204  
1205  struct mlx5_ifc_roce_cap_bits {
1206  	u8         roce_apm[0x1];
1207  	u8         reserved_at_1[0x3];
1208  	u8         sw_r_roce_src_udp_port[0x1];
1209  	u8         fl_rc_qp_when_roce_disabled[0x1];
1210  	u8         fl_rc_qp_when_roce_enabled[0x1];
1211  	u8         roce_cc_general[0x1];
1212  	u8	   qp_ooo_transmit_default[0x1];
1213  	u8         reserved_at_9[0x15];
1214  	u8	   qp_ts_format[0x2];
1215  
1216  	u8         reserved_at_20[0x60];
1217  
1218  	u8         reserved_at_80[0xc];
1219  	u8         l3_type[0x4];
1220  	u8         reserved_at_90[0x8];
1221  	u8         roce_version[0x8];
1222  
1223  	u8         reserved_at_a0[0x10];
1224  	u8         r_roce_dest_udp_port[0x10];
1225  
1226  	u8         r_roce_max_src_udp_port[0x10];
1227  	u8         r_roce_min_src_udp_port[0x10];
1228  
1229  	u8         reserved_at_e0[0x10];
1230  	u8         roce_address_table_size[0x10];
1231  
1232  	u8         reserved_at_100[0x700];
1233  };
1234  
1235  struct mlx5_ifc_sync_steering_in_bits {
1236  	u8         opcode[0x10];
1237  	u8         uid[0x10];
1238  
1239  	u8         reserved_at_20[0x10];
1240  	u8         op_mod[0x10];
1241  
1242  	u8         reserved_at_40[0xc0];
1243  };
1244  
1245  struct mlx5_ifc_sync_steering_out_bits {
1246  	u8         status[0x8];
1247  	u8         reserved_at_8[0x18];
1248  
1249  	u8         syndrome[0x20];
1250  
1251  	u8         reserved_at_40[0x40];
1252  };
1253  
1254  struct mlx5_ifc_sync_crypto_in_bits {
1255  	u8         opcode[0x10];
1256  	u8         uid[0x10];
1257  
1258  	u8         reserved_at_20[0x10];
1259  	u8         op_mod[0x10];
1260  
1261  	u8         reserved_at_40[0x20];
1262  
1263  	u8         reserved_at_60[0x10];
1264  	u8         crypto_type[0x10];
1265  
1266  	u8         reserved_at_80[0x80];
1267  };
1268  
1269  struct mlx5_ifc_sync_crypto_out_bits {
1270  	u8         status[0x8];
1271  	u8         reserved_at_8[0x18];
1272  
1273  	u8         syndrome[0x20];
1274  
1275  	u8         reserved_at_40[0x40];
1276  };
1277  
1278  struct mlx5_ifc_device_mem_cap_bits {
1279  	u8         memic[0x1];
1280  	u8         reserved_at_1[0x1f];
1281  
1282  	u8         reserved_at_20[0xb];
1283  	u8         log_min_memic_alloc_size[0x5];
1284  	u8         reserved_at_30[0x8];
1285  	u8	   log_max_memic_addr_alignment[0x8];
1286  
1287  	u8         memic_bar_start_addr[0x40];
1288  
1289  	u8         memic_bar_size[0x20];
1290  
1291  	u8         max_memic_size[0x20];
1292  
1293  	u8         steering_sw_icm_start_address[0x40];
1294  
1295  	u8         reserved_at_100[0x8];
1296  	u8         log_header_modify_sw_icm_size[0x8];
1297  	u8         reserved_at_110[0x2];
1298  	u8         log_sw_icm_alloc_granularity[0x6];
1299  	u8         log_steering_sw_icm_size[0x8];
1300  
1301  	u8         log_indirect_encap_sw_icm_size[0x8];
1302  	u8         reserved_at_128[0x10];
1303  	u8         log_header_modify_pattern_sw_icm_size[0x8];
1304  
1305  	u8         header_modify_sw_icm_start_address[0x40];
1306  
1307  	u8         reserved_at_180[0x40];
1308  
1309  	u8         header_modify_pattern_sw_icm_start_address[0x40];
1310  
1311  	u8         memic_operations[0x20];
1312  
1313  	u8         reserved_at_220[0x20];
1314  
1315  	u8         indirect_encap_sw_icm_start_address[0x40];
1316  
1317  	u8         reserved_at_280[0x580];
1318  };
1319  
1320  struct mlx5_ifc_device_event_cap_bits {
1321  	u8         user_affiliated_events[4][0x40];
1322  
1323  	u8         user_unaffiliated_events[4][0x40];
1324  };
1325  
1326  struct mlx5_ifc_virtio_emulation_cap_bits {
1327  	u8         desc_tunnel_offload_type[0x1];
1328  	u8         eth_frame_offload_type[0x1];
1329  	u8         virtio_version_1_0[0x1];
1330  	u8         device_features_bits_mask[0xd];
1331  	u8         event_mode[0x8];
1332  	u8         virtio_queue_type[0x8];
1333  
1334  	u8         max_tunnel_desc[0x10];
1335  	u8         reserved_at_30[0x3];
1336  	u8         log_doorbell_stride[0x5];
1337  	u8         reserved_at_38[0x3];
1338  	u8         log_doorbell_bar_size[0x5];
1339  
1340  	u8         doorbell_bar_offset[0x40];
1341  
1342  	u8         max_emulated_devices[0x8];
1343  	u8         max_num_virtio_queues[0x18];
1344  
1345  	u8         reserved_at_a0[0x20];
1346  
1347  	u8	   reserved_at_c0[0x13];
1348  	u8         desc_group_mkey_supported[0x1];
1349  	u8         freeze_to_rdy_supported[0x1];
1350  	u8         reserved_at_d5[0xb];
1351  
1352  	u8         reserved_at_e0[0x20];
1353  
1354  	u8         umem_1_buffer_param_a[0x20];
1355  
1356  	u8         umem_1_buffer_param_b[0x20];
1357  
1358  	u8         umem_2_buffer_param_a[0x20];
1359  
1360  	u8         umem_2_buffer_param_b[0x20];
1361  
1362  	u8         umem_3_buffer_param_a[0x20];
1363  
1364  	u8         umem_3_buffer_param_b[0x20];
1365  
1366  	u8         reserved_at_1c0[0x640];
1367  };
1368  
1369  enum {
1370  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1371  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1372  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1373  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1374  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1375  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1376  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1377  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1378  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1379  };
1380  
1381  enum {
1382  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1383  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1384  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1385  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1386  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1387  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1388  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1389  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1390  	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1391  };
1392  
1393  struct mlx5_ifc_atomic_caps_bits {
1394  	u8         reserved_at_0[0x40];
1395  
1396  	u8         atomic_req_8B_endianness_mode[0x2];
1397  	u8         reserved_at_42[0x4];
1398  	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1399  
1400  	u8         reserved_at_47[0x19];
1401  
1402  	u8         reserved_at_60[0x20];
1403  
1404  	u8         reserved_at_80[0x10];
1405  	u8         atomic_operations[0x10];
1406  
1407  	u8         reserved_at_a0[0x10];
1408  	u8         atomic_size_qp[0x10];
1409  
1410  	u8         reserved_at_c0[0x10];
1411  	u8         atomic_size_dc[0x10];
1412  
1413  	u8         reserved_at_e0[0x720];
1414  };
1415  
1416  struct mlx5_ifc_odp_scheme_cap_bits {
1417  	u8         reserved_at_0[0x40];
1418  
1419  	u8         sig[0x1];
1420  	u8         reserved_at_41[0x4];
1421  	u8         page_prefetch[0x1];
1422  	u8         reserved_at_46[0x1a];
1423  
1424  	u8         reserved_at_60[0x20];
1425  
1426  	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1427  
1428  	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1429  
1430  	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1431  
1432  	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1433  
1434  	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1435  
1436  	u8         reserved_at_120[0xe0];
1437  };
1438  
1439  struct mlx5_ifc_odp_cap_bits {
1440  	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1441  
1442  	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1443  
1444  	u8         reserved_at_400[0x200];
1445  
1446  	u8         mem_page_fault[0x1];
1447  	u8         reserved_at_601[0x1f];
1448  
1449  	u8         reserved_at_620[0x1e0];
1450  };
1451  
1452  struct mlx5_ifc_tls_cap_bits {
1453  	u8         tls_1_2_aes_gcm_128[0x1];
1454  	u8         tls_1_3_aes_gcm_128[0x1];
1455  	u8         tls_1_2_aes_gcm_256[0x1];
1456  	u8         tls_1_3_aes_gcm_256[0x1];
1457  	u8         reserved_at_4[0x1c];
1458  
1459  	u8         reserved_at_20[0x7e0];
1460  };
1461  
1462  struct mlx5_ifc_ipsec_cap_bits {
1463  	u8         ipsec_full_offload[0x1];
1464  	u8         ipsec_crypto_offload[0x1];
1465  	u8         ipsec_esn[0x1];
1466  	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1467  	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1468  	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1469  	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1470  	u8         reserved_at_7[0x4];
1471  	u8         log_max_ipsec_offload[0x5];
1472  	u8         reserved_at_10[0x10];
1473  
1474  	u8         min_log_ipsec_full_replay_window[0x8];
1475  	u8         max_log_ipsec_full_replay_window[0x8];
1476  	u8         reserved_at_30[0x7d0];
1477  };
1478  
1479  struct mlx5_ifc_macsec_cap_bits {
1480  	u8    macsec_epn[0x1];
1481  	u8    reserved_at_1[0x2];
1482  	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1483  	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1484  	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1485  	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1486  	u8    reserved_at_7[0x4];
1487  	u8    log_max_macsec_offload[0x5];
1488  	u8    reserved_at_10[0x10];
1489  
1490  	u8    min_log_macsec_full_replay_window[0x8];
1491  	u8    max_log_macsec_full_replay_window[0x8];
1492  	u8    reserved_at_30[0x10];
1493  
1494  	u8    reserved_at_40[0x7c0];
1495  };
1496  
1497  enum {
1498  	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1499  	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1500  	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1501  	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1502  };
1503  
1504  enum {
1505  	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1506  	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1507  };
1508  
1509  enum {
1510  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1511  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1512  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1513  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1514  	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1515  };
1516  
1517  enum {
1518  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1519  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1520  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1521  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1522  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1523  	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1524  };
1525  
1526  enum {
1527  	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1528  	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1529  };
1530  
1531  enum {
1532  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1533  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1534  	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1535  };
1536  
1537  enum {
1538  	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1539  	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1540  };
1541  
1542  enum {
1543  	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1544  	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1545  	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1546  };
1547  
1548  enum {
1549  	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1550  	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1551  	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1552  	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1553  	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1554  	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1555  	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1556  	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1557  	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1558  	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1559  	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1560  	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1561  	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1562  	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1563  	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1564  	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1565  };
1566  
1567  enum {
1568  	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1569  	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1570  };
1571  
1572  #define MLX5_FC_BULK_SIZE_FACTOR 128
1573  
1574  enum mlx5_fc_bulk_alloc_bitmask {
1575  	MLX5_FC_BULK_128   = (1 << 0),
1576  	MLX5_FC_BULK_256   = (1 << 1),
1577  	MLX5_FC_BULK_512   = (1 << 2),
1578  	MLX5_FC_BULK_1024  = (1 << 3),
1579  	MLX5_FC_BULK_2048  = (1 << 4),
1580  	MLX5_FC_BULK_4096  = (1 << 5),
1581  	MLX5_FC_BULK_8192  = (1 << 6),
1582  	MLX5_FC_BULK_16384 = (1 << 7),
1583  };
1584  
1585  #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1586  
1587  #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1588  
1589  enum {
1590  	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1591  	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1592  	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1593  };
1594  
1595  struct mlx5_ifc_cmd_hca_cap_bits {
1596  	u8         reserved_at_0[0x6];
1597  	u8         page_request_disable[0x1];
1598  	u8         reserved_at_7[0x9];
1599  	u8         shared_object_to_user_object_allowed[0x1];
1600  	u8         reserved_at_13[0xe];
1601  	u8         vhca_resource_manager[0x1];
1602  
1603  	u8         hca_cap_2[0x1];
1604  	u8         create_lag_when_not_master_up[0x1];
1605  	u8         dtor[0x1];
1606  	u8         event_on_vhca_state_teardown_request[0x1];
1607  	u8         event_on_vhca_state_in_use[0x1];
1608  	u8         event_on_vhca_state_active[0x1];
1609  	u8         event_on_vhca_state_allocated[0x1];
1610  	u8         event_on_vhca_state_invalid[0x1];
1611  	u8         reserved_at_28[0x8];
1612  	u8         vhca_id[0x10];
1613  
1614  	u8         reserved_at_40[0x40];
1615  
1616  	u8         log_max_srq_sz[0x8];
1617  	u8         log_max_qp_sz[0x8];
1618  	u8         event_cap[0x1];
1619  	u8         reserved_at_91[0x2];
1620  	u8         isolate_vl_tc_new[0x1];
1621  	u8         reserved_at_94[0x4];
1622  	u8         prio_tag_required[0x1];
1623  	u8         reserved_at_99[0x2];
1624  	u8         log_max_qp[0x5];
1625  
1626  	u8         reserved_at_a0[0x3];
1627  	u8	   ece_support[0x1];
1628  	u8	   reserved_at_a4[0x5];
1629  	u8         reg_c_preserve[0x1];
1630  	u8         reserved_at_aa[0x1];
1631  	u8         log_max_srq[0x5];
1632  	u8         reserved_at_b0[0x1];
1633  	u8         uplink_follow[0x1];
1634  	u8         ts_cqe_to_dest_cqn[0x1];
1635  	u8         reserved_at_b3[0x6];
1636  	u8         go_back_n[0x1];
1637  	u8         reserved_at_ba[0x6];
1638  
1639  	u8         max_sgl_for_optimized_performance[0x8];
1640  	u8         log_max_cq_sz[0x8];
1641  	u8         relaxed_ordering_write_umr[0x1];
1642  	u8         relaxed_ordering_read_umr[0x1];
1643  	u8         reserved_at_d2[0x7];
1644  	u8         virtio_net_device_emualtion_manager[0x1];
1645  	u8         virtio_blk_device_emualtion_manager[0x1];
1646  	u8         log_max_cq[0x5];
1647  
1648  	u8         log_max_eq_sz[0x8];
1649  	u8         relaxed_ordering_write[0x1];
1650  	u8         relaxed_ordering_read_pci_enabled[0x1];
1651  	u8         log_max_mkey[0x6];
1652  	u8         reserved_at_f0[0x6];
1653  	u8	   terminate_scatter_list_mkey[0x1];
1654  	u8	   repeated_mkey[0x1];
1655  	u8         dump_fill_mkey[0x1];
1656  	u8         reserved_at_f9[0x2];
1657  	u8         fast_teardown[0x1];
1658  	u8         log_max_eq[0x4];
1659  
1660  	u8         max_indirection[0x8];
1661  	u8         fixed_buffer_size[0x1];
1662  	u8         log_max_mrw_sz[0x7];
1663  	u8         force_teardown[0x1];
1664  	u8         reserved_at_111[0x1];
1665  	u8         log_max_bsf_list_size[0x6];
1666  	u8         umr_extended_translation_offset[0x1];
1667  	u8         null_mkey[0x1];
1668  	u8         log_max_klm_list_size[0x6];
1669  
1670  	u8         reserved_at_120[0x2];
1671  	u8	   qpc_extension[0x1];
1672  	u8	   reserved_at_123[0x7];
1673  	u8         log_max_ra_req_dc[0x6];
1674  	u8         reserved_at_130[0x2];
1675  	u8         eth_wqe_too_small[0x1];
1676  	u8         reserved_at_133[0x6];
1677  	u8         vnic_env_cq_overrun[0x1];
1678  	u8         log_max_ra_res_dc[0x6];
1679  
1680  	u8         reserved_at_140[0x5];
1681  	u8         release_all_pages[0x1];
1682  	u8         must_not_use[0x1];
1683  	u8         reserved_at_147[0x2];
1684  	u8         roce_accl[0x1];
1685  	u8         log_max_ra_req_qp[0x6];
1686  	u8         reserved_at_150[0xa];
1687  	u8         log_max_ra_res_qp[0x6];
1688  
1689  	u8         end_pad[0x1];
1690  	u8         cc_query_allowed[0x1];
1691  	u8         cc_modify_allowed[0x1];
1692  	u8         start_pad[0x1];
1693  	u8         cache_line_128byte[0x1];
1694  	u8         reserved_at_165[0x4];
1695  	u8         rts2rts_qp_counters_set_id[0x1];
1696  	u8         reserved_at_16a[0x2];
1697  	u8         vnic_env_int_rq_oob[0x1];
1698  	u8         sbcam_reg[0x1];
1699  	u8         reserved_at_16e[0x1];
1700  	u8         qcam_reg[0x1];
1701  	u8         gid_table_size[0x10];
1702  
1703  	u8         out_of_seq_cnt[0x1];
1704  	u8         vport_counters[0x1];
1705  	u8         retransmission_q_counters[0x1];
1706  	u8         debug[0x1];
1707  	u8         modify_rq_counter_set_id[0x1];
1708  	u8         rq_delay_drop[0x1];
1709  	u8         max_qp_cnt[0xa];
1710  	u8         pkey_table_size[0x10];
1711  
1712  	u8         vport_group_manager[0x1];
1713  	u8         vhca_group_manager[0x1];
1714  	u8         ib_virt[0x1];
1715  	u8         eth_virt[0x1];
1716  	u8         vnic_env_queue_counters[0x1];
1717  	u8         ets[0x1];
1718  	u8         nic_flow_table[0x1];
1719  	u8         eswitch_manager[0x1];
1720  	u8         device_memory[0x1];
1721  	u8         mcam_reg[0x1];
1722  	u8         pcam_reg[0x1];
1723  	u8         local_ca_ack_delay[0x5];
1724  	u8         port_module_event[0x1];
1725  	u8         enhanced_error_q_counters[0x1];
1726  	u8         ports_check[0x1];
1727  	u8         reserved_at_1b3[0x1];
1728  	u8         disable_link_up[0x1];
1729  	u8         beacon_led[0x1];
1730  	u8         port_type[0x2];
1731  	u8         num_ports[0x8];
1732  
1733  	u8         reserved_at_1c0[0x1];
1734  	u8         pps[0x1];
1735  	u8         pps_modify[0x1];
1736  	u8         log_max_msg[0x5];
1737  	u8         reserved_at_1c8[0x4];
1738  	u8         max_tc[0x4];
1739  	u8         temp_warn_event[0x1];
1740  	u8         dcbx[0x1];
1741  	u8         general_notification_event[0x1];
1742  	u8         reserved_at_1d3[0x2];
1743  	u8         fpga[0x1];
1744  	u8         rol_s[0x1];
1745  	u8         rol_g[0x1];
1746  	u8         reserved_at_1d8[0x1];
1747  	u8         wol_s[0x1];
1748  	u8         wol_g[0x1];
1749  	u8         wol_a[0x1];
1750  	u8         wol_b[0x1];
1751  	u8         wol_m[0x1];
1752  	u8         wol_u[0x1];
1753  	u8         wol_p[0x1];
1754  
1755  	u8         stat_rate_support[0x10];
1756  	u8         reserved_at_1f0[0x1];
1757  	u8         pci_sync_for_fw_update_event[0x1];
1758  	u8         reserved_at_1f2[0x6];
1759  	u8         init2_lag_tx_port_affinity[0x1];
1760  	u8         reserved_at_1fa[0x2];
1761  	u8         wqe_based_flow_table_update_cap[0x1];
1762  	u8         cqe_version[0x4];
1763  
1764  	u8         compact_address_vector[0x1];
1765  	u8         striding_rq[0x1];
1766  	u8         reserved_at_202[0x1];
1767  	u8         ipoib_enhanced_offloads[0x1];
1768  	u8         ipoib_basic_offloads[0x1];
1769  	u8         reserved_at_205[0x1];
1770  	u8         repeated_block_disabled[0x1];
1771  	u8         umr_modify_entity_size_disabled[0x1];
1772  	u8         umr_modify_atomic_disabled[0x1];
1773  	u8         umr_indirect_mkey_disabled[0x1];
1774  	u8         umr_fence[0x2];
1775  	u8         dc_req_scat_data_cqe[0x1];
1776  	u8         reserved_at_20d[0x2];
1777  	u8         drain_sigerr[0x1];
1778  	u8         cmdif_checksum[0x2];
1779  	u8         sigerr_cqe[0x1];
1780  	u8         reserved_at_213[0x1];
1781  	u8         wq_signature[0x1];
1782  	u8         sctr_data_cqe[0x1];
1783  	u8         reserved_at_216[0x1];
1784  	u8         sho[0x1];
1785  	u8         tph[0x1];
1786  	u8         rf[0x1];
1787  	u8         dct[0x1];
1788  	u8         qos[0x1];
1789  	u8         eth_net_offloads[0x1];
1790  	u8         roce[0x1];
1791  	u8         atomic[0x1];
1792  	u8         reserved_at_21f[0x1];
1793  
1794  	u8         cq_oi[0x1];
1795  	u8         cq_resize[0x1];
1796  	u8         cq_moderation[0x1];
1797  	u8         cq_period_mode_modify[0x1];
1798  	u8         reserved_at_224[0x2];
1799  	u8         cq_eq_remap[0x1];
1800  	u8         pg[0x1];
1801  	u8         block_lb_mc[0x1];
1802  	u8         reserved_at_229[0x1];
1803  	u8         scqe_break_moderation[0x1];
1804  	u8         cq_period_start_from_cqe[0x1];
1805  	u8         cd[0x1];
1806  	u8         reserved_at_22d[0x1];
1807  	u8         apm[0x1];
1808  	u8         vector_calc[0x1];
1809  	u8         umr_ptr_rlky[0x1];
1810  	u8	   imaicl[0x1];
1811  	u8	   qp_packet_based[0x1];
1812  	u8         reserved_at_233[0x3];
1813  	u8         qkv[0x1];
1814  	u8         pkv[0x1];
1815  	u8         set_deth_sqpn[0x1];
1816  	u8         reserved_at_239[0x3];
1817  	u8         xrc[0x1];
1818  	u8         ud[0x1];
1819  	u8         uc[0x1];
1820  	u8         rc[0x1];
1821  
1822  	u8         uar_4k[0x1];
1823  	u8         reserved_at_241[0x7];
1824  	u8         fl_rc_qp_when_roce_disabled[0x1];
1825  	u8         regexp_params[0x1];
1826  	u8         uar_sz[0x6];
1827  	u8         port_selection_cap[0x1];
1828  	u8         reserved_at_251[0x1];
1829  	u8         umem_uid_0[0x1];
1830  	u8         reserved_at_253[0x5];
1831  	u8         log_pg_sz[0x8];
1832  
1833  	u8         bf[0x1];
1834  	u8         driver_version[0x1];
1835  	u8         pad_tx_eth_packet[0x1];
1836  	u8         reserved_at_263[0x3];
1837  	u8         mkey_by_name[0x1];
1838  	u8         reserved_at_267[0x4];
1839  
1840  	u8         log_bf_reg_size[0x5];
1841  
1842  	u8         reserved_at_270[0x3];
1843  	u8	   qp_error_syndrome[0x1];
1844  	u8	   reserved_at_274[0x2];
1845  	u8         lag_dct[0x2];
1846  	u8         lag_tx_port_affinity[0x1];
1847  	u8         lag_native_fdb_selection[0x1];
1848  	u8         reserved_at_27a[0x1];
1849  	u8         lag_master[0x1];
1850  	u8         num_lag_ports[0x4];
1851  
1852  	u8         reserved_at_280[0x10];
1853  	u8         max_wqe_sz_sq[0x10];
1854  
1855  	u8         reserved_at_2a0[0xb];
1856  	u8         shampo[0x1];
1857  	u8         reserved_at_2ac[0x4];
1858  	u8         max_wqe_sz_rq[0x10];
1859  
1860  	u8         max_flow_counter_31_16[0x10];
1861  	u8         max_wqe_sz_sq_dc[0x10];
1862  
1863  	u8         reserved_at_2e0[0x7];
1864  	u8         max_qp_mcg[0x19];
1865  
1866  	u8         reserved_at_300[0x10];
1867  	u8         flow_counter_bulk_alloc[0x8];
1868  	u8         log_max_mcg[0x8];
1869  
1870  	u8         reserved_at_320[0x3];
1871  	u8         log_max_transport_domain[0x5];
1872  	u8         reserved_at_328[0x2];
1873  	u8	   relaxed_ordering_read[0x1];
1874  	u8         log_max_pd[0x5];
1875  	u8         reserved_at_330[0x5];
1876  	u8         pcie_reset_using_hotreset_method[0x1];
1877  	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1878  	u8         vnic_env_cnt_steering_fail[0x1];
1879  	u8         vport_counter_local_loopback[0x1];
1880  	u8         q_counter_aggregation[0x1];
1881  	u8         q_counter_other_vport[0x1];
1882  	u8         log_max_xrcd[0x5];
1883  
1884  	u8         nic_receive_steering_discard[0x1];
1885  	u8         receive_discard_vport_down[0x1];
1886  	u8         transmit_discard_vport_down[0x1];
1887  	u8         eq_overrun_count[0x1];
1888  	u8         reserved_at_344[0x1];
1889  	u8         invalid_command_count[0x1];
1890  	u8         quota_exceeded_count[0x1];
1891  	u8         reserved_at_347[0x1];
1892  	u8         log_max_flow_counter_bulk[0x8];
1893  	u8         max_flow_counter_15_0[0x10];
1894  
1895  
1896  	u8         reserved_at_360[0x3];
1897  	u8         log_max_rq[0x5];
1898  	u8         reserved_at_368[0x3];
1899  	u8         log_max_sq[0x5];
1900  	u8         reserved_at_370[0x3];
1901  	u8         log_max_tir[0x5];
1902  	u8         reserved_at_378[0x3];
1903  	u8         log_max_tis[0x5];
1904  
1905  	u8         basic_cyclic_rcv_wqe[0x1];
1906  	u8         reserved_at_381[0x2];
1907  	u8         log_max_rmp[0x5];
1908  	u8         reserved_at_388[0x3];
1909  	u8         log_max_rqt[0x5];
1910  	u8         reserved_at_390[0x3];
1911  	u8         log_max_rqt_size[0x5];
1912  	u8         reserved_at_398[0x3];
1913  	u8         log_max_tis_per_sq[0x5];
1914  
1915  	u8         ext_stride_num_range[0x1];
1916  	u8         roce_rw_supported[0x1];
1917  	u8         log_max_current_uc_list_wr_supported[0x1];
1918  	u8         log_max_stride_sz_rq[0x5];
1919  	u8         reserved_at_3a8[0x3];
1920  	u8         log_min_stride_sz_rq[0x5];
1921  	u8         reserved_at_3b0[0x3];
1922  	u8         log_max_stride_sz_sq[0x5];
1923  	u8         reserved_at_3b8[0x3];
1924  	u8         log_min_stride_sz_sq[0x5];
1925  
1926  	u8         hairpin[0x1];
1927  	u8         reserved_at_3c1[0x2];
1928  	u8         log_max_hairpin_queues[0x5];
1929  	u8         reserved_at_3c8[0x3];
1930  	u8         log_max_hairpin_wq_data_sz[0x5];
1931  	u8         reserved_at_3d0[0x3];
1932  	u8         log_max_hairpin_num_packets[0x5];
1933  	u8         reserved_at_3d8[0x3];
1934  	u8         log_max_wq_sz[0x5];
1935  
1936  	u8         nic_vport_change_event[0x1];
1937  	u8         disable_local_lb_uc[0x1];
1938  	u8         disable_local_lb_mc[0x1];
1939  	u8         log_min_hairpin_wq_data_sz[0x5];
1940  	u8         reserved_at_3e8[0x1];
1941  	u8         silent_mode[0x1];
1942  	u8         vhca_state[0x1];
1943  	u8         log_max_vlan_list[0x5];
1944  	u8         reserved_at_3f0[0x3];
1945  	u8         log_max_current_mc_list[0x5];
1946  	u8         reserved_at_3f8[0x3];
1947  	u8         log_max_current_uc_list[0x5];
1948  
1949  	u8         general_obj_types[0x40];
1950  
1951  	u8         sq_ts_format[0x2];
1952  	u8         rq_ts_format[0x2];
1953  	u8         steering_format_version[0x4];
1954  	u8         create_qp_start_hint[0x18];
1955  
1956  	u8         reserved_at_460[0x1];
1957  	u8         ats[0x1];
1958  	u8         cross_vhca_rqt[0x1];
1959  	u8         log_max_uctx[0x5];
1960  	u8         reserved_at_468[0x1];
1961  	u8         crypto[0x1];
1962  	u8         ipsec_offload[0x1];
1963  	u8         log_max_umem[0x5];
1964  	u8         max_num_eqs[0x10];
1965  
1966  	u8         reserved_at_480[0x1];
1967  	u8         tls_tx[0x1];
1968  	u8         tls_rx[0x1];
1969  	u8         log_max_l2_table[0x5];
1970  	u8         reserved_at_488[0x8];
1971  	u8         log_uar_page_sz[0x10];
1972  
1973  	u8         reserved_at_4a0[0x20];
1974  	u8         device_frequency_mhz[0x20];
1975  	u8         device_frequency_khz[0x20];
1976  
1977  	u8         reserved_at_500[0x20];
1978  	u8	   num_of_uars_per_page[0x20];
1979  
1980  	u8         flex_parser_protocols[0x20];
1981  
1982  	u8         max_geneve_tlv_options[0x8];
1983  	u8         reserved_at_568[0x3];
1984  	u8         max_geneve_tlv_option_data_len[0x5];
1985  	u8         reserved_at_570[0x9];
1986  	u8         adv_virtualization[0x1];
1987  	u8         reserved_at_57a[0x6];
1988  
1989  	u8	   reserved_at_580[0xb];
1990  	u8	   log_max_dci_stream_channels[0x5];
1991  	u8	   reserved_at_590[0x3];
1992  	u8	   log_max_dci_errored_streams[0x5];
1993  	u8	   reserved_at_598[0x8];
1994  
1995  	u8         reserved_at_5a0[0x10];
1996  	u8         enhanced_cqe_compression[0x1];
1997  	u8         reserved_at_5b1[0x1];
1998  	u8         crossing_vhca_mkey[0x1];
1999  	u8         log_max_dek[0x5];
2000  	u8         reserved_at_5b8[0x4];
2001  	u8         mini_cqe_resp_stride_index[0x1];
2002  	u8         cqe_128_always[0x1];
2003  	u8         cqe_compression_128[0x1];
2004  	u8         cqe_compression[0x1];
2005  
2006  	u8         cqe_compression_timeout[0x10];
2007  	u8         cqe_compression_max_num[0x10];
2008  
2009  	u8         reserved_at_5e0[0x8];
2010  	u8         flex_parser_id_gtpu_dw_0[0x4];
2011  	u8         reserved_at_5ec[0x4];
2012  	u8         tag_matching[0x1];
2013  	u8         rndv_offload_rc[0x1];
2014  	u8         rndv_offload_dc[0x1];
2015  	u8         log_tag_matching_list_sz[0x5];
2016  	u8         reserved_at_5f8[0x3];
2017  	u8         log_max_xrq[0x5];
2018  
2019  	u8	   affiliate_nic_vport_criteria[0x8];
2020  	u8	   native_port_num[0x8];
2021  	u8	   num_vhca_ports[0x8];
2022  	u8         flex_parser_id_gtpu_teid[0x4];
2023  	u8         reserved_at_61c[0x2];
2024  	u8	   sw_owner_id[0x1];
2025  	u8         reserved_at_61f[0x1];
2026  
2027  	u8         max_num_of_monitor_counters[0x10];
2028  	u8         num_ppcnt_monitor_counters[0x10];
2029  
2030  	u8         max_num_sf[0x10];
2031  	u8         num_q_monitor_counters[0x10];
2032  
2033  	u8         reserved_at_660[0x20];
2034  
2035  	u8         sf[0x1];
2036  	u8         sf_set_partition[0x1];
2037  	u8         reserved_at_682[0x1];
2038  	u8         log_max_sf[0x5];
2039  	u8         apu[0x1];
2040  	u8         reserved_at_689[0x4];
2041  	u8         migration[0x1];
2042  	u8         reserved_at_68e[0x2];
2043  	u8         log_min_sf_size[0x8];
2044  	u8         max_num_sf_partitions[0x8];
2045  
2046  	u8         uctx_cap[0x20];
2047  
2048  	u8         reserved_at_6c0[0x4];
2049  	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2050  	u8         flex_parser_id_icmp_dw1[0x4];
2051  	u8         flex_parser_id_icmp_dw0[0x4];
2052  	u8         flex_parser_id_icmpv6_dw1[0x4];
2053  	u8         flex_parser_id_icmpv6_dw0[0x4];
2054  	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2055  	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2056  
2057  	u8         max_num_match_definer[0x10];
2058  	u8	   sf_base_id[0x10];
2059  
2060  	u8         flex_parser_id_gtpu_dw_2[0x4];
2061  	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2062  	u8	   num_total_dynamic_vf_msix[0x18];
2063  	u8	   reserved_at_720[0x14];
2064  	u8	   dynamic_msix_table_size[0xc];
2065  	u8	   reserved_at_740[0xc];
2066  	u8	   min_dynamic_vf_msix_table_size[0x4];
2067  	u8	   reserved_at_750[0x2];
2068  	u8	   data_direct[0x1];
2069  	u8	   reserved_at_753[0x1];
2070  	u8	   max_dynamic_vf_msix_table_size[0xc];
2071  
2072  	u8         reserved_at_760[0x3];
2073  	u8         log_max_num_header_modify_argument[0x5];
2074  	u8         log_header_modify_argument_granularity_offset[0x4];
2075  	u8         log_header_modify_argument_granularity[0x4];
2076  	u8         reserved_at_770[0x3];
2077  	u8         log_header_modify_argument_max_alloc[0x5];
2078  	u8         reserved_at_778[0x8];
2079  
2080  	u8	   vhca_tunnel_commands[0x40];
2081  	u8         match_definer_format_supported[0x40];
2082  };
2083  
2084  enum {
2085  	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2086  	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2087  };
2088  
2089  enum {
2090  	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2091  };
2092  
2093  struct mlx5_ifc_cmd_hca_cap_2_bits {
2094  	u8	   reserved_at_0[0x80];
2095  
2096  	u8         migratable[0x1];
2097  	u8         reserved_at_81[0x11];
2098  	u8         query_vuid[0x1];
2099  	u8         reserved_at_93[0x5];
2100  	u8         umr_log_entity_size_5[0x1];
2101  	u8         reserved_at_99[0x7];
2102  
2103  	u8	   max_reformat_insert_size[0x8];
2104  	u8	   max_reformat_insert_offset[0x8];
2105  	u8	   max_reformat_remove_size[0x8];
2106  	u8	   max_reformat_remove_offset[0x8];
2107  
2108  	u8	   reserved_at_c0[0x8];
2109  	u8	   migration_multi_load[0x1];
2110  	u8	   migration_tracking_state[0x1];
2111  	u8	   multiplane_qp_ud[0x1];
2112  	u8	   reserved_at_cb[0x5];
2113  	u8	   migration_in_chunks[0x1];
2114  	u8	   reserved_at_d1[0x1];
2115  	u8	   sf_eq_usage[0x1];
2116  	u8	   reserved_at_d3[0xd];
2117  
2118  	u8	   cross_vhca_object_to_object_supported[0x20];
2119  
2120  	u8	   allowed_object_for_other_vhca_access[0x40];
2121  
2122  	u8	   reserved_at_140[0x60];
2123  
2124  	u8	   flow_table_type_2_type[0x8];
2125  	u8	   reserved_at_1a8[0x2];
2126  	u8         format_select_dw_8_6_ext[0x1];
2127  	u8	   log_min_mkey_entity_size[0x5];
2128  	u8	   reserved_at_1b0[0x10];
2129  
2130  	u8	   reserved_at_1c0[0x60];
2131  
2132  	u8	   reserved_at_220[0x1];
2133  	u8	   sw_vhca_id_valid[0x1];
2134  	u8	   sw_vhca_id[0xe];
2135  	u8	   reserved_at_230[0x10];
2136  
2137  	u8	   reserved_at_240[0xb];
2138  	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2139  	u8	   reserved_at_250[0x10];
2140  
2141  	u8	   reserved_at_260[0x20];
2142  
2143  	u8	   format_select_dw_gtpu_dw_0[0x8];
2144  	u8	   format_select_dw_gtpu_dw_1[0x8];
2145  	u8	   format_select_dw_gtpu_dw_2[0x8];
2146  	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2147  
2148  	u8	   generate_wqe_type[0x20];
2149  
2150  	u8	   reserved_at_2c0[0xc0];
2151  
2152  	u8	   reserved_at_380[0xb];
2153  	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2154  	u8	   ec_vf_vport_base[0x10];
2155  
2156  	u8	   reserved_at_3a0[0xa];
2157  	u8	   max_mkey_log_entity_size_mtt[0x6];
2158  	u8	   max_rqt_vhca_id[0x10];
2159  
2160  	u8	   reserved_at_3c0[0x20];
2161  
2162  	u8	   reserved_at_3e0[0x10];
2163  	u8	   pcc_ifa2[0x1];
2164  	u8	   reserved_at_3f1[0xf];
2165  
2166  	u8	   reserved_at_400[0x1];
2167  	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2168  	u8	   reserved_at_402[0xe];
2169  	u8	   return_reg_id[0x10];
2170  
2171  	u8	   reserved_at_420[0x1c];
2172  	u8	   flow_table_hash_type[0x4];
2173  
2174  	u8	   reserved_at_440[0x8];
2175  	u8	   max_num_eqs_24b[0x18];
2176  	u8	   reserved_at_460[0x3a0];
2177  };
2178  
2179  enum mlx5_ifc_flow_destination_type {
2180  	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2181  	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2182  	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2183  	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2184  	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2185  	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2186  };
2187  
2188  enum mlx5_flow_table_miss_action {
2189  	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2190  	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2191  	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2192  };
2193  
2194  struct mlx5_ifc_dest_format_struct_bits {
2195  	u8         destination_type[0x8];
2196  	u8         destination_id[0x18];
2197  
2198  	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2199  	u8         packet_reformat[0x1];
2200  	u8         reserved_at_22[0x6];
2201  	u8         destination_table_type[0x8];
2202  	u8         destination_eswitch_owner_vhca_id[0x10];
2203  };
2204  
2205  struct mlx5_ifc_flow_counter_list_bits {
2206  	u8         flow_counter_id[0x20];
2207  
2208  	u8         reserved_at_20[0x20];
2209  };
2210  
2211  struct mlx5_ifc_extended_dest_format_bits {
2212  	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2213  
2214  	u8         packet_reformat_id[0x20];
2215  
2216  	u8         reserved_at_60[0x20];
2217  };
2218  
2219  union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2220  	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2221  	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2222  };
2223  
2224  struct mlx5_ifc_fte_match_param_bits {
2225  	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2226  
2227  	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2228  
2229  	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2230  
2231  	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2232  
2233  	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2234  
2235  	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2236  
2237  	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2238  
2239  	u8         reserved_at_e00[0x200];
2240  };
2241  
2242  enum {
2243  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2244  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2245  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2246  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2247  	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2248  };
2249  
2250  struct mlx5_ifc_rx_hash_field_select_bits {
2251  	u8         l3_prot_type[0x1];
2252  	u8         l4_prot_type[0x1];
2253  	u8         selected_fields[0x1e];
2254  };
2255  
2256  enum {
2257  	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2258  	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2259  };
2260  
2261  enum {
2262  	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2263  	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2264  };
2265  
2266  struct mlx5_ifc_wq_bits {
2267  	u8         wq_type[0x4];
2268  	u8         wq_signature[0x1];
2269  	u8         end_padding_mode[0x2];
2270  	u8         cd_slave[0x1];
2271  	u8         reserved_at_8[0x18];
2272  
2273  	u8         hds_skip_first_sge[0x1];
2274  	u8         log2_hds_buf_size[0x3];
2275  	u8         reserved_at_24[0x7];
2276  	u8         page_offset[0x5];
2277  	u8         lwm[0x10];
2278  
2279  	u8         reserved_at_40[0x8];
2280  	u8         pd[0x18];
2281  
2282  	u8         reserved_at_60[0x8];
2283  	u8         uar_page[0x18];
2284  
2285  	u8         dbr_addr[0x40];
2286  
2287  	u8         hw_counter[0x20];
2288  
2289  	u8         sw_counter[0x20];
2290  
2291  	u8         reserved_at_100[0xc];
2292  	u8         log_wq_stride[0x4];
2293  	u8         reserved_at_110[0x3];
2294  	u8         log_wq_pg_sz[0x5];
2295  	u8         reserved_at_118[0x3];
2296  	u8         log_wq_sz[0x5];
2297  
2298  	u8         dbr_umem_valid[0x1];
2299  	u8         wq_umem_valid[0x1];
2300  	u8         reserved_at_122[0x1];
2301  	u8         log_hairpin_num_packets[0x5];
2302  	u8         reserved_at_128[0x3];
2303  	u8         log_hairpin_data_sz[0x5];
2304  
2305  	u8         reserved_at_130[0x4];
2306  	u8         log_wqe_num_of_strides[0x4];
2307  	u8         two_byte_shift_en[0x1];
2308  	u8         reserved_at_139[0x4];
2309  	u8         log_wqe_stride_size[0x3];
2310  
2311  	u8         dbr_umem_id[0x20];
2312  	u8         wq_umem_id[0x20];
2313  
2314  	u8         wq_umem_offset[0x40];
2315  
2316  	u8         headers_mkey[0x20];
2317  
2318  	u8         shampo_enable[0x1];
2319  	u8         reserved_at_1e1[0x4];
2320  	u8         log_reservation_size[0x3];
2321  	u8         reserved_at_1e8[0x5];
2322  	u8         log_max_num_of_packets_per_reservation[0x3];
2323  	u8         reserved_at_1f0[0x6];
2324  	u8         log_headers_entry_size[0x2];
2325  	u8         reserved_at_1f8[0x4];
2326  	u8         log_headers_buffer_entry_num[0x4];
2327  
2328  	u8         reserved_at_200[0x400];
2329  
2330  	struct mlx5_ifc_cmd_pas_bits pas[];
2331  };
2332  
2333  struct mlx5_ifc_rq_num_bits {
2334  	u8         reserved_at_0[0x8];
2335  	u8         rq_num[0x18];
2336  };
2337  
2338  struct mlx5_ifc_rq_vhca_bits {
2339  	u8         reserved_at_0[0x8];
2340  	u8         rq_num[0x18];
2341  	u8         reserved_at_20[0x10];
2342  	u8         rq_vhca_id[0x10];
2343  };
2344  
2345  struct mlx5_ifc_mac_address_layout_bits {
2346  	u8         reserved_at_0[0x10];
2347  	u8         mac_addr_47_32[0x10];
2348  
2349  	u8         mac_addr_31_0[0x20];
2350  };
2351  
2352  struct mlx5_ifc_vlan_layout_bits {
2353  	u8         reserved_at_0[0x14];
2354  	u8         vlan[0x0c];
2355  
2356  	u8         reserved_at_20[0x20];
2357  };
2358  
2359  struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2360  	u8         reserved_at_0[0xa0];
2361  
2362  	u8         min_time_between_cnps[0x20];
2363  
2364  	u8         reserved_at_c0[0x12];
2365  	u8         cnp_dscp[0x6];
2366  	u8         reserved_at_d8[0x4];
2367  	u8         cnp_prio_mode[0x1];
2368  	u8         cnp_802p_prio[0x3];
2369  
2370  	u8         reserved_at_e0[0x720];
2371  };
2372  
2373  struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2374  	u8         reserved_at_0[0x60];
2375  
2376  	u8         reserved_at_60[0x4];
2377  	u8         clamp_tgt_rate[0x1];
2378  	u8         reserved_at_65[0x3];
2379  	u8         clamp_tgt_rate_after_time_inc[0x1];
2380  	u8         reserved_at_69[0x17];
2381  
2382  	u8         reserved_at_80[0x20];
2383  
2384  	u8         rpg_time_reset[0x20];
2385  
2386  	u8         rpg_byte_reset[0x20];
2387  
2388  	u8         rpg_threshold[0x20];
2389  
2390  	u8         rpg_max_rate[0x20];
2391  
2392  	u8         rpg_ai_rate[0x20];
2393  
2394  	u8         rpg_hai_rate[0x20];
2395  
2396  	u8         rpg_gd[0x20];
2397  
2398  	u8         rpg_min_dec_fac[0x20];
2399  
2400  	u8         rpg_min_rate[0x20];
2401  
2402  	u8         reserved_at_1c0[0xe0];
2403  
2404  	u8         rate_to_set_on_first_cnp[0x20];
2405  
2406  	u8         dce_tcp_g[0x20];
2407  
2408  	u8         dce_tcp_rtt[0x20];
2409  
2410  	u8         rate_reduce_monitor_period[0x20];
2411  
2412  	u8         reserved_at_320[0x20];
2413  
2414  	u8         initial_alpha_value[0x20];
2415  
2416  	u8         reserved_at_360[0x4a0];
2417  };
2418  
2419  struct mlx5_ifc_cong_control_r_roce_general_bits {
2420  	u8         reserved_at_0[0x80];
2421  
2422  	u8         reserved_at_80[0x10];
2423  	u8         rtt_resp_dscp_valid[0x1];
2424  	u8         reserved_at_91[0x9];
2425  	u8         rtt_resp_dscp[0x6];
2426  
2427  	u8         reserved_at_a0[0x760];
2428  };
2429  
2430  struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2431  	u8         reserved_at_0[0x80];
2432  
2433  	u8         rppp_max_rps[0x20];
2434  
2435  	u8         rpg_time_reset[0x20];
2436  
2437  	u8         rpg_byte_reset[0x20];
2438  
2439  	u8         rpg_threshold[0x20];
2440  
2441  	u8         rpg_max_rate[0x20];
2442  
2443  	u8         rpg_ai_rate[0x20];
2444  
2445  	u8         rpg_hai_rate[0x20];
2446  
2447  	u8         rpg_gd[0x20];
2448  
2449  	u8         rpg_min_dec_fac[0x20];
2450  
2451  	u8         rpg_min_rate[0x20];
2452  
2453  	u8         reserved_at_1c0[0x640];
2454  };
2455  
2456  enum {
2457  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2458  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2459  	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2460  };
2461  
2462  struct mlx5_ifc_resize_field_select_bits {
2463  	u8         resize_field_select[0x20];
2464  };
2465  
2466  struct mlx5_ifc_resource_dump_bits {
2467  	u8         more_dump[0x1];
2468  	u8         inline_dump[0x1];
2469  	u8         reserved_at_2[0xa];
2470  	u8         seq_num[0x4];
2471  	u8         segment_type[0x10];
2472  
2473  	u8         reserved_at_20[0x10];
2474  	u8         vhca_id[0x10];
2475  
2476  	u8         index1[0x20];
2477  
2478  	u8         index2[0x20];
2479  
2480  	u8         num_of_obj1[0x10];
2481  	u8         num_of_obj2[0x10];
2482  
2483  	u8         reserved_at_a0[0x20];
2484  
2485  	u8         device_opaque[0x40];
2486  
2487  	u8         mkey[0x20];
2488  
2489  	u8         size[0x20];
2490  
2491  	u8         address[0x40];
2492  
2493  	u8         inline_data[52][0x20];
2494  };
2495  
2496  struct mlx5_ifc_resource_dump_menu_record_bits {
2497  	u8         reserved_at_0[0x4];
2498  	u8         num_of_obj2_supports_active[0x1];
2499  	u8         num_of_obj2_supports_all[0x1];
2500  	u8         must_have_num_of_obj2[0x1];
2501  	u8         support_num_of_obj2[0x1];
2502  	u8         num_of_obj1_supports_active[0x1];
2503  	u8         num_of_obj1_supports_all[0x1];
2504  	u8         must_have_num_of_obj1[0x1];
2505  	u8         support_num_of_obj1[0x1];
2506  	u8         must_have_index2[0x1];
2507  	u8         support_index2[0x1];
2508  	u8         must_have_index1[0x1];
2509  	u8         support_index1[0x1];
2510  	u8         segment_type[0x10];
2511  
2512  	u8         segment_name[4][0x20];
2513  
2514  	u8         index1_name[4][0x20];
2515  
2516  	u8         index2_name[4][0x20];
2517  };
2518  
2519  struct mlx5_ifc_resource_dump_segment_header_bits {
2520  	u8         length_dw[0x10];
2521  	u8         segment_type[0x10];
2522  };
2523  
2524  struct mlx5_ifc_resource_dump_command_segment_bits {
2525  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2526  
2527  	u8         segment_called[0x10];
2528  	u8         vhca_id[0x10];
2529  
2530  	u8         index1[0x20];
2531  
2532  	u8         index2[0x20];
2533  
2534  	u8         num_of_obj1[0x10];
2535  	u8         num_of_obj2[0x10];
2536  };
2537  
2538  struct mlx5_ifc_resource_dump_error_segment_bits {
2539  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2540  
2541  	u8         reserved_at_20[0x10];
2542  	u8         syndrome_id[0x10];
2543  
2544  	u8         reserved_at_40[0x40];
2545  
2546  	u8         error[8][0x20];
2547  };
2548  
2549  struct mlx5_ifc_resource_dump_info_segment_bits {
2550  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2551  
2552  	u8         reserved_at_20[0x18];
2553  	u8         dump_version[0x8];
2554  
2555  	u8         hw_version[0x20];
2556  
2557  	u8         fw_version[0x20];
2558  };
2559  
2560  struct mlx5_ifc_resource_dump_menu_segment_bits {
2561  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2562  
2563  	u8         reserved_at_20[0x10];
2564  	u8         num_of_records[0x10];
2565  
2566  	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2567  };
2568  
2569  struct mlx5_ifc_resource_dump_resource_segment_bits {
2570  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2571  
2572  	u8         reserved_at_20[0x20];
2573  
2574  	u8         index1[0x20];
2575  
2576  	u8         index2[0x20];
2577  
2578  	u8         payload[][0x20];
2579  };
2580  
2581  struct mlx5_ifc_resource_dump_terminate_segment_bits {
2582  	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2583  };
2584  
2585  struct mlx5_ifc_menu_resource_dump_response_bits {
2586  	struct mlx5_ifc_resource_dump_info_segment_bits info;
2587  	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2588  	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2589  	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2590  };
2591  
2592  enum {
2593  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2594  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2595  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2596  	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2597  };
2598  
2599  struct mlx5_ifc_modify_field_select_bits {
2600  	u8         modify_field_select[0x20];
2601  };
2602  
2603  struct mlx5_ifc_field_select_r_roce_np_bits {
2604  	u8         field_select_r_roce_np[0x20];
2605  };
2606  
2607  struct mlx5_ifc_field_select_r_roce_rp_bits {
2608  	u8         field_select_r_roce_rp[0x20];
2609  };
2610  
2611  enum {
2612  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2613  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2614  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2615  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2616  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2617  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2618  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2619  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2620  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2621  	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2622  };
2623  
2624  struct mlx5_ifc_field_select_802_1qau_rp_bits {
2625  	u8         field_select_8021qaurp[0x20];
2626  };
2627  
2628  struct mlx5_ifc_phys_layer_cntrs_bits {
2629  	u8         time_since_last_clear_high[0x20];
2630  
2631  	u8         time_since_last_clear_low[0x20];
2632  
2633  	u8         symbol_errors_high[0x20];
2634  
2635  	u8         symbol_errors_low[0x20];
2636  
2637  	u8         sync_headers_errors_high[0x20];
2638  
2639  	u8         sync_headers_errors_low[0x20];
2640  
2641  	u8         edpl_bip_errors_lane0_high[0x20];
2642  
2643  	u8         edpl_bip_errors_lane0_low[0x20];
2644  
2645  	u8         edpl_bip_errors_lane1_high[0x20];
2646  
2647  	u8         edpl_bip_errors_lane1_low[0x20];
2648  
2649  	u8         edpl_bip_errors_lane2_high[0x20];
2650  
2651  	u8         edpl_bip_errors_lane2_low[0x20];
2652  
2653  	u8         edpl_bip_errors_lane3_high[0x20];
2654  
2655  	u8         edpl_bip_errors_lane3_low[0x20];
2656  
2657  	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2658  
2659  	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2660  
2661  	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2662  
2663  	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2664  
2665  	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2666  
2667  	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2668  
2669  	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2670  
2671  	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2672  
2673  	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2674  
2675  	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2676  
2677  	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2678  
2679  	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2680  
2681  	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2682  
2683  	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2684  
2685  	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2686  
2687  	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2688  
2689  	u8         rs_fec_corrected_blocks_high[0x20];
2690  
2691  	u8         rs_fec_corrected_blocks_low[0x20];
2692  
2693  	u8         rs_fec_uncorrectable_blocks_high[0x20];
2694  
2695  	u8         rs_fec_uncorrectable_blocks_low[0x20];
2696  
2697  	u8         rs_fec_no_errors_blocks_high[0x20];
2698  
2699  	u8         rs_fec_no_errors_blocks_low[0x20];
2700  
2701  	u8         rs_fec_single_error_blocks_high[0x20];
2702  
2703  	u8         rs_fec_single_error_blocks_low[0x20];
2704  
2705  	u8         rs_fec_corrected_symbols_total_high[0x20];
2706  
2707  	u8         rs_fec_corrected_symbols_total_low[0x20];
2708  
2709  	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2710  
2711  	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2712  
2713  	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2714  
2715  	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2716  
2717  	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2718  
2719  	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2720  
2721  	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2722  
2723  	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2724  
2725  	u8         link_down_events[0x20];
2726  
2727  	u8         successful_recovery_events[0x20];
2728  
2729  	u8         reserved_at_640[0x180];
2730  };
2731  
2732  struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2733  	u8         time_since_last_clear_high[0x20];
2734  
2735  	u8         time_since_last_clear_low[0x20];
2736  
2737  	u8         phy_received_bits_high[0x20];
2738  
2739  	u8         phy_received_bits_low[0x20];
2740  
2741  	u8         phy_symbol_errors_high[0x20];
2742  
2743  	u8         phy_symbol_errors_low[0x20];
2744  
2745  	u8         phy_corrected_bits_high[0x20];
2746  
2747  	u8         phy_corrected_bits_low[0x20];
2748  
2749  	u8         phy_corrected_bits_lane0_high[0x20];
2750  
2751  	u8         phy_corrected_bits_lane0_low[0x20];
2752  
2753  	u8         phy_corrected_bits_lane1_high[0x20];
2754  
2755  	u8         phy_corrected_bits_lane1_low[0x20];
2756  
2757  	u8         phy_corrected_bits_lane2_high[0x20];
2758  
2759  	u8         phy_corrected_bits_lane2_low[0x20];
2760  
2761  	u8         phy_corrected_bits_lane3_high[0x20];
2762  
2763  	u8         phy_corrected_bits_lane3_low[0x20];
2764  
2765  	u8         reserved_at_200[0x5c0];
2766  };
2767  
2768  struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2769  	u8	   symbol_error_counter[0x10];
2770  
2771  	u8         link_error_recovery_counter[0x8];
2772  
2773  	u8         link_downed_counter[0x8];
2774  
2775  	u8         port_rcv_errors[0x10];
2776  
2777  	u8         port_rcv_remote_physical_errors[0x10];
2778  
2779  	u8         port_rcv_switch_relay_errors[0x10];
2780  
2781  	u8         port_xmit_discards[0x10];
2782  
2783  	u8         port_xmit_constraint_errors[0x8];
2784  
2785  	u8         port_rcv_constraint_errors[0x8];
2786  
2787  	u8         reserved_at_70[0x8];
2788  
2789  	u8         link_overrun_errors[0x8];
2790  
2791  	u8	   reserved_at_80[0x10];
2792  
2793  	u8         vl_15_dropped[0x10];
2794  
2795  	u8	   reserved_at_a0[0x80];
2796  
2797  	u8         port_xmit_wait[0x20];
2798  };
2799  
2800  struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2801  	u8         reserved_at_0[0x300];
2802  
2803  	u8         port_xmit_data_high[0x20];
2804  
2805  	u8         port_xmit_data_low[0x20];
2806  
2807  	u8         port_rcv_data_high[0x20];
2808  
2809  	u8         port_rcv_data_low[0x20];
2810  
2811  	u8         port_xmit_pkts_high[0x20];
2812  
2813  	u8         port_xmit_pkts_low[0x20];
2814  
2815  	u8         port_rcv_pkts_high[0x20];
2816  
2817  	u8         port_rcv_pkts_low[0x20];
2818  
2819  	u8         reserved_at_400[0x80];
2820  
2821  	u8         port_unicast_xmit_pkts_high[0x20];
2822  
2823  	u8         port_unicast_xmit_pkts_low[0x20];
2824  
2825  	u8         port_multicast_xmit_pkts_high[0x20];
2826  
2827  	u8         port_multicast_xmit_pkts_low[0x20];
2828  
2829  	u8         port_unicast_rcv_pkts_high[0x20];
2830  
2831  	u8         port_unicast_rcv_pkts_low[0x20];
2832  
2833  	u8         port_multicast_rcv_pkts_high[0x20];
2834  
2835  	u8         port_multicast_rcv_pkts_low[0x20];
2836  
2837  	u8         reserved_at_580[0x240];
2838  };
2839  
2840  struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2841  	u8         transmit_queue_high[0x20];
2842  
2843  	u8         transmit_queue_low[0x20];
2844  
2845  	u8         no_buffer_discard_uc_high[0x20];
2846  
2847  	u8         no_buffer_discard_uc_low[0x20];
2848  
2849  	u8         reserved_at_80[0x740];
2850  };
2851  
2852  struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2853  	u8         wred_discard_high[0x20];
2854  
2855  	u8         wred_discard_low[0x20];
2856  
2857  	u8         ecn_marked_tc_high[0x20];
2858  
2859  	u8         ecn_marked_tc_low[0x20];
2860  
2861  	u8         reserved_at_80[0x740];
2862  };
2863  
2864  struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2865  	u8         rx_octets_high[0x20];
2866  
2867  	u8         rx_octets_low[0x20];
2868  
2869  	u8         reserved_at_40[0xc0];
2870  
2871  	u8         rx_frames_high[0x20];
2872  
2873  	u8         rx_frames_low[0x20];
2874  
2875  	u8         tx_octets_high[0x20];
2876  
2877  	u8         tx_octets_low[0x20];
2878  
2879  	u8         reserved_at_180[0xc0];
2880  
2881  	u8         tx_frames_high[0x20];
2882  
2883  	u8         tx_frames_low[0x20];
2884  
2885  	u8         rx_pause_high[0x20];
2886  
2887  	u8         rx_pause_low[0x20];
2888  
2889  	u8         rx_pause_duration_high[0x20];
2890  
2891  	u8         rx_pause_duration_low[0x20];
2892  
2893  	u8         tx_pause_high[0x20];
2894  
2895  	u8         tx_pause_low[0x20];
2896  
2897  	u8         tx_pause_duration_high[0x20];
2898  
2899  	u8         tx_pause_duration_low[0x20];
2900  
2901  	u8         rx_pause_transition_high[0x20];
2902  
2903  	u8         rx_pause_transition_low[0x20];
2904  
2905  	u8         rx_discards_high[0x20];
2906  
2907  	u8         rx_discards_low[0x20];
2908  
2909  	u8         device_stall_minor_watermark_cnt_high[0x20];
2910  
2911  	u8         device_stall_minor_watermark_cnt_low[0x20];
2912  
2913  	u8         device_stall_critical_watermark_cnt_high[0x20];
2914  
2915  	u8         device_stall_critical_watermark_cnt_low[0x20];
2916  
2917  	u8         reserved_at_480[0x340];
2918  };
2919  
2920  struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2921  	u8         port_transmit_wait_high[0x20];
2922  
2923  	u8         port_transmit_wait_low[0x20];
2924  
2925  	u8         reserved_at_40[0x100];
2926  
2927  	u8         rx_buffer_almost_full_high[0x20];
2928  
2929  	u8         rx_buffer_almost_full_low[0x20];
2930  
2931  	u8         rx_buffer_full_high[0x20];
2932  
2933  	u8         rx_buffer_full_low[0x20];
2934  
2935  	u8         rx_icrc_encapsulated_high[0x20];
2936  
2937  	u8         rx_icrc_encapsulated_low[0x20];
2938  
2939  	u8         reserved_at_200[0x5c0];
2940  };
2941  
2942  struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2943  	u8         dot3stats_alignment_errors_high[0x20];
2944  
2945  	u8         dot3stats_alignment_errors_low[0x20];
2946  
2947  	u8         dot3stats_fcs_errors_high[0x20];
2948  
2949  	u8         dot3stats_fcs_errors_low[0x20];
2950  
2951  	u8         dot3stats_single_collision_frames_high[0x20];
2952  
2953  	u8         dot3stats_single_collision_frames_low[0x20];
2954  
2955  	u8         dot3stats_multiple_collision_frames_high[0x20];
2956  
2957  	u8         dot3stats_multiple_collision_frames_low[0x20];
2958  
2959  	u8         dot3stats_sqe_test_errors_high[0x20];
2960  
2961  	u8         dot3stats_sqe_test_errors_low[0x20];
2962  
2963  	u8         dot3stats_deferred_transmissions_high[0x20];
2964  
2965  	u8         dot3stats_deferred_transmissions_low[0x20];
2966  
2967  	u8         dot3stats_late_collisions_high[0x20];
2968  
2969  	u8         dot3stats_late_collisions_low[0x20];
2970  
2971  	u8         dot3stats_excessive_collisions_high[0x20];
2972  
2973  	u8         dot3stats_excessive_collisions_low[0x20];
2974  
2975  	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2976  
2977  	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2978  
2979  	u8         dot3stats_carrier_sense_errors_high[0x20];
2980  
2981  	u8         dot3stats_carrier_sense_errors_low[0x20];
2982  
2983  	u8         dot3stats_frame_too_longs_high[0x20];
2984  
2985  	u8         dot3stats_frame_too_longs_low[0x20];
2986  
2987  	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2988  
2989  	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2990  
2991  	u8         dot3stats_symbol_errors_high[0x20];
2992  
2993  	u8         dot3stats_symbol_errors_low[0x20];
2994  
2995  	u8         dot3control_in_unknown_opcodes_high[0x20];
2996  
2997  	u8         dot3control_in_unknown_opcodes_low[0x20];
2998  
2999  	u8         dot3in_pause_frames_high[0x20];
3000  
3001  	u8         dot3in_pause_frames_low[0x20];
3002  
3003  	u8         dot3out_pause_frames_high[0x20];
3004  
3005  	u8         dot3out_pause_frames_low[0x20];
3006  
3007  	u8         reserved_at_400[0x3c0];
3008  };
3009  
3010  struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3011  	u8         ether_stats_drop_events_high[0x20];
3012  
3013  	u8         ether_stats_drop_events_low[0x20];
3014  
3015  	u8         ether_stats_octets_high[0x20];
3016  
3017  	u8         ether_stats_octets_low[0x20];
3018  
3019  	u8         ether_stats_pkts_high[0x20];
3020  
3021  	u8         ether_stats_pkts_low[0x20];
3022  
3023  	u8         ether_stats_broadcast_pkts_high[0x20];
3024  
3025  	u8         ether_stats_broadcast_pkts_low[0x20];
3026  
3027  	u8         ether_stats_multicast_pkts_high[0x20];
3028  
3029  	u8         ether_stats_multicast_pkts_low[0x20];
3030  
3031  	u8         ether_stats_crc_align_errors_high[0x20];
3032  
3033  	u8         ether_stats_crc_align_errors_low[0x20];
3034  
3035  	u8         ether_stats_undersize_pkts_high[0x20];
3036  
3037  	u8         ether_stats_undersize_pkts_low[0x20];
3038  
3039  	u8         ether_stats_oversize_pkts_high[0x20];
3040  
3041  	u8         ether_stats_oversize_pkts_low[0x20];
3042  
3043  	u8         ether_stats_fragments_high[0x20];
3044  
3045  	u8         ether_stats_fragments_low[0x20];
3046  
3047  	u8         ether_stats_jabbers_high[0x20];
3048  
3049  	u8         ether_stats_jabbers_low[0x20];
3050  
3051  	u8         ether_stats_collisions_high[0x20];
3052  
3053  	u8         ether_stats_collisions_low[0x20];
3054  
3055  	u8         ether_stats_pkts64octets_high[0x20];
3056  
3057  	u8         ether_stats_pkts64octets_low[0x20];
3058  
3059  	u8         ether_stats_pkts65to127octets_high[0x20];
3060  
3061  	u8         ether_stats_pkts65to127octets_low[0x20];
3062  
3063  	u8         ether_stats_pkts128to255octets_high[0x20];
3064  
3065  	u8         ether_stats_pkts128to255octets_low[0x20];
3066  
3067  	u8         ether_stats_pkts256to511octets_high[0x20];
3068  
3069  	u8         ether_stats_pkts256to511octets_low[0x20];
3070  
3071  	u8         ether_stats_pkts512to1023octets_high[0x20];
3072  
3073  	u8         ether_stats_pkts512to1023octets_low[0x20];
3074  
3075  	u8         ether_stats_pkts1024to1518octets_high[0x20];
3076  
3077  	u8         ether_stats_pkts1024to1518octets_low[0x20];
3078  
3079  	u8         ether_stats_pkts1519to2047octets_high[0x20];
3080  
3081  	u8         ether_stats_pkts1519to2047octets_low[0x20];
3082  
3083  	u8         ether_stats_pkts2048to4095octets_high[0x20];
3084  
3085  	u8         ether_stats_pkts2048to4095octets_low[0x20];
3086  
3087  	u8         ether_stats_pkts4096to8191octets_high[0x20];
3088  
3089  	u8         ether_stats_pkts4096to8191octets_low[0x20];
3090  
3091  	u8         ether_stats_pkts8192to10239octets_high[0x20];
3092  
3093  	u8         ether_stats_pkts8192to10239octets_low[0x20];
3094  
3095  	u8         reserved_at_540[0x280];
3096  };
3097  
3098  struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3099  	u8         if_in_octets_high[0x20];
3100  
3101  	u8         if_in_octets_low[0x20];
3102  
3103  	u8         if_in_ucast_pkts_high[0x20];
3104  
3105  	u8         if_in_ucast_pkts_low[0x20];
3106  
3107  	u8         if_in_discards_high[0x20];
3108  
3109  	u8         if_in_discards_low[0x20];
3110  
3111  	u8         if_in_errors_high[0x20];
3112  
3113  	u8         if_in_errors_low[0x20];
3114  
3115  	u8         if_in_unknown_protos_high[0x20];
3116  
3117  	u8         if_in_unknown_protos_low[0x20];
3118  
3119  	u8         if_out_octets_high[0x20];
3120  
3121  	u8         if_out_octets_low[0x20];
3122  
3123  	u8         if_out_ucast_pkts_high[0x20];
3124  
3125  	u8         if_out_ucast_pkts_low[0x20];
3126  
3127  	u8         if_out_discards_high[0x20];
3128  
3129  	u8         if_out_discards_low[0x20];
3130  
3131  	u8         if_out_errors_high[0x20];
3132  
3133  	u8         if_out_errors_low[0x20];
3134  
3135  	u8         if_in_multicast_pkts_high[0x20];
3136  
3137  	u8         if_in_multicast_pkts_low[0x20];
3138  
3139  	u8         if_in_broadcast_pkts_high[0x20];
3140  
3141  	u8         if_in_broadcast_pkts_low[0x20];
3142  
3143  	u8         if_out_multicast_pkts_high[0x20];
3144  
3145  	u8         if_out_multicast_pkts_low[0x20];
3146  
3147  	u8         if_out_broadcast_pkts_high[0x20];
3148  
3149  	u8         if_out_broadcast_pkts_low[0x20];
3150  
3151  	u8         reserved_at_340[0x480];
3152  };
3153  
3154  struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3155  	u8         a_frames_transmitted_ok_high[0x20];
3156  
3157  	u8         a_frames_transmitted_ok_low[0x20];
3158  
3159  	u8         a_frames_received_ok_high[0x20];
3160  
3161  	u8         a_frames_received_ok_low[0x20];
3162  
3163  	u8         a_frame_check_sequence_errors_high[0x20];
3164  
3165  	u8         a_frame_check_sequence_errors_low[0x20];
3166  
3167  	u8         a_alignment_errors_high[0x20];
3168  
3169  	u8         a_alignment_errors_low[0x20];
3170  
3171  	u8         a_octets_transmitted_ok_high[0x20];
3172  
3173  	u8         a_octets_transmitted_ok_low[0x20];
3174  
3175  	u8         a_octets_received_ok_high[0x20];
3176  
3177  	u8         a_octets_received_ok_low[0x20];
3178  
3179  	u8         a_multicast_frames_xmitted_ok_high[0x20];
3180  
3181  	u8         a_multicast_frames_xmitted_ok_low[0x20];
3182  
3183  	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3184  
3185  	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3186  
3187  	u8         a_multicast_frames_received_ok_high[0x20];
3188  
3189  	u8         a_multicast_frames_received_ok_low[0x20];
3190  
3191  	u8         a_broadcast_frames_received_ok_high[0x20];
3192  
3193  	u8         a_broadcast_frames_received_ok_low[0x20];
3194  
3195  	u8         a_in_range_length_errors_high[0x20];
3196  
3197  	u8         a_in_range_length_errors_low[0x20];
3198  
3199  	u8         a_out_of_range_length_field_high[0x20];
3200  
3201  	u8         a_out_of_range_length_field_low[0x20];
3202  
3203  	u8         a_frame_too_long_errors_high[0x20];
3204  
3205  	u8         a_frame_too_long_errors_low[0x20];
3206  
3207  	u8         a_symbol_error_during_carrier_high[0x20];
3208  
3209  	u8         a_symbol_error_during_carrier_low[0x20];
3210  
3211  	u8         a_mac_control_frames_transmitted_high[0x20];
3212  
3213  	u8         a_mac_control_frames_transmitted_low[0x20];
3214  
3215  	u8         a_mac_control_frames_received_high[0x20];
3216  
3217  	u8         a_mac_control_frames_received_low[0x20];
3218  
3219  	u8         a_unsupported_opcodes_received_high[0x20];
3220  
3221  	u8         a_unsupported_opcodes_received_low[0x20];
3222  
3223  	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3224  
3225  	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3226  
3227  	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3228  
3229  	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3230  
3231  	u8         reserved_at_4c0[0x300];
3232  };
3233  
3234  struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3235  	u8         life_time_counter_high[0x20];
3236  
3237  	u8         life_time_counter_low[0x20];
3238  
3239  	u8         rx_errors[0x20];
3240  
3241  	u8         tx_errors[0x20];
3242  
3243  	u8         l0_to_recovery_eieos[0x20];
3244  
3245  	u8         l0_to_recovery_ts[0x20];
3246  
3247  	u8         l0_to_recovery_framing[0x20];
3248  
3249  	u8         l0_to_recovery_retrain[0x20];
3250  
3251  	u8         crc_error_dllp[0x20];
3252  
3253  	u8         crc_error_tlp[0x20];
3254  
3255  	u8         tx_overflow_buffer_pkt_high[0x20];
3256  
3257  	u8         tx_overflow_buffer_pkt_low[0x20];
3258  
3259  	u8         outbound_stalled_reads[0x20];
3260  
3261  	u8         outbound_stalled_writes[0x20];
3262  
3263  	u8         outbound_stalled_reads_events[0x20];
3264  
3265  	u8         outbound_stalled_writes_events[0x20];
3266  
3267  	u8         reserved_at_200[0x5c0];
3268  };
3269  
3270  struct mlx5_ifc_cmd_inter_comp_event_bits {
3271  	u8         command_completion_vector[0x20];
3272  
3273  	u8         reserved_at_20[0xc0];
3274  };
3275  
3276  struct mlx5_ifc_stall_vl_event_bits {
3277  	u8         reserved_at_0[0x18];
3278  	u8         port_num[0x1];
3279  	u8         reserved_at_19[0x3];
3280  	u8         vl[0x4];
3281  
3282  	u8         reserved_at_20[0xa0];
3283  };
3284  
3285  struct mlx5_ifc_db_bf_congestion_event_bits {
3286  	u8         event_subtype[0x8];
3287  	u8         reserved_at_8[0x8];
3288  	u8         congestion_level[0x8];
3289  	u8         reserved_at_18[0x8];
3290  
3291  	u8         reserved_at_20[0xa0];
3292  };
3293  
3294  struct mlx5_ifc_gpio_event_bits {
3295  	u8         reserved_at_0[0x60];
3296  
3297  	u8         gpio_event_hi[0x20];
3298  
3299  	u8         gpio_event_lo[0x20];
3300  
3301  	u8         reserved_at_a0[0x40];
3302  };
3303  
3304  struct mlx5_ifc_port_state_change_event_bits {
3305  	u8         reserved_at_0[0x40];
3306  
3307  	u8         port_num[0x4];
3308  	u8         reserved_at_44[0x1c];
3309  
3310  	u8         reserved_at_60[0x80];
3311  };
3312  
3313  struct mlx5_ifc_dropped_packet_logged_bits {
3314  	u8         reserved_at_0[0xe0];
3315  };
3316  
3317  struct mlx5_ifc_default_timeout_bits {
3318  	u8         to_multiplier[0x3];
3319  	u8         reserved_at_3[0x9];
3320  	u8         to_value[0x14];
3321  };
3322  
3323  struct mlx5_ifc_dtor_reg_bits {
3324  	u8         reserved_at_0[0x20];
3325  
3326  	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3327  
3328  	u8         reserved_at_40[0x60];
3329  
3330  	struct mlx5_ifc_default_timeout_bits health_poll_to;
3331  
3332  	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3333  
3334  	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3335  
3336  	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3337  
3338  	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3339  
3340  	struct mlx5_ifc_default_timeout_bits tear_down_to;
3341  
3342  	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3343  
3344  	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3345  
3346  	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3347  
3348  	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3349  
3350  	u8         reserved_at_1c0[0x20];
3351  };
3352  
3353  enum {
3354  	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3355  	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3356  };
3357  
3358  struct mlx5_ifc_cq_error_bits {
3359  	u8         reserved_at_0[0x8];
3360  	u8         cqn[0x18];
3361  
3362  	u8         reserved_at_20[0x20];
3363  
3364  	u8         reserved_at_40[0x18];
3365  	u8         syndrome[0x8];
3366  
3367  	u8         reserved_at_60[0x80];
3368  };
3369  
3370  struct mlx5_ifc_rdma_page_fault_event_bits {
3371  	u8         bytes_committed[0x20];
3372  
3373  	u8         r_key[0x20];
3374  
3375  	u8         reserved_at_40[0x10];
3376  	u8         packet_len[0x10];
3377  
3378  	u8         rdma_op_len[0x20];
3379  
3380  	u8         rdma_va[0x40];
3381  
3382  	u8         reserved_at_c0[0x5];
3383  	u8         rdma[0x1];
3384  	u8         write[0x1];
3385  	u8         requestor[0x1];
3386  	u8         qp_number[0x18];
3387  };
3388  
3389  struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3390  	u8         bytes_committed[0x20];
3391  
3392  	u8         reserved_at_20[0x10];
3393  	u8         wqe_index[0x10];
3394  
3395  	u8         reserved_at_40[0x10];
3396  	u8         len[0x10];
3397  
3398  	u8         reserved_at_60[0x60];
3399  
3400  	u8         reserved_at_c0[0x5];
3401  	u8         rdma[0x1];
3402  	u8         write_read[0x1];
3403  	u8         requestor[0x1];
3404  	u8         qpn[0x18];
3405  };
3406  
3407  struct mlx5_ifc_qp_events_bits {
3408  	u8         reserved_at_0[0xa0];
3409  
3410  	u8         type[0x8];
3411  	u8         reserved_at_a8[0x18];
3412  
3413  	u8         reserved_at_c0[0x8];
3414  	u8         qpn_rqn_sqn[0x18];
3415  };
3416  
3417  struct mlx5_ifc_dct_events_bits {
3418  	u8         reserved_at_0[0xc0];
3419  
3420  	u8         reserved_at_c0[0x8];
3421  	u8         dct_number[0x18];
3422  };
3423  
3424  struct mlx5_ifc_comp_event_bits {
3425  	u8         reserved_at_0[0xc0];
3426  
3427  	u8         reserved_at_c0[0x8];
3428  	u8         cq_number[0x18];
3429  };
3430  
3431  enum {
3432  	MLX5_QPC_STATE_RST        = 0x0,
3433  	MLX5_QPC_STATE_INIT       = 0x1,
3434  	MLX5_QPC_STATE_RTR        = 0x2,
3435  	MLX5_QPC_STATE_RTS        = 0x3,
3436  	MLX5_QPC_STATE_SQER       = 0x4,
3437  	MLX5_QPC_STATE_ERR        = 0x6,
3438  	MLX5_QPC_STATE_SQD        = 0x7,
3439  	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3440  };
3441  
3442  enum {
3443  	MLX5_QPC_ST_RC            = 0x0,
3444  	MLX5_QPC_ST_UC            = 0x1,
3445  	MLX5_QPC_ST_UD            = 0x2,
3446  	MLX5_QPC_ST_XRC           = 0x3,
3447  	MLX5_QPC_ST_DCI           = 0x5,
3448  	MLX5_QPC_ST_QP0           = 0x7,
3449  	MLX5_QPC_ST_QP1           = 0x8,
3450  	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3451  	MLX5_QPC_ST_REG_UMR       = 0xc,
3452  };
3453  
3454  enum {
3455  	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3456  	MLX5_QPC_PM_STATE_REARM     = 0x1,
3457  	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3458  	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3459  };
3460  
3461  enum {
3462  	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3463  };
3464  
3465  enum {
3466  	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3467  	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3468  };
3469  
3470  enum {
3471  	MLX5_QPC_MTU_256_BYTES        = 0x1,
3472  	MLX5_QPC_MTU_512_BYTES        = 0x2,
3473  	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3474  	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3475  	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3476  	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3477  };
3478  
3479  enum {
3480  	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3481  	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3482  	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3483  	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3484  	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3485  	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3486  	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3487  	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3488  };
3489  
3490  enum {
3491  	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3492  	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3493  	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3494  };
3495  
3496  enum {
3497  	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3498  	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3499  	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3500  };
3501  
3502  enum {
3503  	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3504  	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3505  	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3506  };
3507  
3508  struct mlx5_ifc_qpc_bits {
3509  	u8         state[0x4];
3510  	u8         lag_tx_port_affinity[0x4];
3511  	u8         st[0x8];
3512  	u8         reserved_at_10[0x2];
3513  	u8	   isolate_vl_tc[0x1];
3514  	u8         pm_state[0x2];
3515  	u8         reserved_at_15[0x1];
3516  	u8         req_e2e_credit_mode[0x2];
3517  	u8         offload_type[0x4];
3518  	u8         end_padding_mode[0x2];
3519  	u8         reserved_at_1e[0x2];
3520  
3521  	u8         wq_signature[0x1];
3522  	u8         block_lb_mc[0x1];
3523  	u8         atomic_like_write_en[0x1];
3524  	u8         latency_sensitive[0x1];
3525  	u8         reserved_at_24[0x1];
3526  	u8         drain_sigerr[0x1];
3527  	u8         reserved_at_26[0x2];
3528  	u8         pd[0x18];
3529  
3530  	u8         mtu[0x3];
3531  	u8         log_msg_max[0x5];
3532  	u8         reserved_at_48[0x1];
3533  	u8         log_rq_size[0x4];
3534  	u8         log_rq_stride[0x3];
3535  	u8         no_sq[0x1];
3536  	u8         log_sq_size[0x4];
3537  	u8         reserved_at_55[0x1];
3538  	u8	   retry_mode[0x2];
3539  	u8	   ts_format[0x2];
3540  	u8         reserved_at_5a[0x1];
3541  	u8         rlky[0x1];
3542  	u8         ulp_stateless_offload_mode[0x4];
3543  
3544  	u8         counter_set_id[0x8];
3545  	u8         uar_page[0x18];
3546  
3547  	u8         reserved_at_80[0x8];
3548  	u8         user_index[0x18];
3549  
3550  	u8         reserved_at_a0[0x3];
3551  	u8         log_page_size[0x5];
3552  	u8         remote_qpn[0x18];
3553  
3554  	struct mlx5_ifc_ads_bits primary_address_path;
3555  
3556  	struct mlx5_ifc_ads_bits secondary_address_path;
3557  
3558  	u8         log_ack_req_freq[0x4];
3559  	u8         reserved_at_384[0x4];
3560  	u8         log_sra_max[0x3];
3561  	u8         reserved_at_38b[0x2];
3562  	u8         retry_count[0x3];
3563  	u8         rnr_retry[0x3];
3564  	u8         reserved_at_393[0x1];
3565  	u8         fre[0x1];
3566  	u8         cur_rnr_retry[0x3];
3567  	u8         cur_retry_count[0x3];
3568  	u8         reserved_at_39b[0x5];
3569  
3570  	u8         reserved_at_3a0[0x20];
3571  
3572  	u8         reserved_at_3c0[0x8];
3573  	u8         next_send_psn[0x18];
3574  
3575  	u8         reserved_at_3e0[0x3];
3576  	u8	   log_num_dci_stream_channels[0x5];
3577  	u8         cqn_snd[0x18];
3578  
3579  	u8         reserved_at_400[0x3];
3580  	u8	   log_num_dci_errored_streams[0x5];
3581  	u8         deth_sqpn[0x18];
3582  
3583  	u8         reserved_at_420[0x20];
3584  
3585  	u8         reserved_at_440[0x8];
3586  	u8         last_acked_psn[0x18];
3587  
3588  	u8         reserved_at_460[0x8];
3589  	u8         ssn[0x18];
3590  
3591  	u8         reserved_at_480[0x8];
3592  	u8         log_rra_max[0x3];
3593  	u8         reserved_at_48b[0x1];
3594  	u8         atomic_mode[0x4];
3595  	u8         rre[0x1];
3596  	u8         rwe[0x1];
3597  	u8         rae[0x1];
3598  	u8         reserved_at_493[0x1];
3599  	u8         page_offset[0x6];
3600  	u8         reserved_at_49a[0x3];
3601  	u8         cd_slave_receive[0x1];
3602  	u8         cd_slave_send[0x1];
3603  	u8         cd_master[0x1];
3604  
3605  	u8         reserved_at_4a0[0x3];
3606  	u8         min_rnr_nak[0x5];
3607  	u8         next_rcv_psn[0x18];
3608  
3609  	u8         reserved_at_4c0[0x8];
3610  	u8         xrcd[0x18];
3611  
3612  	u8         reserved_at_4e0[0x8];
3613  	u8         cqn_rcv[0x18];
3614  
3615  	u8         dbr_addr[0x40];
3616  
3617  	u8         q_key[0x20];
3618  
3619  	u8         reserved_at_560[0x5];
3620  	u8         rq_type[0x3];
3621  	u8         srqn_rmpn_xrqn[0x18];
3622  
3623  	u8         reserved_at_580[0x8];
3624  	u8         rmsn[0x18];
3625  
3626  	u8         hw_sq_wqebb_counter[0x10];
3627  	u8         sw_sq_wqebb_counter[0x10];
3628  
3629  	u8         hw_rq_counter[0x20];
3630  
3631  	u8         sw_rq_counter[0x20];
3632  
3633  	u8         reserved_at_600[0x20];
3634  
3635  	u8         reserved_at_620[0xf];
3636  	u8         cgs[0x1];
3637  	u8         cs_req[0x8];
3638  	u8         cs_res[0x8];
3639  
3640  	u8         dc_access_key[0x40];
3641  
3642  	u8         reserved_at_680[0x3];
3643  	u8         dbr_umem_valid[0x1];
3644  
3645  	u8         reserved_at_684[0xbc];
3646  };
3647  
3648  struct mlx5_ifc_roce_addr_layout_bits {
3649  	u8         source_l3_address[16][0x8];
3650  
3651  	u8         reserved_at_80[0x3];
3652  	u8         vlan_valid[0x1];
3653  	u8         vlan_id[0xc];
3654  	u8         source_mac_47_32[0x10];
3655  
3656  	u8         source_mac_31_0[0x20];
3657  
3658  	u8         reserved_at_c0[0x14];
3659  	u8         roce_l3_type[0x4];
3660  	u8         roce_version[0x8];
3661  
3662  	u8         reserved_at_e0[0x20];
3663  };
3664  
3665  struct mlx5_ifc_crypto_cap_bits {
3666  	u8    reserved_at_0[0x3];
3667  	u8    synchronize_dek[0x1];
3668  	u8    int_kek_manual[0x1];
3669  	u8    int_kek_auto[0x1];
3670  	u8    reserved_at_6[0x1a];
3671  
3672  	u8    reserved_at_20[0x3];
3673  	u8    log_dek_max_alloc[0x5];
3674  	u8    reserved_at_28[0x3];
3675  	u8    log_max_num_deks[0x5];
3676  	u8    reserved_at_30[0x10];
3677  
3678  	u8    reserved_at_40[0x20];
3679  
3680  	u8    reserved_at_60[0x3];
3681  	u8    log_dek_granularity[0x5];
3682  	u8    reserved_at_68[0x3];
3683  	u8    log_max_num_int_kek[0x5];
3684  	u8    sw_wrapped_dek[0x10];
3685  
3686  	u8    reserved_at_80[0x780];
3687  };
3688  
3689  union mlx5_ifc_hca_cap_union_bits {
3690  	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3691  	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3692  	struct mlx5_ifc_odp_cap_bits odp_cap;
3693  	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3694  	struct mlx5_ifc_roce_cap_bits roce_cap;
3695  	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3696  	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3697  	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3698  	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3699  	struct mlx5_ifc_esw_cap_bits esw_cap;
3700  	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3701  	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3702  	struct mlx5_ifc_qos_cap_bits qos_cap;
3703  	struct mlx5_ifc_debug_cap_bits debug_cap;
3704  	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3705  	struct mlx5_ifc_tls_cap_bits tls_cap;
3706  	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3707  	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3708  	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3709  	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3710  	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3711  	u8         reserved_at_0[0x8000];
3712  };
3713  
3714  enum {
3715  	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3716  	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3717  	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3718  	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3719  	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3720  	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3721  	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3722  	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3723  	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3724  	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3725  	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3726  	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3727  	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3728  	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3729  };
3730  
3731  enum {
3732  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3733  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3734  	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3735  };
3736  
3737  enum {
3738  	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3739  	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3740  };
3741  
3742  struct mlx5_ifc_vlan_bits {
3743  	u8         ethtype[0x10];
3744  	u8         prio[0x3];
3745  	u8         cfi[0x1];
3746  	u8         vid[0xc];
3747  };
3748  
3749  enum {
3750  	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3751  	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3752  	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3753  	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3754  };
3755  
3756  enum {
3757  	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3758  };
3759  
3760  struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3761  	u8        return_reg_id[0x4];
3762  	u8        aso_type[0x4];
3763  	u8        reserved_at_8[0x14];
3764  	u8        action[0x1];
3765  	u8        init_color[0x2];
3766  	u8        meter_id[0x1];
3767  };
3768  
3769  union mlx5_ifc_exe_aso_ctrl {
3770  	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3771  };
3772  
3773  struct mlx5_ifc_execute_aso_bits {
3774  	u8        valid[0x1];
3775  	u8        reserved_at_1[0x7];
3776  	u8        aso_object_id[0x18];
3777  
3778  	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3779  };
3780  
3781  struct mlx5_ifc_flow_context_bits {
3782  	struct mlx5_ifc_vlan_bits push_vlan;
3783  
3784  	u8         group_id[0x20];
3785  
3786  	u8         reserved_at_40[0x8];
3787  	u8         flow_tag[0x18];
3788  
3789  	u8         reserved_at_60[0x10];
3790  	u8         action[0x10];
3791  
3792  	u8         extended_destination[0x1];
3793  	u8         uplink_hairpin_en[0x1];
3794  	u8         flow_source[0x2];
3795  	u8         encrypt_decrypt_type[0x4];
3796  	u8         destination_list_size[0x18];
3797  
3798  	u8         reserved_at_a0[0x8];
3799  	u8         flow_counter_list_size[0x18];
3800  
3801  	u8         packet_reformat_id[0x20];
3802  
3803  	u8         modify_header_id[0x20];
3804  
3805  	struct mlx5_ifc_vlan_bits push_vlan_2;
3806  
3807  	u8         encrypt_decrypt_obj_id[0x20];
3808  	u8         reserved_at_140[0xc0];
3809  
3810  	struct mlx5_ifc_fte_match_param_bits match_value;
3811  
3812  	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3813  
3814  	u8         reserved_at_1300[0x500];
3815  
3816  	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3817  };
3818  
3819  enum {
3820  	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3821  	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3822  };
3823  
3824  struct mlx5_ifc_xrc_srqc_bits {
3825  	u8         state[0x4];
3826  	u8         log_xrc_srq_size[0x4];
3827  	u8         reserved_at_8[0x18];
3828  
3829  	u8         wq_signature[0x1];
3830  	u8         cont_srq[0x1];
3831  	u8         reserved_at_22[0x1];
3832  	u8         rlky[0x1];
3833  	u8         basic_cyclic_rcv_wqe[0x1];
3834  	u8         log_rq_stride[0x3];
3835  	u8         xrcd[0x18];
3836  
3837  	u8         page_offset[0x6];
3838  	u8         reserved_at_46[0x1];
3839  	u8         dbr_umem_valid[0x1];
3840  	u8         cqn[0x18];
3841  
3842  	u8         reserved_at_60[0x20];
3843  
3844  	u8         user_index_equal_xrc_srqn[0x1];
3845  	u8         reserved_at_81[0x1];
3846  	u8         log_page_size[0x6];
3847  	u8         user_index[0x18];
3848  
3849  	u8         reserved_at_a0[0x20];
3850  
3851  	u8         reserved_at_c0[0x8];
3852  	u8         pd[0x18];
3853  
3854  	u8         lwm[0x10];
3855  	u8         wqe_cnt[0x10];
3856  
3857  	u8         reserved_at_100[0x40];
3858  
3859  	u8         db_record_addr_h[0x20];
3860  
3861  	u8         db_record_addr_l[0x1e];
3862  	u8         reserved_at_17e[0x2];
3863  
3864  	u8         reserved_at_180[0x80];
3865  };
3866  
3867  struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3868  	u8         counter_error_queues[0x20];
3869  
3870  	u8         total_error_queues[0x20];
3871  
3872  	u8         send_queue_priority_update_flow[0x20];
3873  
3874  	u8         reserved_at_60[0x20];
3875  
3876  	u8         nic_receive_steering_discard[0x40];
3877  
3878  	u8         receive_discard_vport_down[0x40];
3879  
3880  	u8         transmit_discard_vport_down[0x40];
3881  
3882  	u8         async_eq_overrun[0x20];
3883  
3884  	u8         comp_eq_overrun[0x20];
3885  
3886  	u8         reserved_at_180[0x20];
3887  
3888  	u8         invalid_command[0x20];
3889  
3890  	u8         quota_exceeded_command[0x20];
3891  
3892  	u8         internal_rq_out_of_buffer[0x20];
3893  
3894  	u8         cq_overrun[0x20];
3895  
3896  	u8         eth_wqe_too_small[0x20];
3897  
3898  	u8         reserved_at_220[0xc0];
3899  
3900  	u8         generated_pkt_steering_fail[0x40];
3901  
3902  	u8         handled_pkt_steering_fail[0x40];
3903  
3904  	u8         reserved_at_360[0xc80];
3905  };
3906  
3907  struct mlx5_ifc_traffic_counter_bits {
3908  	u8         packets[0x40];
3909  
3910  	u8         octets[0x40];
3911  };
3912  
3913  struct mlx5_ifc_tisc_bits {
3914  	u8         strict_lag_tx_port_affinity[0x1];
3915  	u8         tls_en[0x1];
3916  	u8         reserved_at_2[0x2];
3917  	u8         lag_tx_port_affinity[0x04];
3918  
3919  	u8         reserved_at_8[0x4];
3920  	u8         prio[0x4];
3921  	u8         reserved_at_10[0x10];
3922  
3923  	u8         reserved_at_20[0x100];
3924  
3925  	u8         reserved_at_120[0x8];
3926  	u8         transport_domain[0x18];
3927  
3928  	u8         reserved_at_140[0x8];
3929  	u8         underlay_qpn[0x18];
3930  
3931  	u8         reserved_at_160[0x8];
3932  	u8         pd[0x18];
3933  
3934  	u8         reserved_at_180[0x380];
3935  };
3936  
3937  enum {
3938  	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3939  	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3940  };
3941  
3942  enum {
3943  	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3944  	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3945  };
3946  
3947  enum {
3948  	MLX5_RX_HASH_FN_NONE           = 0x0,
3949  	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3950  	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3951  };
3952  
3953  enum {
3954  	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3955  	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3956  };
3957  
3958  struct mlx5_ifc_tirc_bits {
3959  	u8         reserved_at_0[0x20];
3960  
3961  	u8         disp_type[0x4];
3962  	u8         tls_en[0x1];
3963  	u8         reserved_at_25[0x1b];
3964  
3965  	u8         reserved_at_40[0x40];
3966  
3967  	u8         reserved_at_80[0x4];
3968  	u8         lro_timeout_period_usecs[0x10];
3969  	u8         packet_merge_mask[0x4];
3970  	u8         lro_max_ip_payload_size[0x8];
3971  
3972  	u8         reserved_at_a0[0x40];
3973  
3974  	u8         reserved_at_e0[0x8];
3975  	u8         inline_rqn[0x18];
3976  
3977  	u8         rx_hash_symmetric[0x1];
3978  	u8         reserved_at_101[0x1];
3979  	u8         tunneled_offload_en[0x1];
3980  	u8         reserved_at_103[0x5];
3981  	u8         indirect_table[0x18];
3982  
3983  	u8         rx_hash_fn[0x4];
3984  	u8         reserved_at_124[0x2];
3985  	u8         self_lb_block[0x2];
3986  	u8         transport_domain[0x18];
3987  
3988  	u8         rx_hash_toeplitz_key[10][0x20];
3989  
3990  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3991  
3992  	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3993  
3994  	u8         reserved_at_2c0[0x4c0];
3995  };
3996  
3997  enum {
3998  	MLX5_SRQC_STATE_GOOD   = 0x0,
3999  	MLX5_SRQC_STATE_ERROR  = 0x1,
4000  };
4001  
4002  struct mlx5_ifc_srqc_bits {
4003  	u8         state[0x4];
4004  	u8         log_srq_size[0x4];
4005  	u8         reserved_at_8[0x18];
4006  
4007  	u8         wq_signature[0x1];
4008  	u8         cont_srq[0x1];
4009  	u8         reserved_at_22[0x1];
4010  	u8         rlky[0x1];
4011  	u8         reserved_at_24[0x1];
4012  	u8         log_rq_stride[0x3];
4013  	u8         xrcd[0x18];
4014  
4015  	u8         page_offset[0x6];
4016  	u8         reserved_at_46[0x2];
4017  	u8         cqn[0x18];
4018  
4019  	u8         reserved_at_60[0x20];
4020  
4021  	u8         reserved_at_80[0x2];
4022  	u8         log_page_size[0x6];
4023  	u8         reserved_at_88[0x18];
4024  
4025  	u8         reserved_at_a0[0x20];
4026  
4027  	u8         reserved_at_c0[0x8];
4028  	u8         pd[0x18];
4029  
4030  	u8         lwm[0x10];
4031  	u8         wqe_cnt[0x10];
4032  
4033  	u8         reserved_at_100[0x40];
4034  
4035  	u8         dbr_addr[0x40];
4036  
4037  	u8         reserved_at_180[0x80];
4038  };
4039  
4040  enum {
4041  	MLX5_SQC_STATE_RST  = 0x0,
4042  	MLX5_SQC_STATE_RDY  = 0x1,
4043  	MLX5_SQC_STATE_ERR  = 0x3,
4044  };
4045  
4046  struct mlx5_ifc_sqc_bits {
4047  	u8         rlky[0x1];
4048  	u8         cd_master[0x1];
4049  	u8         fre[0x1];
4050  	u8         flush_in_error_en[0x1];
4051  	u8         allow_multi_pkt_send_wqe[0x1];
4052  	u8	   min_wqe_inline_mode[0x3];
4053  	u8         state[0x4];
4054  	u8         reg_umr[0x1];
4055  	u8         allow_swp[0x1];
4056  	u8         hairpin[0x1];
4057  	u8         non_wire[0x1];
4058  	u8         reserved_at_10[0xa];
4059  	u8	   ts_format[0x2];
4060  	u8	   reserved_at_1c[0x4];
4061  
4062  	u8         reserved_at_20[0x8];
4063  	u8         user_index[0x18];
4064  
4065  	u8         reserved_at_40[0x8];
4066  	u8         cqn[0x18];
4067  
4068  	u8         reserved_at_60[0x8];
4069  	u8         hairpin_peer_rq[0x18];
4070  
4071  	u8         reserved_at_80[0x10];
4072  	u8         hairpin_peer_vhca[0x10];
4073  
4074  	u8         reserved_at_a0[0x20];
4075  
4076  	u8         reserved_at_c0[0x8];
4077  	u8         ts_cqe_to_dest_cqn[0x18];
4078  
4079  	u8         reserved_at_e0[0x10];
4080  	u8         packet_pacing_rate_limit_index[0x10];
4081  	u8         tis_lst_sz[0x10];
4082  	u8         qos_queue_group_id[0x10];
4083  
4084  	u8         reserved_at_120[0x40];
4085  
4086  	u8         reserved_at_160[0x8];
4087  	u8         tis_num_0[0x18];
4088  
4089  	struct mlx5_ifc_wq_bits wq;
4090  };
4091  
4092  enum {
4093  	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4094  	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4095  	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4096  	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4097  	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4098  };
4099  
4100  enum {
4101  	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4102  	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4103  	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4104  	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4105  	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4106  };
4107  
4108  struct mlx5_ifc_scheduling_context_bits {
4109  	u8         element_type[0x8];
4110  	u8         reserved_at_8[0x18];
4111  
4112  	u8         element_attributes[0x20];
4113  
4114  	u8         parent_element_id[0x20];
4115  
4116  	u8         reserved_at_60[0x40];
4117  
4118  	u8         bw_share[0x20];
4119  
4120  	u8         max_average_bw[0x20];
4121  
4122  	u8         reserved_at_e0[0x120];
4123  };
4124  
4125  struct mlx5_ifc_rqtc_bits {
4126  	u8    reserved_at_0[0xa0];
4127  
4128  	u8    reserved_at_a0[0x5];
4129  	u8    list_q_type[0x3];
4130  	u8    reserved_at_a8[0x8];
4131  	u8    rqt_max_size[0x10];
4132  
4133  	u8    rq_vhca_id_format[0x1];
4134  	u8    reserved_at_c1[0xf];
4135  	u8    rqt_actual_size[0x10];
4136  
4137  	u8    reserved_at_e0[0x6a0];
4138  
4139  	union {
4140  		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4141  		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4142  	};
4143  };
4144  
4145  enum {
4146  	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4147  	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4148  };
4149  
4150  enum {
4151  	MLX5_RQC_STATE_RST  = 0x0,
4152  	MLX5_RQC_STATE_RDY  = 0x1,
4153  	MLX5_RQC_STATE_ERR  = 0x3,
4154  };
4155  
4156  enum {
4157  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4158  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4159  	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4160  };
4161  
4162  enum {
4163  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4164  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4165  	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4166  };
4167  
4168  struct mlx5_ifc_rqc_bits {
4169  	u8         rlky[0x1];
4170  	u8	   delay_drop_en[0x1];
4171  	u8         scatter_fcs[0x1];
4172  	u8         vsd[0x1];
4173  	u8         mem_rq_type[0x4];
4174  	u8         state[0x4];
4175  	u8         reserved_at_c[0x1];
4176  	u8         flush_in_error_en[0x1];
4177  	u8         hairpin[0x1];
4178  	u8         reserved_at_f[0xb];
4179  	u8	   ts_format[0x2];
4180  	u8	   reserved_at_1c[0x4];
4181  
4182  	u8         reserved_at_20[0x8];
4183  	u8         user_index[0x18];
4184  
4185  	u8         reserved_at_40[0x8];
4186  	u8         cqn[0x18];
4187  
4188  	u8         counter_set_id[0x8];
4189  	u8         reserved_at_68[0x18];
4190  
4191  	u8         reserved_at_80[0x8];
4192  	u8         rmpn[0x18];
4193  
4194  	u8         reserved_at_a0[0x8];
4195  	u8         hairpin_peer_sq[0x18];
4196  
4197  	u8         reserved_at_c0[0x10];
4198  	u8         hairpin_peer_vhca[0x10];
4199  
4200  	u8         reserved_at_e0[0x46];
4201  	u8         shampo_no_match_alignment_granularity[0x2];
4202  	u8         reserved_at_128[0x6];
4203  	u8         shampo_match_criteria_type[0x2];
4204  	u8         reservation_timeout[0x10];
4205  
4206  	u8         reserved_at_140[0x40];
4207  
4208  	struct mlx5_ifc_wq_bits wq;
4209  };
4210  
4211  enum {
4212  	MLX5_RMPC_STATE_RDY  = 0x1,
4213  	MLX5_RMPC_STATE_ERR  = 0x3,
4214  };
4215  
4216  struct mlx5_ifc_rmpc_bits {
4217  	u8         reserved_at_0[0x8];
4218  	u8         state[0x4];
4219  	u8         reserved_at_c[0x14];
4220  
4221  	u8         basic_cyclic_rcv_wqe[0x1];
4222  	u8         reserved_at_21[0x1f];
4223  
4224  	u8         reserved_at_40[0x140];
4225  
4226  	struct mlx5_ifc_wq_bits wq;
4227  };
4228  
4229  enum {
4230  	VHCA_ID_TYPE_HW = 0,
4231  	VHCA_ID_TYPE_SW = 1,
4232  };
4233  
4234  struct mlx5_ifc_nic_vport_context_bits {
4235  	u8         reserved_at_0[0x5];
4236  	u8         min_wqe_inline_mode[0x3];
4237  	u8         reserved_at_8[0x15];
4238  	u8         disable_mc_local_lb[0x1];
4239  	u8         disable_uc_local_lb[0x1];
4240  	u8         roce_en[0x1];
4241  
4242  	u8         arm_change_event[0x1];
4243  	u8         reserved_at_21[0x1a];
4244  	u8         event_on_mtu[0x1];
4245  	u8         event_on_promisc_change[0x1];
4246  	u8         event_on_vlan_change[0x1];
4247  	u8         event_on_mc_address_change[0x1];
4248  	u8         event_on_uc_address_change[0x1];
4249  
4250  	u8         vhca_id_type[0x1];
4251  	u8         reserved_at_41[0xb];
4252  	u8	   affiliation_criteria[0x4];
4253  	u8	   affiliated_vhca_id[0x10];
4254  
4255  	u8	   reserved_at_60[0xa0];
4256  
4257  	u8	   reserved_at_100[0x1];
4258  	u8         sd_group[0x3];
4259  	u8	   reserved_at_104[0x1c];
4260  
4261  	u8	   reserved_at_120[0x10];
4262  	u8         mtu[0x10];
4263  
4264  	u8         system_image_guid[0x40];
4265  	u8         port_guid[0x40];
4266  	u8         node_guid[0x40];
4267  
4268  	u8         reserved_at_200[0x140];
4269  	u8         qkey_violation_counter[0x10];
4270  	u8         reserved_at_350[0x430];
4271  
4272  	u8         promisc_uc[0x1];
4273  	u8         promisc_mc[0x1];
4274  	u8         promisc_all[0x1];
4275  	u8         reserved_at_783[0x2];
4276  	u8         allowed_list_type[0x3];
4277  	u8         reserved_at_788[0xc];
4278  	u8         allowed_list_size[0xc];
4279  
4280  	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4281  
4282  	u8         reserved_at_7e0[0x20];
4283  
4284  	u8         current_uc_mac_address[][0x40];
4285  };
4286  
4287  enum {
4288  	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4289  	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4290  	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4291  	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4292  	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4293  	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4294  	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4295  };
4296  
4297  struct mlx5_ifc_mkc_bits {
4298  	u8         reserved_at_0[0x1];
4299  	u8         free[0x1];
4300  	u8         reserved_at_2[0x1];
4301  	u8         access_mode_4_2[0x3];
4302  	u8         reserved_at_6[0x7];
4303  	u8         relaxed_ordering_write[0x1];
4304  	u8         reserved_at_e[0x1];
4305  	u8         small_fence_on_rdma_read_response[0x1];
4306  	u8         umr_en[0x1];
4307  	u8         a[0x1];
4308  	u8         rw[0x1];
4309  	u8         rr[0x1];
4310  	u8         lw[0x1];
4311  	u8         lr[0x1];
4312  	u8         access_mode_1_0[0x2];
4313  	u8         reserved_at_18[0x2];
4314  	u8         ma_translation_mode[0x2];
4315  	u8         reserved_at_1c[0x4];
4316  
4317  	u8         qpn[0x18];
4318  	u8         mkey_7_0[0x8];
4319  
4320  	u8         reserved_at_40[0x20];
4321  
4322  	u8         length64[0x1];
4323  	u8         bsf_en[0x1];
4324  	u8         sync_umr[0x1];
4325  	u8         reserved_at_63[0x2];
4326  	u8         expected_sigerr_count[0x1];
4327  	u8         reserved_at_66[0x1];
4328  	u8         en_rinval[0x1];
4329  	u8         pd[0x18];
4330  
4331  	u8         start_addr[0x40];
4332  
4333  	u8         len[0x40];
4334  
4335  	u8         bsf_octword_size[0x20];
4336  
4337  	u8         reserved_at_120[0x60];
4338  
4339  	u8         crossing_target_vhca_id[0x10];
4340  	u8         reserved_at_190[0x10];
4341  
4342  	u8         translations_octword_size[0x20];
4343  
4344  	u8         reserved_at_1c0[0x19];
4345  	u8         relaxed_ordering_read[0x1];
4346  	u8         log_page_size[0x6];
4347  
4348  	u8         reserved_at_1e0[0x20];
4349  };
4350  
4351  struct mlx5_ifc_pkey_bits {
4352  	u8         reserved_at_0[0x10];
4353  	u8         pkey[0x10];
4354  };
4355  
4356  struct mlx5_ifc_array128_auto_bits {
4357  	u8         array128_auto[16][0x8];
4358  };
4359  
4360  struct mlx5_ifc_hca_vport_context_bits {
4361  	u8         field_select[0x20];
4362  
4363  	u8         reserved_at_20[0xe0];
4364  
4365  	u8         sm_virt_aware[0x1];
4366  	u8         has_smi[0x1];
4367  	u8         has_raw[0x1];
4368  	u8         grh_required[0x1];
4369  	u8         reserved_at_104[0x4];
4370  	u8         num_port_plane[0x8];
4371  	u8         port_physical_state[0x4];
4372  	u8         vport_state_policy[0x4];
4373  	u8         port_state[0x4];
4374  	u8         vport_state[0x4];
4375  
4376  	u8         reserved_at_120[0x20];
4377  
4378  	u8         system_image_guid[0x40];
4379  
4380  	u8         port_guid[0x40];
4381  
4382  	u8         node_guid[0x40];
4383  
4384  	u8         cap_mask1[0x20];
4385  
4386  	u8         cap_mask1_field_select[0x20];
4387  
4388  	u8         cap_mask2[0x20];
4389  
4390  	u8         cap_mask2_field_select[0x20];
4391  
4392  	u8         reserved_at_280[0x80];
4393  
4394  	u8         lid[0x10];
4395  	u8         reserved_at_310[0x4];
4396  	u8         init_type_reply[0x4];
4397  	u8         lmc[0x3];
4398  	u8         subnet_timeout[0x5];
4399  
4400  	u8         sm_lid[0x10];
4401  	u8         sm_sl[0x4];
4402  	u8         reserved_at_334[0xc];
4403  
4404  	u8         qkey_violation_counter[0x10];
4405  	u8         pkey_violation_counter[0x10];
4406  
4407  	u8         reserved_at_360[0xca0];
4408  };
4409  
4410  struct mlx5_ifc_esw_vport_context_bits {
4411  	u8         fdb_to_vport_reg_c[0x1];
4412  	u8         reserved_at_1[0x2];
4413  	u8         vport_svlan_strip[0x1];
4414  	u8         vport_cvlan_strip[0x1];
4415  	u8         vport_svlan_insert[0x1];
4416  	u8         vport_cvlan_insert[0x2];
4417  	u8         fdb_to_vport_reg_c_id[0x8];
4418  	u8         reserved_at_10[0x10];
4419  
4420  	u8         reserved_at_20[0x20];
4421  
4422  	u8         svlan_cfi[0x1];
4423  	u8         svlan_pcp[0x3];
4424  	u8         svlan_id[0xc];
4425  	u8         cvlan_cfi[0x1];
4426  	u8         cvlan_pcp[0x3];
4427  	u8         cvlan_id[0xc];
4428  
4429  	u8         reserved_at_60[0x720];
4430  
4431  	u8         sw_steering_vport_icm_address_rx[0x40];
4432  
4433  	u8         sw_steering_vport_icm_address_tx[0x40];
4434  };
4435  
4436  enum {
4437  	MLX5_EQC_STATUS_OK                = 0x0,
4438  	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4439  };
4440  
4441  enum {
4442  	MLX5_EQC_ST_ARMED  = 0x9,
4443  	MLX5_EQC_ST_FIRED  = 0xa,
4444  };
4445  
4446  struct mlx5_ifc_eqc_bits {
4447  	u8         status[0x4];
4448  	u8         reserved_at_4[0x9];
4449  	u8         ec[0x1];
4450  	u8         oi[0x1];
4451  	u8         reserved_at_f[0x5];
4452  	u8         st[0x4];
4453  	u8         reserved_at_18[0x8];
4454  
4455  	u8         reserved_at_20[0x20];
4456  
4457  	u8         reserved_at_40[0x14];
4458  	u8         page_offset[0x6];
4459  	u8         reserved_at_5a[0x6];
4460  
4461  	u8         reserved_at_60[0x3];
4462  	u8         log_eq_size[0x5];
4463  	u8         uar_page[0x18];
4464  
4465  	u8         reserved_at_80[0x20];
4466  
4467  	u8         reserved_at_a0[0x14];
4468  	u8         intr[0xc];
4469  
4470  	u8         reserved_at_c0[0x3];
4471  	u8         log_page_size[0x5];
4472  	u8         reserved_at_c8[0x18];
4473  
4474  	u8         reserved_at_e0[0x60];
4475  
4476  	u8         reserved_at_140[0x8];
4477  	u8         consumer_counter[0x18];
4478  
4479  	u8         reserved_at_160[0x8];
4480  	u8         producer_counter[0x18];
4481  
4482  	u8         reserved_at_180[0x80];
4483  };
4484  
4485  enum {
4486  	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4487  	MLX5_DCTC_STATE_DRAINING  = 0x1,
4488  	MLX5_DCTC_STATE_DRAINED   = 0x2,
4489  };
4490  
4491  enum {
4492  	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4493  	MLX5_DCTC_CS_RES_NA         = 0x1,
4494  	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4495  };
4496  
4497  enum {
4498  	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4499  	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4500  	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4501  	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4502  	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4503  };
4504  
4505  struct mlx5_ifc_dctc_bits {
4506  	u8         reserved_at_0[0x4];
4507  	u8         state[0x4];
4508  	u8         reserved_at_8[0x18];
4509  
4510  	u8         reserved_at_20[0x8];
4511  	u8         user_index[0x18];
4512  
4513  	u8         reserved_at_40[0x8];
4514  	u8         cqn[0x18];
4515  
4516  	u8         counter_set_id[0x8];
4517  	u8         atomic_mode[0x4];
4518  	u8         rre[0x1];
4519  	u8         rwe[0x1];
4520  	u8         rae[0x1];
4521  	u8         atomic_like_write_en[0x1];
4522  	u8         latency_sensitive[0x1];
4523  	u8         rlky[0x1];
4524  	u8         free_ar[0x1];
4525  	u8         reserved_at_73[0xd];
4526  
4527  	u8         reserved_at_80[0x8];
4528  	u8         cs_res[0x8];
4529  	u8         reserved_at_90[0x3];
4530  	u8         min_rnr_nak[0x5];
4531  	u8         reserved_at_98[0x8];
4532  
4533  	u8         reserved_at_a0[0x8];
4534  	u8         srqn_xrqn[0x18];
4535  
4536  	u8         reserved_at_c0[0x8];
4537  	u8         pd[0x18];
4538  
4539  	u8         tclass[0x8];
4540  	u8         reserved_at_e8[0x4];
4541  	u8         flow_label[0x14];
4542  
4543  	u8         dc_access_key[0x40];
4544  
4545  	u8         reserved_at_140[0x5];
4546  	u8         mtu[0x3];
4547  	u8         port[0x8];
4548  	u8         pkey_index[0x10];
4549  
4550  	u8         reserved_at_160[0x8];
4551  	u8         my_addr_index[0x8];
4552  	u8         reserved_at_170[0x8];
4553  	u8         hop_limit[0x8];
4554  
4555  	u8         dc_access_key_violation_count[0x20];
4556  
4557  	u8         reserved_at_1a0[0x14];
4558  	u8         dei_cfi[0x1];
4559  	u8         eth_prio[0x3];
4560  	u8         ecn[0x2];
4561  	u8         dscp[0x6];
4562  
4563  	u8         reserved_at_1c0[0x20];
4564  	u8         ece[0x20];
4565  };
4566  
4567  enum {
4568  	MLX5_CQC_STATUS_OK             = 0x0,
4569  	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4570  	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4571  };
4572  
4573  enum {
4574  	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4575  	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4576  };
4577  
4578  enum {
4579  	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4580  	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4581  	MLX5_CQC_ST_FIRED                                 = 0xa,
4582  };
4583  
4584  enum mlx5_cq_period_mode {
4585  	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4586  	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4587  	MLX5_CQ_PERIOD_NUM_MODES,
4588  };
4589  
4590  struct mlx5_ifc_cqc_bits {
4591  	u8         status[0x4];
4592  	u8         reserved_at_4[0x2];
4593  	u8         dbr_umem_valid[0x1];
4594  	u8         apu_cq[0x1];
4595  	u8         cqe_sz[0x3];
4596  	u8         cc[0x1];
4597  	u8         reserved_at_c[0x1];
4598  	u8         scqe_break_moderation_en[0x1];
4599  	u8         oi[0x1];
4600  	u8         cq_period_mode[0x2];
4601  	u8         cqe_comp_en[0x1];
4602  	u8         mini_cqe_res_format[0x2];
4603  	u8         st[0x4];
4604  	u8         reserved_at_18[0x6];
4605  	u8         cqe_compression_layout[0x2];
4606  
4607  	u8         reserved_at_20[0x20];
4608  
4609  	u8         reserved_at_40[0x14];
4610  	u8         page_offset[0x6];
4611  	u8         reserved_at_5a[0x6];
4612  
4613  	u8         reserved_at_60[0x3];
4614  	u8         log_cq_size[0x5];
4615  	u8         uar_page[0x18];
4616  
4617  	u8         reserved_at_80[0x4];
4618  	u8         cq_period[0xc];
4619  	u8         cq_max_count[0x10];
4620  
4621  	u8         c_eqn_or_apu_element[0x20];
4622  
4623  	u8         reserved_at_c0[0x3];
4624  	u8         log_page_size[0x5];
4625  	u8         reserved_at_c8[0x18];
4626  
4627  	u8         reserved_at_e0[0x20];
4628  
4629  	u8         reserved_at_100[0x8];
4630  	u8         last_notified_index[0x18];
4631  
4632  	u8         reserved_at_120[0x8];
4633  	u8         last_solicit_index[0x18];
4634  
4635  	u8         reserved_at_140[0x8];
4636  	u8         consumer_counter[0x18];
4637  
4638  	u8         reserved_at_160[0x8];
4639  	u8         producer_counter[0x18];
4640  
4641  	u8         reserved_at_180[0x40];
4642  
4643  	u8         dbr_addr[0x40];
4644  };
4645  
4646  union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4647  	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4648  	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4649  	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4650  	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4651  	u8         reserved_at_0[0x800];
4652  };
4653  
4654  struct mlx5_ifc_query_adapter_param_block_bits {
4655  	u8         reserved_at_0[0xc0];
4656  
4657  	u8         reserved_at_c0[0x8];
4658  	u8         ieee_vendor_id[0x18];
4659  
4660  	u8         reserved_at_e0[0x10];
4661  	u8         vsd_vendor_id[0x10];
4662  
4663  	u8         vsd[208][0x8];
4664  
4665  	u8         vsd_contd_psid[16][0x8];
4666  };
4667  
4668  enum {
4669  	MLX5_XRQC_STATE_GOOD   = 0x0,
4670  	MLX5_XRQC_STATE_ERROR  = 0x1,
4671  };
4672  
4673  enum {
4674  	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4675  	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4676  };
4677  
4678  enum {
4679  	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4680  };
4681  
4682  struct mlx5_ifc_tag_matching_topology_context_bits {
4683  	u8         log_matching_list_sz[0x4];
4684  	u8         reserved_at_4[0xc];
4685  	u8         append_next_index[0x10];
4686  
4687  	u8         sw_phase_cnt[0x10];
4688  	u8         hw_phase_cnt[0x10];
4689  
4690  	u8         reserved_at_40[0x40];
4691  };
4692  
4693  struct mlx5_ifc_xrqc_bits {
4694  	u8         state[0x4];
4695  	u8         rlkey[0x1];
4696  	u8         reserved_at_5[0xf];
4697  	u8         topology[0x4];
4698  	u8         reserved_at_18[0x4];
4699  	u8         offload[0x4];
4700  
4701  	u8         reserved_at_20[0x8];
4702  	u8         user_index[0x18];
4703  
4704  	u8         reserved_at_40[0x8];
4705  	u8         cqn[0x18];
4706  
4707  	u8         reserved_at_60[0xa0];
4708  
4709  	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4710  
4711  	u8         reserved_at_180[0x280];
4712  
4713  	struct mlx5_ifc_wq_bits wq;
4714  };
4715  
4716  union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4717  	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4718  	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4719  	u8         reserved_at_0[0x20];
4720  };
4721  
4722  union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4723  	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4724  	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4725  	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4726  	u8         reserved_at_0[0x20];
4727  };
4728  
4729  union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4730  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4731  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4732  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4733  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4734  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4735  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4736  	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4737  	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4738  	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4739  	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4740  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4741  	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4742  	u8         reserved_at_0[0x7c0];
4743  };
4744  
4745  union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4746  	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4747  	u8         reserved_at_0[0x7c0];
4748  };
4749  
4750  union mlx5_ifc_event_auto_bits {
4751  	struct mlx5_ifc_comp_event_bits comp_event;
4752  	struct mlx5_ifc_dct_events_bits dct_events;
4753  	struct mlx5_ifc_qp_events_bits qp_events;
4754  	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4755  	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4756  	struct mlx5_ifc_cq_error_bits cq_error;
4757  	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4758  	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4759  	struct mlx5_ifc_gpio_event_bits gpio_event;
4760  	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4761  	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4762  	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4763  	u8         reserved_at_0[0xe0];
4764  };
4765  
4766  struct mlx5_ifc_health_buffer_bits {
4767  	u8         reserved_at_0[0x100];
4768  
4769  	u8         assert_existptr[0x20];
4770  
4771  	u8         assert_callra[0x20];
4772  
4773  	u8         reserved_at_140[0x20];
4774  
4775  	u8         time[0x20];
4776  
4777  	u8         fw_version[0x20];
4778  
4779  	u8         hw_id[0x20];
4780  
4781  	u8         rfr[0x1];
4782  	u8         reserved_at_1c1[0x3];
4783  	u8         valid[0x1];
4784  	u8         severity[0x3];
4785  	u8         reserved_at_1c8[0x18];
4786  
4787  	u8         irisc_index[0x8];
4788  	u8         synd[0x8];
4789  	u8         ext_synd[0x10];
4790  };
4791  
4792  struct mlx5_ifc_register_loopback_control_bits {
4793  	u8         no_lb[0x1];
4794  	u8         reserved_at_1[0x7];
4795  	u8         port[0x8];
4796  	u8         reserved_at_10[0x10];
4797  
4798  	u8         reserved_at_20[0x60];
4799  };
4800  
4801  struct mlx5_ifc_vport_tc_element_bits {
4802  	u8         traffic_class[0x4];
4803  	u8         reserved_at_4[0xc];
4804  	u8         vport_number[0x10];
4805  };
4806  
4807  struct mlx5_ifc_vport_element_bits {
4808  	u8         reserved_at_0[0x10];
4809  	u8         vport_number[0x10];
4810  };
4811  
4812  enum {
4813  	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4814  	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4815  	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4816  };
4817  
4818  enum {
4819  	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4820  	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4821  	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4822  };
4823  
4824  struct mlx5_ifc_tsar_element_bits {
4825  	u8         reserved_at_0[0x8];
4826  	u8         tsar_type[0x8];
4827  	u8         reserved_at_10[0x10];
4828  };
4829  
4830  enum {
4831  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4832  	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4833  };
4834  
4835  struct mlx5_ifc_teardown_hca_out_bits {
4836  	u8         status[0x8];
4837  	u8         reserved_at_8[0x18];
4838  
4839  	u8         syndrome[0x20];
4840  
4841  	u8         reserved_at_40[0x3f];
4842  
4843  	u8         state[0x1];
4844  };
4845  
4846  enum {
4847  	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4848  	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4849  	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4850  };
4851  
4852  struct mlx5_ifc_teardown_hca_in_bits {
4853  	u8         opcode[0x10];
4854  	u8         reserved_at_10[0x10];
4855  
4856  	u8         reserved_at_20[0x10];
4857  	u8         op_mod[0x10];
4858  
4859  	u8         reserved_at_40[0x10];
4860  	u8         profile[0x10];
4861  
4862  	u8         reserved_at_60[0x20];
4863  };
4864  
4865  struct mlx5_ifc_sqerr2rts_qp_out_bits {
4866  	u8         status[0x8];
4867  	u8         reserved_at_8[0x18];
4868  
4869  	u8         syndrome[0x20];
4870  
4871  	u8         reserved_at_40[0x40];
4872  };
4873  
4874  struct mlx5_ifc_sqerr2rts_qp_in_bits {
4875  	u8         opcode[0x10];
4876  	u8         uid[0x10];
4877  
4878  	u8         reserved_at_20[0x10];
4879  	u8         op_mod[0x10];
4880  
4881  	u8         reserved_at_40[0x8];
4882  	u8         qpn[0x18];
4883  
4884  	u8         reserved_at_60[0x20];
4885  
4886  	u8         opt_param_mask[0x20];
4887  
4888  	u8         reserved_at_a0[0x20];
4889  
4890  	struct mlx5_ifc_qpc_bits qpc;
4891  
4892  	u8         reserved_at_800[0x80];
4893  };
4894  
4895  struct mlx5_ifc_sqd2rts_qp_out_bits {
4896  	u8         status[0x8];
4897  	u8         reserved_at_8[0x18];
4898  
4899  	u8         syndrome[0x20];
4900  
4901  	u8         reserved_at_40[0x40];
4902  };
4903  
4904  struct mlx5_ifc_sqd2rts_qp_in_bits {
4905  	u8         opcode[0x10];
4906  	u8         uid[0x10];
4907  
4908  	u8         reserved_at_20[0x10];
4909  	u8         op_mod[0x10];
4910  
4911  	u8         reserved_at_40[0x8];
4912  	u8         qpn[0x18];
4913  
4914  	u8         reserved_at_60[0x20];
4915  
4916  	u8         opt_param_mask[0x20];
4917  
4918  	u8         reserved_at_a0[0x20];
4919  
4920  	struct mlx5_ifc_qpc_bits qpc;
4921  
4922  	u8         reserved_at_800[0x80];
4923  };
4924  
4925  struct mlx5_ifc_set_roce_address_out_bits {
4926  	u8         status[0x8];
4927  	u8         reserved_at_8[0x18];
4928  
4929  	u8         syndrome[0x20];
4930  
4931  	u8         reserved_at_40[0x40];
4932  };
4933  
4934  struct mlx5_ifc_set_roce_address_in_bits {
4935  	u8         opcode[0x10];
4936  	u8         reserved_at_10[0x10];
4937  
4938  	u8         reserved_at_20[0x10];
4939  	u8         op_mod[0x10];
4940  
4941  	u8         roce_address_index[0x10];
4942  	u8         reserved_at_50[0xc];
4943  	u8	   vhca_port_num[0x4];
4944  
4945  	u8         reserved_at_60[0x20];
4946  
4947  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4948  };
4949  
4950  struct mlx5_ifc_set_mad_demux_out_bits {
4951  	u8         status[0x8];
4952  	u8         reserved_at_8[0x18];
4953  
4954  	u8         syndrome[0x20];
4955  
4956  	u8         reserved_at_40[0x40];
4957  };
4958  
4959  enum {
4960  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4961  	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4962  };
4963  
4964  struct mlx5_ifc_set_mad_demux_in_bits {
4965  	u8         opcode[0x10];
4966  	u8         reserved_at_10[0x10];
4967  
4968  	u8         reserved_at_20[0x10];
4969  	u8         op_mod[0x10];
4970  
4971  	u8         reserved_at_40[0x20];
4972  
4973  	u8         reserved_at_60[0x6];
4974  	u8         demux_mode[0x2];
4975  	u8         reserved_at_68[0x18];
4976  };
4977  
4978  struct mlx5_ifc_set_l2_table_entry_out_bits {
4979  	u8         status[0x8];
4980  	u8         reserved_at_8[0x18];
4981  
4982  	u8         syndrome[0x20];
4983  
4984  	u8         reserved_at_40[0x40];
4985  };
4986  
4987  struct mlx5_ifc_set_l2_table_entry_in_bits {
4988  	u8         opcode[0x10];
4989  	u8         reserved_at_10[0x10];
4990  
4991  	u8         reserved_at_20[0x10];
4992  	u8         op_mod[0x10];
4993  
4994  	u8         reserved_at_40[0x60];
4995  
4996  	u8         reserved_at_a0[0x8];
4997  	u8         table_index[0x18];
4998  
4999  	u8         reserved_at_c0[0x20];
5000  
5001  	u8         reserved_at_e0[0x10];
5002  	u8         silent_mode_valid[0x1];
5003  	u8         silent_mode[0x1];
5004  	u8         reserved_at_f2[0x1];
5005  	u8         vlan_valid[0x1];
5006  	u8         vlan[0xc];
5007  
5008  	struct mlx5_ifc_mac_address_layout_bits mac_address;
5009  
5010  	u8         reserved_at_140[0xc0];
5011  };
5012  
5013  struct mlx5_ifc_set_issi_out_bits {
5014  	u8         status[0x8];
5015  	u8         reserved_at_8[0x18];
5016  
5017  	u8         syndrome[0x20];
5018  
5019  	u8         reserved_at_40[0x40];
5020  };
5021  
5022  struct mlx5_ifc_set_issi_in_bits {
5023  	u8         opcode[0x10];
5024  	u8         reserved_at_10[0x10];
5025  
5026  	u8         reserved_at_20[0x10];
5027  	u8         op_mod[0x10];
5028  
5029  	u8         reserved_at_40[0x10];
5030  	u8         current_issi[0x10];
5031  
5032  	u8         reserved_at_60[0x20];
5033  };
5034  
5035  struct mlx5_ifc_set_hca_cap_out_bits {
5036  	u8         status[0x8];
5037  	u8         reserved_at_8[0x18];
5038  
5039  	u8         syndrome[0x20];
5040  
5041  	u8         reserved_at_40[0x40];
5042  };
5043  
5044  struct mlx5_ifc_set_hca_cap_in_bits {
5045  	u8         opcode[0x10];
5046  	u8         reserved_at_10[0x10];
5047  
5048  	u8         reserved_at_20[0x10];
5049  	u8         op_mod[0x10];
5050  
5051  	u8         other_function[0x1];
5052  	u8         ec_vf_function[0x1];
5053  	u8         reserved_at_42[0xe];
5054  	u8         function_id[0x10];
5055  
5056  	u8         reserved_at_60[0x20];
5057  
5058  	union mlx5_ifc_hca_cap_union_bits capability;
5059  };
5060  
5061  enum {
5062  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5063  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5064  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5065  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5066  	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5067  };
5068  
5069  struct mlx5_ifc_set_fte_out_bits {
5070  	u8         status[0x8];
5071  	u8         reserved_at_8[0x18];
5072  
5073  	u8         syndrome[0x20];
5074  
5075  	u8         reserved_at_40[0x40];
5076  };
5077  
5078  struct mlx5_ifc_set_fte_in_bits {
5079  	u8         opcode[0x10];
5080  	u8         reserved_at_10[0x10];
5081  
5082  	u8         reserved_at_20[0x10];
5083  	u8         op_mod[0x10];
5084  
5085  	u8         other_vport[0x1];
5086  	u8         reserved_at_41[0xf];
5087  	u8         vport_number[0x10];
5088  
5089  	u8         reserved_at_60[0x20];
5090  
5091  	u8         table_type[0x8];
5092  	u8         reserved_at_88[0x18];
5093  
5094  	u8         reserved_at_a0[0x8];
5095  	u8         table_id[0x18];
5096  
5097  	u8         ignore_flow_level[0x1];
5098  	u8         reserved_at_c1[0x17];
5099  	u8         modify_enable_mask[0x8];
5100  
5101  	u8         reserved_at_e0[0x20];
5102  
5103  	u8         flow_index[0x20];
5104  
5105  	u8         reserved_at_120[0xe0];
5106  
5107  	struct mlx5_ifc_flow_context_bits flow_context;
5108  };
5109  
5110  struct mlx5_ifc_dest_format_bits {
5111  	u8         destination_type[0x8];
5112  	u8         destination_id[0x18];
5113  
5114  	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5115  	u8         packet_reformat[0x1];
5116  	u8         reserved_at_22[0xe];
5117  	u8         destination_eswitch_owner_vhca_id[0x10];
5118  };
5119  
5120  struct mlx5_ifc_rts2rts_qp_out_bits {
5121  	u8         status[0x8];
5122  	u8         reserved_at_8[0x18];
5123  
5124  	u8         syndrome[0x20];
5125  
5126  	u8         reserved_at_40[0x20];
5127  	u8         ece[0x20];
5128  };
5129  
5130  struct mlx5_ifc_rts2rts_qp_in_bits {
5131  	u8         opcode[0x10];
5132  	u8         uid[0x10];
5133  
5134  	u8         reserved_at_20[0x10];
5135  	u8         op_mod[0x10];
5136  
5137  	u8         reserved_at_40[0x8];
5138  	u8         qpn[0x18];
5139  
5140  	u8         reserved_at_60[0x20];
5141  
5142  	u8         opt_param_mask[0x20];
5143  
5144  	u8         ece[0x20];
5145  
5146  	struct mlx5_ifc_qpc_bits qpc;
5147  
5148  	u8         reserved_at_800[0x80];
5149  };
5150  
5151  struct mlx5_ifc_rtr2rts_qp_out_bits {
5152  	u8         status[0x8];
5153  	u8         reserved_at_8[0x18];
5154  
5155  	u8         syndrome[0x20];
5156  
5157  	u8         reserved_at_40[0x20];
5158  	u8         ece[0x20];
5159  };
5160  
5161  struct mlx5_ifc_rtr2rts_qp_in_bits {
5162  	u8         opcode[0x10];
5163  	u8         uid[0x10];
5164  
5165  	u8         reserved_at_20[0x10];
5166  	u8         op_mod[0x10];
5167  
5168  	u8         reserved_at_40[0x8];
5169  	u8         qpn[0x18];
5170  
5171  	u8         reserved_at_60[0x20];
5172  
5173  	u8         opt_param_mask[0x20];
5174  
5175  	u8         ece[0x20];
5176  
5177  	struct mlx5_ifc_qpc_bits qpc;
5178  
5179  	u8         reserved_at_800[0x80];
5180  };
5181  
5182  struct mlx5_ifc_rst2init_qp_out_bits {
5183  	u8         status[0x8];
5184  	u8         reserved_at_8[0x18];
5185  
5186  	u8         syndrome[0x20];
5187  
5188  	u8         reserved_at_40[0x20];
5189  	u8         ece[0x20];
5190  };
5191  
5192  struct mlx5_ifc_rst2init_qp_in_bits {
5193  	u8         opcode[0x10];
5194  	u8         uid[0x10];
5195  
5196  	u8         reserved_at_20[0x10];
5197  	u8         op_mod[0x10];
5198  
5199  	u8         reserved_at_40[0x8];
5200  	u8         qpn[0x18];
5201  
5202  	u8         reserved_at_60[0x20];
5203  
5204  	u8         opt_param_mask[0x20];
5205  
5206  	u8         ece[0x20];
5207  
5208  	struct mlx5_ifc_qpc_bits qpc;
5209  
5210  	u8         reserved_at_800[0x80];
5211  };
5212  
5213  struct mlx5_ifc_query_xrq_out_bits {
5214  	u8         status[0x8];
5215  	u8         reserved_at_8[0x18];
5216  
5217  	u8         syndrome[0x20];
5218  
5219  	u8         reserved_at_40[0x40];
5220  
5221  	struct mlx5_ifc_xrqc_bits xrq_context;
5222  };
5223  
5224  struct mlx5_ifc_query_xrq_in_bits {
5225  	u8         opcode[0x10];
5226  	u8         reserved_at_10[0x10];
5227  
5228  	u8         reserved_at_20[0x10];
5229  	u8         op_mod[0x10];
5230  
5231  	u8         reserved_at_40[0x8];
5232  	u8         xrqn[0x18];
5233  
5234  	u8         reserved_at_60[0x20];
5235  };
5236  
5237  struct mlx5_ifc_query_xrc_srq_out_bits {
5238  	u8         status[0x8];
5239  	u8         reserved_at_8[0x18];
5240  
5241  	u8         syndrome[0x20];
5242  
5243  	u8         reserved_at_40[0x40];
5244  
5245  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5246  
5247  	u8         reserved_at_280[0x600];
5248  
5249  	u8         pas[][0x40];
5250  };
5251  
5252  struct mlx5_ifc_query_xrc_srq_in_bits {
5253  	u8         opcode[0x10];
5254  	u8         reserved_at_10[0x10];
5255  
5256  	u8         reserved_at_20[0x10];
5257  	u8         op_mod[0x10];
5258  
5259  	u8         reserved_at_40[0x8];
5260  	u8         xrc_srqn[0x18];
5261  
5262  	u8         reserved_at_60[0x20];
5263  };
5264  
5265  enum {
5266  	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5267  	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5268  };
5269  
5270  struct mlx5_ifc_query_vport_state_out_bits {
5271  	u8         status[0x8];
5272  	u8         reserved_at_8[0x18];
5273  
5274  	u8         syndrome[0x20];
5275  
5276  	u8         reserved_at_40[0x20];
5277  
5278  	u8         reserved_at_60[0x18];
5279  	u8         admin_state[0x4];
5280  	u8         state[0x4];
5281  };
5282  
5283  struct mlx5_ifc_array1024_auto_bits {
5284  	u8         array1024_auto[32][0x20];
5285  };
5286  
5287  struct mlx5_ifc_query_vuid_in_bits {
5288  	u8         opcode[0x10];
5289  	u8         uid[0x10];
5290  
5291  	u8         reserved_at_20[0x40];
5292  
5293  	u8         query_vfs_vuid[0x1];
5294  	u8         data_direct[0x1];
5295  	u8         reserved_at_62[0xe];
5296  	u8         vhca_id[0x10];
5297  };
5298  
5299  struct mlx5_ifc_query_vuid_out_bits {
5300  	u8        status[0x8];
5301  	u8        reserved_at_8[0x18];
5302  
5303  	u8        syndrome[0x20];
5304  
5305  	u8        reserved_at_40[0x1a0];
5306  
5307  	u8        reserved_at_1e0[0x10];
5308  	u8        num_of_entries[0x10];
5309  
5310  	struct mlx5_ifc_array1024_auto_bits vuid[];
5311  };
5312  
5313  enum {
5314  	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5315  	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5316  	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5317  };
5318  
5319  struct mlx5_ifc_arm_monitor_counter_in_bits {
5320  	u8         opcode[0x10];
5321  	u8         uid[0x10];
5322  
5323  	u8         reserved_at_20[0x10];
5324  	u8         op_mod[0x10];
5325  
5326  	u8         reserved_at_40[0x20];
5327  
5328  	u8         reserved_at_60[0x20];
5329  };
5330  
5331  struct mlx5_ifc_arm_monitor_counter_out_bits {
5332  	u8         status[0x8];
5333  	u8         reserved_at_8[0x18];
5334  
5335  	u8         syndrome[0x20];
5336  
5337  	u8         reserved_at_40[0x40];
5338  };
5339  
5340  enum {
5341  	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5342  	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5343  };
5344  
5345  enum mlx5_monitor_counter_ppcnt {
5346  	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5347  	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5348  	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5349  	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5350  	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5351  	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5352  };
5353  
5354  enum {
5355  	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5356  };
5357  
5358  struct mlx5_ifc_monitor_counter_output_bits {
5359  	u8         reserved_at_0[0x4];
5360  	u8         type[0x4];
5361  	u8         reserved_at_8[0x8];
5362  	u8         counter[0x10];
5363  
5364  	u8         counter_group_id[0x20];
5365  };
5366  
5367  #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5368  #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5369  #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5370  					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5371  
5372  struct mlx5_ifc_set_monitor_counter_in_bits {
5373  	u8         opcode[0x10];
5374  	u8         uid[0x10];
5375  
5376  	u8         reserved_at_20[0x10];
5377  	u8         op_mod[0x10];
5378  
5379  	u8         reserved_at_40[0x10];
5380  	u8         num_of_counters[0x10];
5381  
5382  	u8         reserved_at_60[0x20];
5383  
5384  	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5385  };
5386  
5387  struct mlx5_ifc_set_monitor_counter_out_bits {
5388  	u8         status[0x8];
5389  	u8         reserved_at_8[0x18];
5390  
5391  	u8         syndrome[0x20];
5392  
5393  	u8         reserved_at_40[0x40];
5394  };
5395  
5396  struct mlx5_ifc_query_vport_state_in_bits {
5397  	u8         opcode[0x10];
5398  	u8         reserved_at_10[0x10];
5399  
5400  	u8         reserved_at_20[0x10];
5401  	u8         op_mod[0x10];
5402  
5403  	u8         other_vport[0x1];
5404  	u8         reserved_at_41[0xf];
5405  	u8         vport_number[0x10];
5406  
5407  	u8         reserved_at_60[0x20];
5408  };
5409  
5410  struct mlx5_ifc_query_vnic_env_out_bits {
5411  	u8         status[0x8];
5412  	u8         reserved_at_8[0x18];
5413  
5414  	u8         syndrome[0x20];
5415  
5416  	u8         reserved_at_40[0x40];
5417  
5418  	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5419  };
5420  
5421  enum {
5422  	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5423  };
5424  
5425  struct mlx5_ifc_query_vnic_env_in_bits {
5426  	u8         opcode[0x10];
5427  	u8         reserved_at_10[0x10];
5428  
5429  	u8         reserved_at_20[0x10];
5430  	u8         op_mod[0x10];
5431  
5432  	u8         other_vport[0x1];
5433  	u8         reserved_at_41[0xf];
5434  	u8         vport_number[0x10];
5435  
5436  	u8         reserved_at_60[0x20];
5437  };
5438  
5439  struct mlx5_ifc_query_vport_counter_out_bits {
5440  	u8         status[0x8];
5441  	u8         reserved_at_8[0x18];
5442  
5443  	u8         syndrome[0x20];
5444  
5445  	u8         reserved_at_40[0x40];
5446  
5447  	struct mlx5_ifc_traffic_counter_bits received_errors;
5448  
5449  	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5450  
5451  	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5452  
5453  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5454  
5455  	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5456  
5457  	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5458  
5459  	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5460  
5461  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5462  
5463  	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5464  
5465  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5466  
5467  	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5468  
5469  	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5470  
5471  	struct mlx5_ifc_traffic_counter_bits local_loopback;
5472  
5473  	u8         reserved_at_700[0x980];
5474  };
5475  
5476  enum {
5477  	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5478  };
5479  
5480  struct mlx5_ifc_query_vport_counter_in_bits {
5481  	u8         opcode[0x10];
5482  	u8         reserved_at_10[0x10];
5483  
5484  	u8         reserved_at_20[0x10];
5485  	u8         op_mod[0x10];
5486  
5487  	u8         other_vport[0x1];
5488  	u8         reserved_at_41[0xb];
5489  	u8	   port_num[0x4];
5490  	u8         vport_number[0x10];
5491  
5492  	u8         reserved_at_60[0x60];
5493  
5494  	u8         clear[0x1];
5495  	u8         reserved_at_c1[0x1f];
5496  
5497  	u8         reserved_at_e0[0x20];
5498  };
5499  
5500  struct mlx5_ifc_query_tis_out_bits {
5501  	u8         status[0x8];
5502  	u8         reserved_at_8[0x18];
5503  
5504  	u8         syndrome[0x20];
5505  
5506  	u8         reserved_at_40[0x40];
5507  
5508  	struct mlx5_ifc_tisc_bits tis_context;
5509  };
5510  
5511  struct mlx5_ifc_query_tis_in_bits {
5512  	u8         opcode[0x10];
5513  	u8         reserved_at_10[0x10];
5514  
5515  	u8         reserved_at_20[0x10];
5516  	u8         op_mod[0x10];
5517  
5518  	u8         reserved_at_40[0x8];
5519  	u8         tisn[0x18];
5520  
5521  	u8         reserved_at_60[0x20];
5522  };
5523  
5524  struct mlx5_ifc_query_tir_out_bits {
5525  	u8         status[0x8];
5526  	u8         reserved_at_8[0x18];
5527  
5528  	u8         syndrome[0x20];
5529  
5530  	u8         reserved_at_40[0xc0];
5531  
5532  	struct mlx5_ifc_tirc_bits tir_context;
5533  };
5534  
5535  struct mlx5_ifc_query_tir_in_bits {
5536  	u8         opcode[0x10];
5537  	u8         reserved_at_10[0x10];
5538  
5539  	u8         reserved_at_20[0x10];
5540  	u8         op_mod[0x10];
5541  
5542  	u8         reserved_at_40[0x8];
5543  	u8         tirn[0x18];
5544  
5545  	u8         reserved_at_60[0x20];
5546  };
5547  
5548  struct mlx5_ifc_query_srq_out_bits {
5549  	u8         status[0x8];
5550  	u8         reserved_at_8[0x18];
5551  
5552  	u8         syndrome[0x20];
5553  
5554  	u8         reserved_at_40[0x40];
5555  
5556  	struct mlx5_ifc_srqc_bits srq_context_entry;
5557  
5558  	u8         reserved_at_280[0x600];
5559  
5560  	u8         pas[][0x40];
5561  };
5562  
5563  struct mlx5_ifc_query_srq_in_bits {
5564  	u8         opcode[0x10];
5565  	u8         reserved_at_10[0x10];
5566  
5567  	u8         reserved_at_20[0x10];
5568  	u8         op_mod[0x10];
5569  
5570  	u8         reserved_at_40[0x8];
5571  	u8         srqn[0x18];
5572  
5573  	u8         reserved_at_60[0x20];
5574  };
5575  
5576  struct mlx5_ifc_query_sq_out_bits {
5577  	u8         status[0x8];
5578  	u8         reserved_at_8[0x18];
5579  
5580  	u8         syndrome[0x20];
5581  
5582  	u8         reserved_at_40[0xc0];
5583  
5584  	struct mlx5_ifc_sqc_bits sq_context;
5585  };
5586  
5587  struct mlx5_ifc_query_sq_in_bits {
5588  	u8         opcode[0x10];
5589  	u8         reserved_at_10[0x10];
5590  
5591  	u8         reserved_at_20[0x10];
5592  	u8         op_mod[0x10];
5593  
5594  	u8         reserved_at_40[0x8];
5595  	u8         sqn[0x18];
5596  
5597  	u8         reserved_at_60[0x20];
5598  };
5599  
5600  struct mlx5_ifc_query_special_contexts_out_bits {
5601  	u8         status[0x8];
5602  	u8         reserved_at_8[0x18];
5603  
5604  	u8         syndrome[0x20];
5605  
5606  	u8         dump_fill_mkey[0x20];
5607  
5608  	u8         resd_lkey[0x20];
5609  
5610  	u8         null_mkey[0x20];
5611  
5612  	u8	   terminate_scatter_list_mkey[0x20];
5613  
5614  	u8	   repeated_mkey[0x20];
5615  
5616  	u8         reserved_at_a0[0x20];
5617  };
5618  
5619  struct mlx5_ifc_query_special_contexts_in_bits {
5620  	u8         opcode[0x10];
5621  	u8         reserved_at_10[0x10];
5622  
5623  	u8         reserved_at_20[0x10];
5624  	u8         op_mod[0x10];
5625  
5626  	u8         reserved_at_40[0x40];
5627  };
5628  
5629  struct mlx5_ifc_query_scheduling_element_out_bits {
5630  	u8         opcode[0x10];
5631  	u8         reserved_at_10[0x10];
5632  
5633  	u8         reserved_at_20[0x10];
5634  	u8         op_mod[0x10];
5635  
5636  	u8         reserved_at_40[0xc0];
5637  
5638  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5639  
5640  	u8         reserved_at_300[0x100];
5641  };
5642  
5643  enum {
5644  	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5645  	SCHEDULING_HIERARCHY_NIC = 0x3,
5646  };
5647  
5648  struct mlx5_ifc_query_scheduling_element_in_bits {
5649  	u8         opcode[0x10];
5650  	u8         reserved_at_10[0x10];
5651  
5652  	u8         reserved_at_20[0x10];
5653  	u8         op_mod[0x10];
5654  
5655  	u8         scheduling_hierarchy[0x8];
5656  	u8         reserved_at_48[0x18];
5657  
5658  	u8         scheduling_element_id[0x20];
5659  
5660  	u8         reserved_at_80[0x180];
5661  };
5662  
5663  struct mlx5_ifc_query_rqt_out_bits {
5664  	u8         status[0x8];
5665  	u8         reserved_at_8[0x18];
5666  
5667  	u8         syndrome[0x20];
5668  
5669  	u8         reserved_at_40[0xc0];
5670  
5671  	struct mlx5_ifc_rqtc_bits rqt_context;
5672  };
5673  
5674  struct mlx5_ifc_query_rqt_in_bits {
5675  	u8         opcode[0x10];
5676  	u8         reserved_at_10[0x10];
5677  
5678  	u8         reserved_at_20[0x10];
5679  	u8         op_mod[0x10];
5680  
5681  	u8         reserved_at_40[0x8];
5682  	u8         rqtn[0x18];
5683  
5684  	u8         reserved_at_60[0x20];
5685  };
5686  
5687  struct mlx5_ifc_query_rq_out_bits {
5688  	u8         status[0x8];
5689  	u8         reserved_at_8[0x18];
5690  
5691  	u8         syndrome[0x20];
5692  
5693  	u8         reserved_at_40[0xc0];
5694  
5695  	struct mlx5_ifc_rqc_bits rq_context;
5696  };
5697  
5698  struct mlx5_ifc_query_rq_in_bits {
5699  	u8         opcode[0x10];
5700  	u8         reserved_at_10[0x10];
5701  
5702  	u8         reserved_at_20[0x10];
5703  	u8         op_mod[0x10];
5704  
5705  	u8         reserved_at_40[0x8];
5706  	u8         rqn[0x18];
5707  
5708  	u8         reserved_at_60[0x20];
5709  };
5710  
5711  struct mlx5_ifc_query_roce_address_out_bits {
5712  	u8         status[0x8];
5713  	u8         reserved_at_8[0x18];
5714  
5715  	u8         syndrome[0x20];
5716  
5717  	u8         reserved_at_40[0x40];
5718  
5719  	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5720  };
5721  
5722  struct mlx5_ifc_query_roce_address_in_bits {
5723  	u8         opcode[0x10];
5724  	u8         reserved_at_10[0x10];
5725  
5726  	u8         reserved_at_20[0x10];
5727  	u8         op_mod[0x10];
5728  
5729  	u8         roce_address_index[0x10];
5730  	u8         reserved_at_50[0xc];
5731  	u8	   vhca_port_num[0x4];
5732  
5733  	u8         reserved_at_60[0x20];
5734  };
5735  
5736  struct mlx5_ifc_query_rmp_out_bits {
5737  	u8         status[0x8];
5738  	u8         reserved_at_8[0x18];
5739  
5740  	u8         syndrome[0x20];
5741  
5742  	u8         reserved_at_40[0xc0];
5743  
5744  	struct mlx5_ifc_rmpc_bits rmp_context;
5745  };
5746  
5747  struct mlx5_ifc_query_rmp_in_bits {
5748  	u8         opcode[0x10];
5749  	u8         reserved_at_10[0x10];
5750  
5751  	u8         reserved_at_20[0x10];
5752  	u8         op_mod[0x10];
5753  
5754  	u8         reserved_at_40[0x8];
5755  	u8         rmpn[0x18];
5756  
5757  	u8         reserved_at_60[0x20];
5758  };
5759  
5760  struct mlx5_ifc_cqe_error_syndrome_bits {
5761  	u8         hw_error_syndrome[0x8];
5762  	u8         hw_syndrome_type[0x4];
5763  	u8         reserved_at_c[0x4];
5764  	u8         vendor_error_syndrome[0x8];
5765  	u8         syndrome[0x8];
5766  };
5767  
5768  struct mlx5_ifc_qp_context_extension_bits {
5769  	u8         reserved_at_0[0x60];
5770  
5771  	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5772  
5773  	u8         reserved_at_80[0x580];
5774  };
5775  
5776  struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5777  	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5778  
5779  	u8         pas[0][0x40];
5780  };
5781  
5782  struct mlx5_ifc_qp_pas_list_in_bits {
5783  	struct mlx5_ifc_cmd_pas_bits pas[0];
5784  };
5785  
5786  union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5787  	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5788  	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5789  };
5790  
5791  struct mlx5_ifc_query_qp_out_bits {
5792  	u8         status[0x8];
5793  	u8         reserved_at_8[0x18];
5794  
5795  	u8         syndrome[0x20];
5796  
5797  	u8         reserved_at_40[0x40];
5798  
5799  	u8         opt_param_mask[0x20];
5800  
5801  	u8         ece[0x20];
5802  
5803  	struct mlx5_ifc_qpc_bits qpc;
5804  
5805  	u8         reserved_at_800[0x80];
5806  
5807  	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5808  };
5809  
5810  struct mlx5_ifc_query_qp_in_bits {
5811  	u8         opcode[0x10];
5812  	u8         reserved_at_10[0x10];
5813  
5814  	u8         reserved_at_20[0x10];
5815  	u8         op_mod[0x10];
5816  
5817  	u8         qpc_ext[0x1];
5818  	u8         reserved_at_41[0x7];
5819  	u8         qpn[0x18];
5820  
5821  	u8         reserved_at_60[0x20];
5822  };
5823  
5824  struct mlx5_ifc_query_q_counter_out_bits {
5825  	u8         status[0x8];
5826  	u8         reserved_at_8[0x18];
5827  
5828  	u8         syndrome[0x20];
5829  
5830  	u8         reserved_at_40[0x40];
5831  
5832  	u8         rx_write_requests[0x20];
5833  
5834  	u8         reserved_at_a0[0x20];
5835  
5836  	u8         rx_read_requests[0x20];
5837  
5838  	u8         reserved_at_e0[0x20];
5839  
5840  	u8         rx_atomic_requests[0x20];
5841  
5842  	u8         reserved_at_120[0x20];
5843  
5844  	u8         rx_dct_connect[0x20];
5845  
5846  	u8         reserved_at_160[0x20];
5847  
5848  	u8         out_of_buffer[0x20];
5849  
5850  	u8         reserved_at_1a0[0x20];
5851  
5852  	u8         out_of_sequence[0x20];
5853  
5854  	u8         reserved_at_1e0[0x20];
5855  
5856  	u8         duplicate_request[0x20];
5857  
5858  	u8         reserved_at_220[0x20];
5859  
5860  	u8         rnr_nak_retry_err[0x20];
5861  
5862  	u8         reserved_at_260[0x20];
5863  
5864  	u8         packet_seq_err[0x20];
5865  
5866  	u8         reserved_at_2a0[0x20];
5867  
5868  	u8         implied_nak_seq_err[0x20];
5869  
5870  	u8         reserved_at_2e0[0x20];
5871  
5872  	u8         local_ack_timeout_err[0x20];
5873  
5874  	u8         reserved_at_320[0x60];
5875  
5876  	u8         req_rnr_retries_exceeded[0x20];
5877  
5878  	u8         reserved_at_3a0[0x20];
5879  
5880  	u8         resp_local_length_error[0x20];
5881  
5882  	u8         req_local_length_error[0x20];
5883  
5884  	u8         resp_local_qp_error[0x20];
5885  
5886  	u8         local_operation_error[0x20];
5887  
5888  	u8         resp_local_protection[0x20];
5889  
5890  	u8         req_local_protection[0x20];
5891  
5892  	u8         resp_cqe_error[0x20];
5893  
5894  	u8         req_cqe_error[0x20];
5895  
5896  	u8         req_mw_binding[0x20];
5897  
5898  	u8         req_bad_response[0x20];
5899  
5900  	u8         req_remote_invalid_request[0x20];
5901  
5902  	u8         resp_remote_invalid_request[0x20];
5903  
5904  	u8         req_remote_access_errors[0x20];
5905  
5906  	u8	   resp_remote_access_errors[0x20];
5907  
5908  	u8         req_remote_operation_errors[0x20];
5909  
5910  	u8         req_transport_retries_exceeded[0x20];
5911  
5912  	u8         cq_overflow[0x20];
5913  
5914  	u8         resp_cqe_flush_error[0x20];
5915  
5916  	u8         req_cqe_flush_error[0x20];
5917  
5918  	u8         reserved_at_620[0x20];
5919  
5920  	u8         roce_adp_retrans[0x20];
5921  
5922  	u8         roce_adp_retrans_to[0x20];
5923  
5924  	u8         roce_slow_restart[0x20];
5925  
5926  	u8         roce_slow_restart_cnps[0x20];
5927  
5928  	u8         roce_slow_restart_trans[0x20];
5929  
5930  	u8         reserved_at_6e0[0x120];
5931  };
5932  
5933  struct mlx5_ifc_query_q_counter_in_bits {
5934  	u8         opcode[0x10];
5935  	u8         reserved_at_10[0x10];
5936  
5937  	u8         reserved_at_20[0x10];
5938  	u8         op_mod[0x10];
5939  
5940  	u8         other_vport[0x1];
5941  	u8         reserved_at_41[0xf];
5942  	u8         vport_number[0x10];
5943  
5944  	u8         reserved_at_60[0x60];
5945  
5946  	u8         clear[0x1];
5947  	u8         aggregate[0x1];
5948  	u8         reserved_at_c2[0x1e];
5949  
5950  	u8         reserved_at_e0[0x18];
5951  	u8         counter_set_id[0x8];
5952  };
5953  
5954  struct mlx5_ifc_query_pages_out_bits {
5955  	u8         status[0x8];
5956  	u8         reserved_at_8[0x18];
5957  
5958  	u8         syndrome[0x20];
5959  
5960  	u8         embedded_cpu_function[0x1];
5961  	u8         reserved_at_41[0xf];
5962  	u8         function_id[0x10];
5963  
5964  	u8         num_pages[0x20];
5965  };
5966  
5967  enum {
5968  	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5969  	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5970  	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5971  };
5972  
5973  struct mlx5_ifc_query_pages_in_bits {
5974  	u8         opcode[0x10];
5975  	u8         reserved_at_10[0x10];
5976  
5977  	u8         reserved_at_20[0x10];
5978  	u8         op_mod[0x10];
5979  
5980  	u8         embedded_cpu_function[0x1];
5981  	u8         reserved_at_41[0xf];
5982  	u8         function_id[0x10];
5983  
5984  	u8         reserved_at_60[0x20];
5985  };
5986  
5987  struct mlx5_ifc_query_nic_vport_context_out_bits {
5988  	u8         status[0x8];
5989  	u8         reserved_at_8[0x18];
5990  
5991  	u8         syndrome[0x20];
5992  
5993  	u8         reserved_at_40[0x40];
5994  
5995  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5996  };
5997  
5998  struct mlx5_ifc_query_nic_vport_context_in_bits {
5999  	u8         opcode[0x10];
6000  	u8         reserved_at_10[0x10];
6001  
6002  	u8         reserved_at_20[0x10];
6003  	u8         op_mod[0x10];
6004  
6005  	u8         other_vport[0x1];
6006  	u8         reserved_at_41[0xf];
6007  	u8         vport_number[0x10];
6008  
6009  	u8         reserved_at_60[0x5];
6010  	u8         allowed_list_type[0x3];
6011  	u8         reserved_at_68[0x18];
6012  };
6013  
6014  struct mlx5_ifc_query_mkey_out_bits {
6015  	u8         status[0x8];
6016  	u8         reserved_at_8[0x18];
6017  
6018  	u8         syndrome[0x20];
6019  
6020  	u8         reserved_at_40[0x40];
6021  
6022  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6023  
6024  	u8         reserved_at_280[0x600];
6025  
6026  	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6027  
6028  	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6029  };
6030  
6031  struct mlx5_ifc_query_mkey_in_bits {
6032  	u8         opcode[0x10];
6033  	u8         reserved_at_10[0x10];
6034  
6035  	u8         reserved_at_20[0x10];
6036  	u8         op_mod[0x10];
6037  
6038  	u8         reserved_at_40[0x8];
6039  	u8         mkey_index[0x18];
6040  
6041  	u8         pg_access[0x1];
6042  	u8         reserved_at_61[0x1f];
6043  };
6044  
6045  struct mlx5_ifc_query_mad_demux_out_bits {
6046  	u8         status[0x8];
6047  	u8         reserved_at_8[0x18];
6048  
6049  	u8         syndrome[0x20];
6050  
6051  	u8         reserved_at_40[0x40];
6052  
6053  	u8         mad_dumux_parameters_block[0x20];
6054  };
6055  
6056  struct mlx5_ifc_query_mad_demux_in_bits {
6057  	u8         opcode[0x10];
6058  	u8         reserved_at_10[0x10];
6059  
6060  	u8         reserved_at_20[0x10];
6061  	u8         op_mod[0x10];
6062  
6063  	u8         reserved_at_40[0x40];
6064  };
6065  
6066  struct mlx5_ifc_query_l2_table_entry_out_bits {
6067  	u8         status[0x8];
6068  	u8         reserved_at_8[0x18];
6069  
6070  	u8         syndrome[0x20];
6071  
6072  	u8         reserved_at_40[0xa0];
6073  
6074  	u8         reserved_at_e0[0x13];
6075  	u8         vlan_valid[0x1];
6076  	u8         vlan[0xc];
6077  
6078  	struct mlx5_ifc_mac_address_layout_bits mac_address;
6079  
6080  	u8         reserved_at_140[0xc0];
6081  };
6082  
6083  struct mlx5_ifc_query_l2_table_entry_in_bits {
6084  	u8         opcode[0x10];
6085  	u8         reserved_at_10[0x10];
6086  
6087  	u8         reserved_at_20[0x10];
6088  	u8         op_mod[0x10];
6089  
6090  	u8         reserved_at_40[0x60];
6091  
6092  	u8         reserved_at_a0[0x8];
6093  	u8         table_index[0x18];
6094  
6095  	u8         reserved_at_c0[0x140];
6096  };
6097  
6098  struct mlx5_ifc_query_issi_out_bits {
6099  	u8         status[0x8];
6100  	u8         reserved_at_8[0x18];
6101  
6102  	u8         syndrome[0x20];
6103  
6104  	u8         reserved_at_40[0x10];
6105  	u8         current_issi[0x10];
6106  
6107  	u8         reserved_at_60[0xa0];
6108  
6109  	u8         reserved_at_100[76][0x8];
6110  	u8         supported_issi_dw0[0x20];
6111  };
6112  
6113  struct mlx5_ifc_query_issi_in_bits {
6114  	u8         opcode[0x10];
6115  	u8         reserved_at_10[0x10];
6116  
6117  	u8         reserved_at_20[0x10];
6118  	u8         op_mod[0x10];
6119  
6120  	u8         reserved_at_40[0x40];
6121  };
6122  
6123  struct mlx5_ifc_set_driver_version_out_bits {
6124  	u8         status[0x8];
6125  	u8         reserved_0[0x18];
6126  
6127  	u8         syndrome[0x20];
6128  	u8         reserved_1[0x40];
6129  };
6130  
6131  struct mlx5_ifc_set_driver_version_in_bits {
6132  	u8         opcode[0x10];
6133  	u8         reserved_0[0x10];
6134  
6135  	u8         reserved_1[0x10];
6136  	u8         op_mod[0x10];
6137  
6138  	u8         reserved_2[0x40];
6139  	u8         driver_version[64][0x8];
6140  };
6141  
6142  struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6143  	u8         status[0x8];
6144  	u8         reserved_at_8[0x18];
6145  
6146  	u8         syndrome[0x20];
6147  
6148  	u8         reserved_at_40[0x40];
6149  
6150  	struct mlx5_ifc_pkey_bits pkey[];
6151  };
6152  
6153  struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6154  	u8         opcode[0x10];
6155  	u8         reserved_at_10[0x10];
6156  
6157  	u8         reserved_at_20[0x10];
6158  	u8         op_mod[0x10];
6159  
6160  	u8         other_vport[0x1];
6161  	u8         reserved_at_41[0xb];
6162  	u8         port_num[0x4];
6163  	u8         vport_number[0x10];
6164  
6165  	u8         reserved_at_60[0x10];
6166  	u8         pkey_index[0x10];
6167  };
6168  
6169  enum {
6170  	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6171  	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6172  	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6173  };
6174  
6175  struct mlx5_ifc_query_hca_vport_gid_out_bits {
6176  	u8         status[0x8];
6177  	u8         reserved_at_8[0x18];
6178  
6179  	u8         syndrome[0x20];
6180  
6181  	u8         reserved_at_40[0x20];
6182  
6183  	u8         gids_num[0x10];
6184  	u8         reserved_at_70[0x10];
6185  
6186  	struct mlx5_ifc_array128_auto_bits gid[];
6187  };
6188  
6189  struct mlx5_ifc_query_hca_vport_gid_in_bits {
6190  	u8         opcode[0x10];
6191  	u8         reserved_at_10[0x10];
6192  
6193  	u8         reserved_at_20[0x10];
6194  	u8         op_mod[0x10];
6195  
6196  	u8         other_vport[0x1];
6197  	u8         reserved_at_41[0xb];
6198  	u8         port_num[0x4];
6199  	u8         vport_number[0x10];
6200  
6201  	u8         reserved_at_60[0x10];
6202  	u8         gid_index[0x10];
6203  };
6204  
6205  struct mlx5_ifc_query_hca_vport_context_out_bits {
6206  	u8         status[0x8];
6207  	u8         reserved_at_8[0x18];
6208  
6209  	u8         syndrome[0x20];
6210  
6211  	u8         reserved_at_40[0x40];
6212  
6213  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6214  };
6215  
6216  struct mlx5_ifc_query_hca_vport_context_in_bits {
6217  	u8         opcode[0x10];
6218  	u8         reserved_at_10[0x10];
6219  
6220  	u8         reserved_at_20[0x10];
6221  	u8         op_mod[0x10];
6222  
6223  	u8         other_vport[0x1];
6224  	u8         reserved_at_41[0xb];
6225  	u8         port_num[0x4];
6226  	u8         vport_number[0x10];
6227  
6228  	u8         reserved_at_60[0x20];
6229  };
6230  
6231  struct mlx5_ifc_query_hca_cap_out_bits {
6232  	u8         status[0x8];
6233  	u8         reserved_at_8[0x18];
6234  
6235  	u8         syndrome[0x20];
6236  
6237  	u8         reserved_at_40[0x40];
6238  
6239  	union mlx5_ifc_hca_cap_union_bits capability;
6240  };
6241  
6242  struct mlx5_ifc_query_hca_cap_in_bits {
6243  	u8         opcode[0x10];
6244  	u8         reserved_at_10[0x10];
6245  
6246  	u8         reserved_at_20[0x10];
6247  	u8         op_mod[0x10];
6248  
6249  	u8         other_function[0x1];
6250  	u8         ec_vf_function[0x1];
6251  	u8         reserved_at_42[0xe];
6252  	u8         function_id[0x10];
6253  
6254  	u8         reserved_at_60[0x20];
6255  };
6256  
6257  struct mlx5_ifc_other_hca_cap_bits {
6258  	u8         roce[0x1];
6259  	u8         reserved_at_1[0x27f];
6260  };
6261  
6262  struct mlx5_ifc_query_other_hca_cap_out_bits {
6263  	u8         status[0x8];
6264  	u8         reserved_at_8[0x18];
6265  
6266  	u8         syndrome[0x20];
6267  
6268  	u8         reserved_at_40[0x40];
6269  
6270  	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6271  };
6272  
6273  struct mlx5_ifc_query_other_hca_cap_in_bits {
6274  	u8         opcode[0x10];
6275  	u8         reserved_at_10[0x10];
6276  
6277  	u8         reserved_at_20[0x10];
6278  	u8         op_mod[0x10];
6279  
6280  	u8         reserved_at_40[0x10];
6281  	u8         function_id[0x10];
6282  
6283  	u8         reserved_at_60[0x20];
6284  };
6285  
6286  struct mlx5_ifc_modify_other_hca_cap_out_bits {
6287  	u8         status[0x8];
6288  	u8         reserved_at_8[0x18];
6289  
6290  	u8         syndrome[0x20];
6291  
6292  	u8         reserved_at_40[0x40];
6293  };
6294  
6295  struct mlx5_ifc_modify_other_hca_cap_in_bits {
6296  	u8         opcode[0x10];
6297  	u8         reserved_at_10[0x10];
6298  
6299  	u8         reserved_at_20[0x10];
6300  	u8         op_mod[0x10];
6301  
6302  	u8         reserved_at_40[0x10];
6303  	u8         function_id[0x10];
6304  	u8         field_select[0x20];
6305  
6306  	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6307  };
6308  
6309  struct mlx5_ifc_flow_table_context_bits {
6310  	u8         reformat_en[0x1];
6311  	u8         decap_en[0x1];
6312  	u8         sw_owner[0x1];
6313  	u8         termination_table[0x1];
6314  	u8         table_miss_action[0x4];
6315  	u8         level[0x8];
6316  	u8         rtc_valid[0x1];
6317  	u8         reserved_at_11[0x7];
6318  	u8         log_size[0x8];
6319  
6320  	u8         reserved_at_20[0x8];
6321  	u8         table_miss_id[0x18];
6322  
6323  	u8         reserved_at_40[0x8];
6324  	u8         lag_master_next_table_id[0x18];
6325  
6326  	u8         reserved_at_60[0x60];
6327  	union {
6328  		struct {
6329  			u8         sw_owner_icm_root_1[0x40];
6330  
6331  			u8         sw_owner_icm_root_0[0x40];
6332  		} sws;
6333  		struct {
6334  			u8         rtc_id_0[0x20];
6335  
6336  			u8         rtc_id_1[0x20];
6337  
6338  			u8         reserved_at_100[0x40];
6339  
6340  		} hws;
6341  	};
6342  };
6343  
6344  struct mlx5_ifc_query_flow_table_out_bits {
6345  	u8         status[0x8];
6346  	u8         reserved_at_8[0x18];
6347  
6348  	u8         syndrome[0x20];
6349  
6350  	u8         reserved_at_40[0x80];
6351  
6352  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6353  };
6354  
6355  struct mlx5_ifc_query_flow_table_in_bits {
6356  	u8         opcode[0x10];
6357  	u8         reserved_at_10[0x10];
6358  
6359  	u8         reserved_at_20[0x10];
6360  	u8         op_mod[0x10];
6361  
6362  	u8         reserved_at_40[0x40];
6363  
6364  	u8         table_type[0x8];
6365  	u8         reserved_at_88[0x18];
6366  
6367  	u8         reserved_at_a0[0x8];
6368  	u8         table_id[0x18];
6369  
6370  	u8         reserved_at_c0[0x140];
6371  };
6372  
6373  struct mlx5_ifc_query_fte_out_bits {
6374  	u8         status[0x8];
6375  	u8         reserved_at_8[0x18];
6376  
6377  	u8         syndrome[0x20];
6378  
6379  	u8         reserved_at_40[0x1c0];
6380  
6381  	struct mlx5_ifc_flow_context_bits flow_context;
6382  };
6383  
6384  struct mlx5_ifc_query_fte_in_bits {
6385  	u8         opcode[0x10];
6386  	u8         reserved_at_10[0x10];
6387  
6388  	u8         reserved_at_20[0x10];
6389  	u8         op_mod[0x10];
6390  
6391  	u8         reserved_at_40[0x40];
6392  
6393  	u8         table_type[0x8];
6394  	u8         reserved_at_88[0x18];
6395  
6396  	u8         reserved_at_a0[0x8];
6397  	u8         table_id[0x18];
6398  
6399  	u8         reserved_at_c0[0x40];
6400  
6401  	u8         flow_index[0x20];
6402  
6403  	u8         reserved_at_120[0xe0];
6404  };
6405  
6406  struct mlx5_ifc_match_definer_format_0_bits {
6407  	u8         reserved_at_0[0x100];
6408  
6409  	u8         metadata_reg_c_0[0x20];
6410  
6411  	u8         metadata_reg_c_1[0x20];
6412  
6413  	u8         outer_dmac_47_16[0x20];
6414  
6415  	u8         outer_dmac_15_0[0x10];
6416  	u8         outer_ethertype[0x10];
6417  
6418  	u8         reserved_at_180[0x1];
6419  	u8         sx_sniffer[0x1];
6420  	u8         functional_lb[0x1];
6421  	u8         outer_ip_frag[0x1];
6422  	u8         outer_qp_type[0x2];
6423  	u8         outer_encap_type[0x2];
6424  	u8         port_number[0x2];
6425  	u8         outer_l3_type[0x2];
6426  	u8         outer_l4_type[0x2];
6427  	u8         outer_first_vlan_type[0x2];
6428  	u8         outer_first_vlan_prio[0x3];
6429  	u8         outer_first_vlan_cfi[0x1];
6430  	u8         outer_first_vlan_vid[0xc];
6431  
6432  	u8         outer_l4_type_ext[0x4];
6433  	u8         reserved_at_1a4[0x2];
6434  	u8         outer_ipsec_layer[0x2];
6435  	u8         outer_l2_type[0x2];
6436  	u8         force_lb[0x1];
6437  	u8         outer_l2_ok[0x1];
6438  	u8         outer_l3_ok[0x1];
6439  	u8         outer_l4_ok[0x1];
6440  	u8         outer_second_vlan_type[0x2];
6441  	u8         outer_second_vlan_prio[0x3];
6442  	u8         outer_second_vlan_cfi[0x1];
6443  	u8         outer_second_vlan_vid[0xc];
6444  
6445  	u8         outer_smac_47_16[0x20];
6446  
6447  	u8         outer_smac_15_0[0x10];
6448  	u8         inner_ipv4_checksum_ok[0x1];
6449  	u8         inner_l4_checksum_ok[0x1];
6450  	u8         outer_ipv4_checksum_ok[0x1];
6451  	u8         outer_l4_checksum_ok[0x1];
6452  	u8         inner_l3_ok[0x1];
6453  	u8         inner_l4_ok[0x1];
6454  	u8         outer_l3_ok_duplicate[0x1];
6455  	u8         outer_l4_ok_duplicate[0x1];
6456  	u8         outer_tcp_cwr[0x1];
6457  	u8         outer_tcp_ece[0x1];
6458  	u8         outer_tcp_urg[0x1];
6459  	u8         outer_tcp_ack[0x1];
6460  	u8         outer_tcp_psh[0x1];
6461  	u8         outer_tcp_rst[0x1];
6462  	u8         outer_tcp_syn[0x1];
6463  	u8         outer_tcp_fin[0x1];
6464  };
6465  
6466  struct mlx5_ifc_match_definer_format_22_bits {
6467  	u8         reserved_at_0[0x100];
6468  
6469  	u8         outer_ip_src_addr[0x20];
6470  
6471  	u8         outer_ip_dest_addr[0x20];
6472  
6473  	u8         outer_l4_sport[0x10];
6474  	u8         outer_l4_dport[0x10];
6475  
6476  	u8         reserved_at_160[0x1];
6477  	u8         sx_sniffer[0x1];
6478  	u8         functional_lb[0x1];
6479  	u8         outer_ip_frag[0x1];
6480  	u8         outer_qp_type[0x2];
6481  	u8         outer_encap_type[0x2];
6482  	u8         port_number[0x2];
6483  	u8         outer_l3_type[0x2];
6484  	u8         outer_l4_type[0x2];
6485  	u8         outer_first_vlan_type[0x2];
6486  	u8         outer_first_vlan_prio[0x3];
6487  	u8         outer_first_vlan_cfi[0x1];
6488  	u8         outer_first_vlan_vid[0xc];
6489  
6490  	u8         metadata_reg_c_0[0x20];
6491  
6492  	u8         outer_dmac_47_16[0x20];
6493  
6494  	u8         outer_smac_47_16[0x20];
6495  
6496  	u8         outer_smac_15_0[0x10];
6497  	u8         outer_dmac_15_0[0x10];
6498  };
6499  
6500  struct mlx5_ifc_match_definer_format_23_bits {
6501  	u8         reserved_at_0[0x100];
6502  
6503  	u8         inner_ip_src_addr[0x20];
6504  
6505  	u8         inner_ip_dest_addr[0x20];
6506  
6507  	u8         inner_l4_sport[0x10];
6508  	u8         inner_l4_dport[0x10];
6509  
6510  	u8         reserved_at_160[0x1];
6511  	u8         sx_sniffer[0x1];
6512  	u8         functional_lb[0x1];
6513  	u8         inner_ip_frag[0x1];
6514  	u8         inner_qp_type[0x2];
6515  	u8         inner_encap_type[0x2];
6516  	u8         port_number[0x2];
6517  	u8         inner_l3_type[0x2];
6518  	u8         inner_l4_type[0x2];
6519  	u8         inner_first_vlan_type[0x2];
6520  	u8         inner_first_vlan_prio[0x3];
6521  	u8         inner_first_vlan_cfi[0x1];
6522  	u8         inner_first_vlan_vid[0xc];
6523  
6524  	u8         tunnel_header_0[0x20];
6525  
6526  	u8         inner_dmac_47_16[0x20];
6527  
6528  	u8         inner_smac_47_16[0x20];
6529  
6530  	u8         inner_smac_15_0[0x10];
6531  	u8         inner_dmac_15_0[0x10];
6532  };
6533  
6534  struct mlx5_ifc_match_definer_format_29_bits {
6535  	u8         reserved_at_0[0xc0];
6536  
6537  	u8         outer_ip_dest_addr[0x80];
6538  
6539  	u8         outer_ip_src_addr[0x80];
6540  
6541  	u8         outer_l4_sport[0x10];
6542  	u8         outer_l4_dport[0x10];
6543  
6544  	u8         reserved_at_1e0[0x20];
6545  };
6546  
6547  struct mlx5_ifc_match_definer_format_30_bits {
6548  	u8         reserved_at_0[0xa0];
6549  
6550  	u8         outer_ip_dest_addr[0x80];
6551  
6552  	u8         outer_ip_src_addr[0x80];
6553  
6554  	u8         outer_dmac_47_16[0x20];
6555  
6556  	u8         outer_smac_47_16[0x20];
6557  
6558  	u8         outer_smac_15_0[0x10];
6559  	u8         outer_dmac_15_0[0x10];
6560  };
6561  
6562  struct mlx5_ifc_match_definer_format_31_bits {
6563  	u8         reserved_at_0[0xc0];
6564  
6565  	u8         inner_ip_dest_addr[0x80];
6566  
6567  	u8         inner_ip_src_addr[0x80];
6568  
6569  	u8         inner_l4_sport[0x10];
6570  	u8         inner_l4_dport[0x10];
6571  
6572  	u8         reserved_at_1e0[0x20];
6573  };
6574  
6575  struct mlx5_ifc_match_definer_format_32_bits {
6576  	u8         reserved_at_0[0xa0];
6577  
6578  	u8         inner_ip_dest_addr[0x80];
6579  
6580  	u8         inner_ip_src_addr[0x80];
6581  
6582  	u8         inner_dmac_47_16[0x20];
6583  
6584  	u8         inner_smac_47_16[0x20];
6585  
6586  	u8         inner_smac_15_0[0x10];
6587  	u8         inner_dmac_15_0[0x10];
6588  };
6589  
6590  enum {
6591  	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6592  };
6593  
6594  #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6595  #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6596  #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6597  #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6598  
6599  struct mlx5_ifc_match_definer_match_mask_bits {
6600  	u8         reserved_at_1c0[5][0x20];
6601  	u8         match_dw_8[0x20];
6602  	u8         match_dw_7[0x20];
6603  	u8         match_dw_6[0x20];
6604  	u8         match_dw_5[0x20];
6605  	u8         match_dw_4[0x20];
6606  	u8         match_dw_3[0x20];
6607  	u8         match_dw_2[0x20];
6608  	u8         match_dw_1[0x20];
6609  	u8         match_dw_0[0x20];
6610  
6611  	u8         match_byte_7[0x8];
6612  	u8         match_byte_6[0x8];
6613  	u8         match_byte_5[0x8];
6614  	u8         match_byte_4[0x8];
6615  
6616  	u8         match_byte_3[0x8];
6617  	u8         match_byte_2[0x8];
6618  	u8         match_byte_1[0x8];
6619  	u8         match_byte_0[0x8];
6620  };
6621  
6622  struct mlx5_ifc_match_definer_bits {
6623  	u8         modify_field_select[0x40];
6624  
6625  	u8         reserved_at_40[0x40];
6626  
6627  	u8         reserved_at_80[0x10];
6628  	u8         format_id[0x10];
6629  
6630  	u8         reserved_at_a0[0x60];
6631  
6632  	u8         format_select_dw3[0x8];
6633  	u8         format_select_dw2[0x8];
6634  	u8         format_select_dw1[0x8];
6635  	u8         format_select_dw0[0x8];
6636  
6637  	u8         format_select_dw7[0x8];
6638  	u8         format_select_dw6[0x8];
6639  	u8         format_select_dw5[0x8];
6640  	u8         format_select_dw4[0x8];
6641  
6642  	u8         reserved_at_100[0x18];
6643  	u8         format_select_dw8[0x8];
6644  
6645  	u8         reserved_at_120[0x20];
6646  
6647  	u8         format_select_byte3[0x8];
6648  	u8         format_select_byte2[0x8];
6649  	u8         format_select_byte1[0x8];
6650  	u8         format_select_byte0[0x8];
6651  
6652  	u8         format_select_byte7[0x8];
6653  	u8         format_select_byte6[0x8];
6654  	u8         format_select_byte5[0x8];
6655  	u8         format_select_byte4[0x8];
6656  
6657  	u8         reserved_at_180[0x40];
6658  
6659  	union {
6660  		struct {
6661  			u8         match_mask[16][0x20];
6662  		};
6663  		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6664  	};
6665  };
6666  
6667  struct mlx5_ifc_general_obj_create_param_bits {
6668  	u8         alias_object[0x1];
6669  	u8         reserved_at_1[0x2];
6670  	u8         log_obj_range[0x5];
6671  	u8         reserved_at_8[0x18];
6672  };
6673  
6674  struct mlx5_ifc_general_obj_query_param_bits {
6675  	u8         alias_object[0x1];
6676  	u8         obj_offset[0x1f];
6677  };
6678  
6679  struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6680  	u8         opcode[0x10];
6681  	u8         uid[0x10];
6682  
6683  	u8         vhca_tunnel_id[0x10];
6684  	u8         obj_type[0x10];
6685  
6686  	u8         obj_id[0x20];
6687  
6688  	union {
6689  		struct mlx5_ifc_general_obj_create_param_bits create;
6690  		struct mlx5_ifc_general_obj_query_param_bits query;
6691  	} op_param;
6692  };
6693  
6694  struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6695  	u8         status[0x8];
6696  	u8         reserved_at_8[0x18];
6697  
6698  	u8         syndrome[0x20];
6699  
6700  	u8         obj_id[0x20];
6701  
6702  	u8         reserved_at_60[0x20];
6703  };
6704  
6705  struct mlx5_ifc_allow_other_vhca_access_in_bits {
6706  	u8 opcode[0x10];
6707  	u8 uid[0x10];
6708  	u8 reserved_at_20[0x10];
6709  	u8 op_mod[0x10];
6710  	u8 reserved_at_40[0x50];
6711  	u8 object_type_to_be_accessed[0x10];
6712  	u8 object_id_to_be_accessed[0x20];
6713  	u8 reserved_at_c0[0x40];
6714  	union {
6715  		u8 access_key_raw[0x100];
6716  		u8 access_key[8][0x20];
6717  	};
6718  };
6719  
6720  struct mlx5_ifc_allow_other_vhca_access_out_bits {
6721  	u8 status[0x8];
6722  	u8 reserved_at_8[0x18];
6723  	u8 syndrome[0x20];
6724  	u8 reserved_at_40[0x40];
6725  };
6726  
6727  struct mlx5_ifc_modify_header_arg_bits {
6728  	u8         reserved_at_0[0x80];
6729  
6730  	u8         reserved_at_80[0x8];
6731  	u8         access_pd[0x18];
6732  };
6733  
6734  struct mlx5_ifc_create_modify_header_arg_in_bits {
6735  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6736  	struct mlx5_ifc_modify_header_arg_bits arg;
6737  };
6738  
6739  struct mlx5_ifc_create_match_definer_in_bits {
6740  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6741  
6742  	struct mlx5_ifc_match_definer_bits obj_context;
6743  };
6744  
6745  struct mlx5_ifc_create_match_definer_out_bits {
6746  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6747  };
6748  
6749  struct mlx5_ifc_alias_context_bits {
6750  	u8 vhca_id_to_be_accessed[0x10];
6751  	u8 reserved_at_10[0xd];
6752  	u8 status[0x3];
6753  	u8 object_id_to_be_accessed[0x20];
6754  	u8 reserved_at_40[0x40];
6755  	union {
6756  		u8 access_key_raw[0x100];
6757  		u8 access_key[8][0x20];
6758  	};
6759  	u8 metadata[0x80];
6760  };
6761  
6762  struct mlx5_ifc_create_alias_obj_in_bits {
6763  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6764  	struct mlx5_ifc_alias_context_bits alias_ctx;
6765  };
6766  
6767  enum {
6768  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6769  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6770  	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6771  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6772  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6773  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6774  	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6775  };
6776  
6777  struct mlx5_ifc_query_flow_group_out_bits {
6778  	u8         status[0x8];
6779  	u8         reserved_at_8[0x18];
6780  
6781  	u8         syndrome[0x20];
6782  
6783  	u8         reserved_at_40[0xa0];
6784  
6785  	u8         start_flow_index[0x20];
6786  
6787  	u8         reserved_at_100[0x20];
6788  
6789  	u8         end_flow_index[0x20];
6790  
6791  	u8         reserved_at_140[0xa0];
6792  
6793  	u8         reserved_at_1e0[0x18];
6794  	u8         match_criteria_enable[0x8];
6795  
6796  	struct mlx5_ifc_fte_match_param_bits match_criteria;
6797  
6798  	u8         reserved_at_1200[0xe00];
6799  };
6800  
6801  struct mlx5_ifc_query_flow_group_in_bits {
6802  	u8         opcode[0x10];
6803  	u8         reserved_at_10[0x10];
6804  
6805  	u8         reserved_at_20[0x10];
6806  	u8         op_mod[0x10];
6807  
6808  	u8         reserved_at_40[0x40];
6809  
6810  	u8         table_type[0x8];
6811  	u8         reserved_at_88[0x18];
6812  
6813  	u8         reserved_at_a0[0x8];
6814  	u8         table_id[0x18];
6815  
6816  	u8         group_id[0x20];
6817  
6818  	u8         reserved_at_e0[0x120];
6819  };
6820  
6821  struct mlx5_ifc_query_flow_counter_out_bits {
6822  	u8         status[0x8];
6823  	u8         reserved_at_8[0x18];
6824  
6825  	u8         syndrome[0x20];
6826  
6827  	u8         reserved_at_40[0x40];
6828  
6829  	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6830  };
6831  
6832  struct mlx5_ifc_query_flow_counter_in_bits {
6833  	u8         opcode[0x10];
6834  	u8         reserved_at_10[0x10];
6835  
6836  	u8         reserved_at_20[0x10];
6837  	u8         op_mod[0x10];
6838  
6839  	u8         reserved_at_40[0x80];
6840  
6841  	u8         clear[0x1];
6842  	u8         reserved_at_c1[0xf];
6843  	u8         num_of_counters[0x10];
6844  
6845  	u8         flow_counter_id[0x20];
6846  };
6847  
6848  struct mlx5_ifc_query_esw_vport_context_out_bits {
6849  	u8         status[0x8];
6850  	u8         reserved_at_8[0x18];
6851  
6852  	u8         syndrome[0x20];
6853  
6854  	u8         reserved_at_40[0x40];
6855  
6856  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6857  };
6858  
6859  struct mlx5_ifc_query_esw_vport_context_in_bits {
6860  	u8         opcode[0x10];
6861  	u8         reserved_at_10[0x10];
6862  
6863  	u8         reserved_at_20[0x10];
6864  	u8         op_mod[0x10];
6865  
6866  	u8         other_vport[0x1];
6867  	u8         reserved_at_41[0xf];
6868  	u8         vport_number[0x10];
6869  
6870  	u8         reserved_at_60[0x20];
6871  };
6872  
6873  struct mlx5_ifc_modify_esw_vport_context_out_bits {
6874  	u8         status[0x8];
6875  	u8         reserved_at_8[0x18];
6876  
6877  	u8         syndrome[0x20];
6878  
6879  	u8         reserved_at_40[0x40];
6880  };
6881  
6882  struct mlx5_ifc_esw_vport_context_fields_select_bits {
6883  	u8         reserved_at_0[0x1b];
6884  	u8         fdb_to_vport_reg_c_id[0x1];
6885  	u8         vport_cvlan_insert[0x1];
6886  	u8         vport_svlan_insert[0x1];
6887  	u8         vport_cvlan_strip[0x1];
6888  	u8         vport_svlan_strip[0x1];
6889  };
6890  
6891  struct mlx5_ifc_modify_esw_vport_context_in_bits {
6892  	u8         opcode[0x10];
6893  	u8         reserved_at_10[0x10];
6894  
6895  	u8         reserved_at_20[0x10];
6896  	u8         op_mod[0x10];
6897  
6898  	u8         other_vport[0x1];
6899  	u8         reserved_at_41[0xf];
6900  	u8         vport_number[0x10];
6901  
6902  	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6903  
6904  	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6905  };
6906  
6907  struct mlx5_ifc_query_eq_out_bits {
6908  	u8         status[0x8];
6909  	u8         reserved_at_8[0x18];
6910  
6911  	u8         syndrome[0x20];
6912  
6913  	u8         reserved_at_40[0x40];
6914  
6915  	struct mlx5_ifc_eqc_bits eq_context_entry;
6916  
6917  	u8         reserved_at_280[0x40];
6918  
6919  	u8         event_bitmask[0x40];
6920  
6921  	u8         reserved_at_300[0x580];
6922  
6923  	u8         pas[][0x40];
6924  };
6925  
6926  struct mlx5_ifc_query_eq_in_bits {
6927  	u8         opcode[0x10];
6928  	u8         reserved_at_10[0x10];
6929  
6930  	u8         reserved_at_20[0x10];
6931  	u8         op_mod[0x10];
6932  
6933  	u8         reserved_at_40[0x18];
6934  	u8         eq_number[0x8];
6935  
6936  	u8         reserved_at_60[0x20];
6937  };
6938  
6939  struct mlx5_ifc_packet_reformat_context_in_bits {
6940  	u8         reformat_type[0x8];
6941  	u8         reserved_at_8[0x4];
6942  	u8         reformat_param_0[0x4];
6943  	u8         reserved_at_10[0x6];
6944  	u8         reformat_data_size[0xa];
6945  
6946  	u8         reformat_param_1[0x8];
6947  	u8         reserved_at_28[0x8];
6948  	u8         reformat_data[2][0x8];
6949  
6950  	u8         more_reformat_data[][0x8];
6951  };
6952  
6953  struct mlx5_ifc_query_packet_reformat_context_out_bits {
6954  	u8         status[0x8];
6955  	u8         reserved_at_8[0x18];
6956  
6957  	u8         syndrome[0x20];
6958  
6959  	u8         reserved_at_40[0xa0];
6960  
6961  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6962  };
6963  
6964  struct mlx5_ifc_query_packet_reformat_context_in_bits {
6965  	u8         opcode[0x10];
6966  	u8         reserved_at_10[0x10];
6967  
6968  	u8         reserved_at_20[0x10];
6969  	u8         op_mod[0x10];
6970  
6971  	u8         packet_reformat_id[0x20];
6972  
6973  	u8         reserved_at_60[0xa0];
6974  };
6975  
6976  struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6977  	u8         status[0x8];
6978  	u8         reserved_at_8[0x18];
6979  
6980  	u8         syndrome[0x20];
6981  
6982  	u8         packet_reformat_id[0x20];
6983  
6984  	u8         reserved_at_60[0x20];
6985  };
6986  
6987  enum {
6988  	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6989  	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6990  	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6991  };
6992  
6993  enum mlx5_reformat_ctx_type {
6994  	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6995  	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6996  	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6997  	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6998  	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6999  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7000  	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7001  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7002  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7003  	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7004  	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7005  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7006  	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7007  	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7008  	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7009  	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7010  	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7011  };
7012  
7013  struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7014  	u8         opcode[0x10];
7015  	u8         reserved_at_10[0x10];
7016  
7017  	u8         reserved_at_20[0x10];
7018  	u8         op_mod[0x10];
7019  
7020  	u8         reserved_at_40[0xa0];
7021  
7022  	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7023  };
7024  
7025  struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7026  	u8         status[0x8];
7027  	u8         reserved_at_8[0x18];
7028  
7029  	u8         syndrome[0x20];
7030  
7031  	u8         reserved_at_40[0x40];
7032  };
7033  
7034  struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7035  	u8         opcode[0x10];
7036  	u8         reserved_at_10[0x10];
7037  
7038  	u8         reserved_20[0x10];
7039  	u8         op_mod[0x10];
7040  
7041  	u8         packet_reformat_id[0x20];
7042  
7043  	u8         reserved_60[0x20];
7044  };
7045  
7046  struct mlx5_ifc_set_action_in_bits {
7047  	u8         action_type[0x4];
7048  	u8         field[0xc];
7049  	u8         reserved_at_10[0x3];
7050  	u8         offset[0x5];
7051  	u8         reserved_at_18[0x3];
7052  	u8         length[0x5];
7053  
7054  	u8         data[0x20];
7055  };
7056  
7057  struct mlx5_ifc_add_action_in_bits {
7058  	u8         action_type[0x4];
7059  	u8         field[0xc];
7060  	u8         reserved_at_10[0x10];
7061  
7062  	u8         data[0x20];
7063  };
7064  
7065  struct mlx5_ifc_copy_action_in_bits {
7066  	u8         action_type[0x4];
7067  	u8         src_field[0xc];
7068  	u8         reserved_at_10[0x3];
7069  	u8         src_offset[0x5];
7070  	u8         reserved_at_18[0x3];
7071  	u8         length[0x5];
7072  
7073  	u8         reserved_at_20[0x4];
7074  	u8         dst_field[0xc];
7075  	u8         reserved_at_30[0x3];
7076  	u8         dst_offset[0x5];
7077  	u8         reserved_at_38[0x8];
7078  };
7079  
7080  union mlx5_ifc_set_add_copy_action_in_auto_bits {
7081  	struct mlx5_ifc_set_action_in_bits  set_action_in;
7082  	struct mlx5_ifc_add_action_in_bits  add_action_in;
7083  	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7084  	u8         reserved_at_0[0x40];
7085  };
7086  
7087  enum {
7088  	MLX5_ACTION_TYPE_SET   = 0x1,
7089  	MLX5_ACTION_TYPE_ADD   = 0x2,
7090  	MLX5_ACTION_TYPE_COPY  = 0x3,
7091  };
7092  
7093  enum {
7094  	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7095  	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7096  	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7097  	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7098  	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7099  	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7100  	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7101  	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7102  	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7103  	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7104  	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7105  	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7106  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7107  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7108  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7109  	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7110  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7111  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7112  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7113  	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7114  	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7115  	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7116  	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7117  	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7118  	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7119  	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7120  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7121  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7122  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7123  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7124  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7125  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7126  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7127  	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7128  	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7129  	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7130  	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7131  	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7132  	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7133  };
7134  
7135  struct mlx5_ifc_alloc_modify_header_context_out_bits {
7136  	u8         status[0x8];
7137  	u8         reserved_at_8[0x18];
7138  
7139  	u8         syndrome[0x20];
7140  
7141  	u8         modify_header_id[0x20];
7142  
7143  	u8         reserved_at_60[0x20];
7144  };
7145  
7146  struct mlx5_ifc_alloc_modify_header_context_in_bits {
7147  	u8         opcode[0x10];
7148  	u8         reserved_at_10[0x10];
7149  
7150  	u8         reserved_at_20[0x10];
7151  	u8         op_mod[0x10];
7152  
7153  	u8         reserved_at_40[0x20];
7154  
7155  	u8         table_type[0x8];
7156  	u8         reserved_at_68[0x10];
7157  	u8         num_of_actions[0x8];
7158  
7159  	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7160  };
7161  
7162  struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7163  	u8         status[0x8];
7164  	u8         reserved_at_8[0x18];
7165  
7166  	u8         syndrome[0x20];
7167  
7168  	u8         reserved_at_40[0x40];
7169  };
7170  
7171  struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7172  	u8         opcode[0x10];
7173  	u8         reserved_at_10[0x10];
7174  
7175  	u8         reserved_at_20[0x10];
7176  	u8         op_mod[0x10];
7177  
7178  	u8         modify_header_id[0x20];
7179  
7180  	u8         reserved_at_60[0x20];
7181  };
7182  
7183  struct mlx5_ifc_query_modify_header_context_in_bits {
7184  	u8         opcode[0x10];
7185  	u8         uid[0x10];
7186  
7187  	u8         reserved_at_20[0x10];
7188  	u8         op_mod[0x10];
7189  
7190  	u8         modify_header_id[0x20];
7191  
7192  	u8         reserved_at_60[0xa0];
7193  };
7194  
7195  struct mlx5_ifc_query_dct_out_bits {
7196  	u8         status[0x8];
7197  	u8         reserved_at_8[0x18];
7198  
7199  	u8         syndrome[0x20];
7200  
7201  	u8         reserved_at_40[0x40];
7202  
7203  	struct mlx5_ifc_dctc_bits dct_context_entry;
7204  
7205  	u8         reserved_at_280[0x180];
7206  };
7207  
7208  struct mlx5_ifc_query_dct_in_bits {
7209  	u8         opcode[0x10];
7210  	u8         reserved_at_10[0x10];
7211  
7212  	u8         reserved_at_20[0x10];
7213  	u8         op_mod[0x10];
7214  
7215  	u8         reserved_at_40[0x8];
7216  	u8         dctn[0x18];
7217  
7218  	u8         reserved_at_60[0x20];
7219  };
7220  
7221  struct mlx5_ifc_query_cq_out_bits {
7222  	u8         status[0x8];
7223  	u8         reserved_at_8[0x18];
7224  
7225  	u8         syndrome[0x20];
7226  
7227  	u8         reserved_at_40[0x40];
7228  
7229  	struct mlx5_ifc_cqc_bits cq_context;
7230  
7231  	u8         reserved_at_280[0x600];
7232  
7233  	u8         pas[][0x40];
7234  };
7235  
7236  struct mlx5_ifc_query_cq_in_bits {
7237  	u8         opcode[0x10];
7238  	u8         reserved_at_10[0x10];
7239  
7240  	u8         reserved_at_20[0x10];
7241  	u8         op_mod[0x10];
7242  
7243  	u8         reserved_at_40[0x8];
7244  	u8         cqn[0x18];
7245  
7246  	u8         reserved_at_60[0x20];
7247  };
7248  
7249  struct mlx5_ifc_query_cong_status_out_bits {
7250  	u8         status[0x8];
7251  	u8         reserved_at_8[0x18];
7252  
7253  	u8         syndrome[0x20];
7254  
7255  	u8         reserved_at_40[0x20];
7256  
7257  	u8         enable[0x1];
7258  	u8         tag_enable[0x1];
7259  	u8         reserved_at_62[0x1e];
7260  };
7261  
7262  struct mlx5_ifc_query_cong_status_in_bits {
7263  	u8         opcode[0x10];
7264  	u8         reserved_at_10[0x10];
7265  
7266  	u8         reserved_at_20[0x10];
7267  	u8         op_mod[0x10];
7268  
7269  	u8         reserved_at_40[0x18];
7270  	u8         priority[0x4];
7271  	u8         cong_protocol[0x4];
7272  
7273  	u8         reserved_at_60[0x20];
7274  };
7275  
7276  struct mlx5_ifc_query_cong_statistics_out_bits {
7277  	u8         status[0x8];
7278  	u8         reserved_at_8[0x18];
7279  
7280  	u8         syndrome[0x20];
7281  
7282  	u8         reserved_at_40[0x40];
7283  
7284  	u8         rp_cur_flows[0x20];
7285  
7286  	u8         sum_flows[0x20];
7287  
7288  	u8         rp_cnp_ignored_high[0x20];
7289  
7290  	u8         rp_cnp_ignored_low[0x20];
7291  
7292  	u8         rp_cnp_handled_high[0x20];
7293  
7294  	u8         rp_cnp_handled_low[0x20];
7295  
7296  	u8         reserved_at_140[0x100];
7297  
7298  	u8         time_stamp_high[0x20];
7299  
7300  	u8         time_stamp_low[0x20];
7301  
7302  	u8         accumulators_period[0x20];
7303  
7304  	u8         np_ecn_marked_roce_packets_high[0x20];
7305  
7306  	u8         np_ecn_marked_roce_packets_low[0x20];
7307  
7308  	u8         np_cnp_sent_high[0x20];
7309  
7310  	u8         np_cnp_sent_low[0x20];
7311  
7312  	u8         reserved_at_320[0x560];
7313  };
7314  
7315  struct mlx5_ifc_query_cong_statistics_in_bits {
7316  	u8         opcode[0x10];
7317  	u8         reserved_at_10[0x10];
7318  
7319  	u8         reserved_at_20[0x10];
7320  	u8         op_mod[0x10];
7321  
7322  	u8         clear[0x1];
7323  	u8         reserved_at_41[0x1f];
7324  
7325  	u8         reserved_at_60[0x20];
7326  };
7327  
7328  struct mlx5_ifc_query_cong_params_out_bits {
7329  	u8         status[0x8];
7330  	u8         reserved_at_8[0x18];
7331  
7332  	u8         syndrome[0x20];
7333  
7334  	u8         reserved_at_40[0x40];
7335  
7336  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7337  };
7338  
7339  struct mlx5_ifc_query_cong_params_in_bits {
7340  	u8         opcode[0x10];
7341  	u8         reserved_at_10[0x10];
7342  
7343  	u8         reserved_at_20[0x10];
7344  	u8         op_mod[0x10];
7345  
7346  	u8         reserved_at_40[0x1c];
7347  	u8         cong_protocol[0x4];
7348  
7349  	u8         reserved_at_60[0x20];
7350  };
7351  
7352  struct mlx5_ifc_query_adapter_out_bits {
7353  	u8         status[0x8];
7354  	u8         reserved_at_8[0x18];
7355  
7356  	u8         syndrome[0x20];
7357  
7358  	u8         reserved_at_40[0x40];
7359  
7360  	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7361  };
7362  
7363  struct mlx5_ifc_query_adapter_in_bits {
7364  	u8         opcode[0x10];
7365  	u8         reserved_at_10[0x10];
7366  
7367  	u8         reserved_at_20[0x10];
7368  	u8         op_mod[0x10];
7369  
7370  	u8         reserved_at_40[0x40];
7371  };
7372  
7373  struct mlx5_ifc_qp_2rst_out_bits {
7374  	u8         status[0x8];
7375  	u8         reserved_at_8[0x18];
7376  
7377  	u8         syndrome[0x20];
7378  
7379  	u8         reserved_at_40[0x40];
7380  };
7381  
7382  struct mlx5_ifc_qp_2rst_in_bits {
7383  	u8         opcode[0x10];
7384  	u8         uid[0x10];
7385  
7386  	u8         reserved_at_20[0x10];
7387  	u8         op_mod[0x10];
7388  
7389  	u8         reserved_at_40[0x8];
7390  	u8         qpn[0x18];
7391  
7392  	u8         reserved_at_60[0x20];
7393  };
7394  
7395  struct mlx5_ifc_qp_2err_out_bits {
7396  	u8         status[0x8];
7397  	u8         reserved_at_8[0x18];
7398  
7399  	u8         syndrome[0x20];
7400  
7401  	u8         reserved_at_40[0x40];
7402  };
7403  
7404  struct mlx5_ifc_qp_2err_in_bits {
7405  	u8         opcode[0x10];
7406  	u8         uid[0x10];
7407  
7408  	u8         reserved_at_20[0x10];
7409  	u8         op_mod[0x10];
7410  
7411  	u8         reserved_at_40[0x8];
7412  	u8         qpn[0x18];
7413  
7414  	u8         reserved_at_60[0x20];
7415  };
7416  
7417  struct mlx5_ifc_trans_page_fault_info_bits {
7418  	u8         error[0x1];
7419  	u8         reserved_at_1[0x4];
7420  	u8         page_fault_type[0x3];
7421  	u8         wq_number[0x18];
7422  
7423  	u8         reserved_at_20[0x8];
7424  	u8         fault_token[0x18];
7425  };
7426  
7427  struct mlx5_ifc_mem_page_fault_info_bits {
7428  	u8          error[0x1];
7429  	u8          reserved_at_1[0xf];
7430  	u8          fault_token_47_32[0x10];
7431  
7432  	u8          fault_token_31_0[0x20];
7433  };
7434  
7435  union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7436  	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7437  	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7438  	u8          reserved_at_0[0x40];
7439  };
7440  
7441  struct mlx5_ifc_page_fault_resume_out_bits {
7442  	u8         status[0x8];
7443  	u8         reserved_at_8[0x18];
7444  
7445  	u8         syndrome[0x20];
7446  
7447  	u8         reserved_at_40[0x40];
7448  };
7449  
7450  struct mlx5_ifc_page_fault_resume_in_bits {
7451  	u8         opcode[0x10];
7452  	u8         reserved_at_10[0x10];
7453  
7454  	u8         reserved_at_20[0x10];
7455  	u8         op_mod[0x10];
7456  
7457  	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7458  		page_fault_info;
7459  };
7460  
7461  struct mlx5_ifc_nop_out_bits {
7462  	u8         status[0x8];
7463  	u8         reserved_at_8[0x18];
7464  
7465  	u8         syndrome[0x20];
7466  
7467  	u8         reserved_at_40[0x40];
7468  };
7469  
7470  struct mlx5_ifc_nop_in_bits {
7471  	u8         opcode[0x10];
7472  	u8         reserved_at_10[0x10];
7473  
7474  	u8         reserved_at_20[0x10];
7475  	u8         op_mod[0x10];
7476  
7477  	u8         reserved_at_40[0x40];
7478  };
7479  
7480  struct mlx5_ifc_modify_vport_state_out_bits {
7481  	u8         status[0x8];
7482  	u8         reserved_at_8[0x18];
7483  
7484  	u8         syndrome[0x20];
7485  
7486  	u8         reserved_at_40[0x40];
7487  };
7488  
7489  struct mlx5_ifc_modify_vport_state_in_bits {
7490  	u8         opcode[0x10];
7491  	u8         reserved_at_10[0x10];
7492  
7493  	u8         reserved_at_20[0x10];
7494  	u8         op_mod[0x10];
7495  
7496  	u8         other_vport[0x1];
7497  	u8         reserved_at_41[0xf];
7498  	u8         vport_number[0x10];
7499  
7500  	u8         reserved_at_60[0x18];
7501  	u8         admin_state[0x4];
7502  	u8         reserved_at_7c[0x4];
7503  };
7504  
7505  struct mlx5_ifc_modify_tis_out_bits {
7506  	u8         status[0x8];
7507  	u8         reserved_at_8[0x18];
7508  
7509  	u8         syndrome[0x20];
7510  
7511  	u8         reserved_at_40[0x40];
7512  };
7513  
7514  struct mlx5_ifc_modify_tis_bitmask_bits {
7515  	u8         reserved_at_0[0x20];
7516  
7517  	u8         reserved_at_20[0x1d];
7518  	u8         lag_tx_port_affinity[0x1];
7519  	u8         strict_lag_tx_port_affinity[0x1];
7520  	u8         prio[0x1];
7521  };
7522  
7523  struct mlx5_ifc_modify_tis_in_bits {
7524  	u8         opcode[0x10];
7525  	u8         uid[0x10];
7526  
7527  	u8         reserved_at_20[0x10];
7528  	u8         op_mod[0x10];
7529  
7530  	u8         reserved_at_40[0x8];
7531  	u8         tisn[0x18];
7532  
7533  	u8         reserved_at_60[0x20];
7534  
7535  	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7536  
7537  	u8         reserved_at_c0[0x40];
7538  
7539  	struct mlx5_ifc_tisc_bits ctx;
7540  };
7541  
7542  struct mlx5_ifc_modify_tir_bitmask_bits {
7543  	u8	   reserved_at_0[0x20];
7544  
7545  	u8         reserved_at_20[0x1b];
7546  	u8         self_lb_en[0x1];
7547  	u8         reserved_at_3c[0x1];
7548  	u8         hash[0x1];
7549  	u8         reserved_at_3e[0x1];
7550  	u8         packet_merge[0x1];
7551  };
7552  
7553  struct mlx5_ifc_modify_tir_out_bits {
7554  	u8         status[0x8];
7555  	u8         reserved_at_8[0x18];
7556  
7557  	u8         syndrome[0x20];
7558  
7559  	u8         reserved_at_40[0x40];
7560  };
7561  
7562  struct mlx5_ifc_modify_tir_in_bits {
7563  	u8         opcode[0x10];
7564  	u8         uid[0x10];
7565  
7566  	u8         reserved_at_20[0x10];
7567  	u8         op_mod[0x10];
7568  
7569  	u8         reserved_at_40[0x8];
7570  	u8         tirn[0x18];
7571  
7572  	u8         reserved_at_60[0x20];
7573  
7574  	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7575  
7576  	u8         reserved_at_c0[0x40];
7577  
7578  	struct mlx5_ifc_tirc_bits ctx;
7579  };
7580  
7581  struct mlx5_ifc_modify_sq_out_bits {
7582  	u8         status[0x8];
7583  	u8         reserved_at_8[0x18];
7584  
7585  	u8         syndrome[0x20];
7586  
7587  	u8         reserved_at_40[0x40];
7588  };
7589  
7590  struct mlx5_ifc_modify_sq_in_bits {
7591  	u8         opcode[0x10];
7592  	u8         uid[0x10];
7593  
7594  	u8         reserved_at_20[0x10];
7595  	u8         op_mod[0x10];
7596  
7597  	u8         sq_state[0x4];
7598  	u8         reserved_at_44[0x4];
7599  	u8         sqn[0x18];
7600  
7601  	u8         reserved_at_60[0x20];
7602  
7603  	u8         modify_bitmask[0x40];
7604  
7605  	u8         reserved_at_c0[0x40];
7606  
7607  	struct mlx5_ifc_sqc_bits ctx;
7608  };
7609  
7610  struct mlx5_ifc_modify_scheduling_element_out_bits {
7611  	u8         status[0x8];
7612  	u8         reserved_at_8[0x18];
7613  
7614  	u8         syndrome[0x20];
7615  
7616  	u8         reserved_at_40[0x1c0];
7617  };
7618  
7619  enum {
7620  	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7621  	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7622  };
7623  
7624  struct mlx5_ifc_modify_scheduling_element_in_bits {
7625  	u8         opcode[0x10];
7626  	u8         reserved_at_10[0x10];
7627  
7628  	u8         reserved_at_20[0x10];
7629  	u8         op_mod[0x10];
7630  
7631  	u8         scheduling_hierarchy[0x8];
7632  	u8         reserved_at_48[0x18];
7633  
7634  	u8         scheduling_element_id[0x20];
7635  
7636  	u8         reserved_at_80[0x20];
7637  
7638  	u8         modify_bitmask[0x20];
7639  
7640  	u8         reserved_at_c0[0x40];
7641  
7642  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7643  
7644  	u8         reserved_at_300[0x100];
7645  };
7646  
7647  struct mlx5_ifc_modify_rqt_out_bits {
7648  	u8         status[0x8];
7649  	u8         reserved_at_8[0x18];
7650  
7651  	u8         syndrome[0x20];
7652  
7653  	u8         reserved_at_40[0x40];
7654  };
7655  
7656  struct mlx5_ifc_rqt_bitmask_bits {
7657  	u8	   reserved_at_0[0x20];
7658  
7659  	u8         reserved_at_20[0x1f];
7660  	u8         rqn_list[0x1];
7661  };
7662  
7663  struct mlx5_ifc_modify_rqt_in_bits {
7664  	u8         opcode[0x10];
7665  	u8         uid[0x10];
7666  
7667  	u8         reserved_at_20[0x10];
7668  	u8         op_mod[0x10];
7669  
7670  	u8         reserved_at_40[0x8];
7671  	u8         rqtn[0x18];
7672  
7673  	u8         reserved_at_60[0x20];
7674  
7675  	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7676  
7677  	u8         reserved_at_c0[0x40];
7678  
7679  	struct mlx5_ifc_rqtc_bits ctx;
7680  };
7681  
7682  struct mlx5_ifc_modify_rq_out_bits {
7683  	u8         status[0x8];
7684  	u8         reserved_at_8[0x18];
7685  
7686  	u8         syndrome[0x20];
7687  
7688  	u8         reserved_at_40[0x40];
7689  };
7690  
7691  enum {
7692  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7693  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7694  	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7695  };
7696  
7697  struct mlx5_ifc_modify_rq_in_bits {
7698  	u8         opcode[0x10];
7699  	u8         uid[0x10];
7700  
7701  	u8         reserved_at_20[0x10];
7702  	u8         op_mod[0x10];
7703  
7704  	u8         rq_state[0x4];
7705  	u8         reserved_at_44[0x4];
7706  	u8         rqn[0x18];
7707  
7708  	u8         reserved_at_60[0x20];
7709  
7710  	u8         modify_bitmask[0x40];
7711  
7712  	u8         reserved_at_c0[0x40];
7713  
7714  	struct mlx5_ifc_rqc_bits ctx;
7715  };
7716  
7717  struct mlx5_ifc_modify_rmp_out_bits {
7718  	u8         status[0x8];
7719  	u8         reserved_at_8[0x18];
7720  
7721  	u8         syndrome[0x20];
7722  
7723  	u8         reserved_at_40[0x40];
7724  };
7725  
7726  struct mlx5_ifc_rmp_bitmask_bits {
7727  	u8	   reserved_at_0[0x20];
7728  
7729  	u8         reserved_at_20[0x1f];
7730  	u8         lwm[0x1];
7731  };
7732  
7733  struct mlx5_ifc_modify_rmp_in_bits {
7734  	u8         opcode[0x10];
7735  	u8         uid[0x10];
7736  
7737  	u8         reserved_at_20[0x10];
7738  	u8         op_mod[0x10];
7739  
7740  	u8         rmp_state[0x4];
7741  	u8         reserved_at_44[0x4];
7742  	u8         rmpn[0x18];
7743  
7744  	u8         reserved_at_60[0x20];
7745  
7746  	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7747  
7748  	u8         reserved_at_c0[0x40];
7749  
7750  	struct mlx5_ifc_rmpc_bits ctx;
7751  };
7752  
7753  struct mlx5_ifc_modify_nic_vport_context_out_bits {
7754  	u8         status[0x8];
7755  	u8         reserved_at_8[0x18];
7756  
7757  	u8         syndrome[0x20];
7758  
7759  	u8         reserved_at_40[0x40];
7760  };
7761  
7762  struct mlx5_ifc_modify_nic_vport_field_select_bits {
7763  	u8         reserved_at_0[0x12];
7764  	u8	   affiliation[0x1];
7765  	u8	   reserved_at_13[0x1];
7766  	u8         disable_uc_local_lb[0x1];
7767  	u8         disable_mc_local_lb[0x1];
7768  	u8         node_guid[0x1];
7769  	u8         port_guid[0x1];
7770  	u8         min_inline[0x1];
7771  	u8         mtu[0x1];
7772  	u8         change_event[0x1];
7773  	u8         promisc[0x1];
7774  	u8         permanent_address[0x1];
7775  	u8         addresses_list[0x1];
7776  	u8         roce_en[0x1];
7777  	u8         reserved_at_1f[0x1];
7778  };
7779  
7780  struct mlx5_ifc_modify_nic_vport_context_in_bits {
7781  	u8         opcode[0x10];
7782  	u8         reserved_at_10[0x10];
7783  
7784  	u8         reserved_at_20[0x10];
7785  	u8         op_mod[0x10];
7786  
7787  	u8         other_vport[0x1];
7788  	u8         reserved_at_41[0xf];
7789  	u8         vport_number[0x10];
7790  
7791  	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7792  
7793  	u8         reserved_at_80[0x780];
7794  
7795  	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7796  };
7797  
7798  struct mlx5_ifc_modify_hca_vport_context_out_bits {
7799  	u8         status[0x8];
7800  	u8         reserved_at_8[0x18];
7801  
7802  	u8         syndrome[0x20];
7803  
7804  	u8         reserved_at_40[0x40];
7805  };
7806  
7807  struct mlx5_ifc_modify_hca_vport_context_in_bits {
7808  	u8         opcode[0x10];
7809  	u8         reserved_at_10[0x10];
7810  
7811  	u8         reserved_at_20[0x10];
7812  	u8         op_mod[0x10];
7813  
7814  	u8         other_vport[0x1];
7815  	u8         reserved_at_41[0xb];
7816  	u8         port_num[0x4];
7817  	u8         vport_number[0x10];
7818  
7819  	u8         reserved_at_60[0x20];
7820  
7821  	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7822  };
7823  
7824  struct mlx5_ifc_modify_cq_out_bits {
7825  	u8         status[0x8];
7826  	u8         reserved_at_8[0x18];
7827  
7828  	u8         syndrome[0x20];
7829  
7830  	u8         reserved_at_40[0x40];
7831  };
7832  
7833  enum {
7834  	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7835  	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7836  };
7837  
7838  struct mlx5_ifc_modify_cq_in_bits {
7839  	u8         opcode[0x10];
7840  	u8         uid[0x10];
7841  
7842  	u8         reserved_at_20[0x10];
7843  	u8         op_mod[0x10];
7844  
7845  	u8         reserved_at_40[0x8];
7846  	u8         cqn[0x18];
7847  
7848  	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7849  
7850  	struct mlx5_ifc_cqc_bits cq_context;
7851  
7852  	u8         reserved_at_280[0x60];
7853  
7854  	u8         cq_umem_valid[0x1];
7855  	u8         reserved_at_2e1[0x1f];
7856  
7857  	u8         reserved_at_300[0x580];
7858  
7859  	u8         pas[][0x40];
7860  };
7861  
7862  struct mlx5_ifc_modify_cong_status_out_bits {
7863  	u8         status[0x8];
7864  	u8         reserved_at_8[0x18];
7865  
7866  	u8         syndrome[0x20];
7867  
7868  	u8         reserved_at_40[0x40];
7869  };
7870  
7871  struct mlx5_ifc_modify_cong_status_in_bits {
7872  	u8         opcode[0x10];
7873  	u8         reserved_at_10[0x10];
7874  
7875  	u8         reserved_at_20[0x10];
7876  	u8         op_mod[0x10];
7877  
7878  	u8         reserved_at_40[0x18];
7879  	u8         priority[0x4];
7880  	u8         cong_protocol[0x4];
7881  
7882  	u8         enable[0x1];
7883  	u8         tag_enable[0x1];
7884  	u8         reserved_at_62[0x1e];
7885  };
7886  
7887  struct mlx5_ifc_modify_cong_params_out_bits {
7888  	u8         status[0x8];
7889  	u8         reserved_at_8[0x18];
7890  
7891  	u8         syndrome[0x20];
7892  
7893  	u8         reserved_at_40[0x40];
7894  };
7895  
7896  struct mlx5_ifc_modify_cong_params_in_bits {
7897  	u8         opcode[0x10];
7898  	u8         reserved_at_10[0x10];
7899  
7900  	u8         reserved_at_20[0x10];
7901  	u8         op_mod[0x10];
7902  
7903  	u8         reserved_at_40[0x1c];
7904  	u8         cong_protocol[0x4];
7905  
7906  	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7907  
7908  	u8         reserved_at_80[0x80];
7909  
7910  	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7911  };
7912  
7913  struct mlx5_ifc_manage_pages_out_bits {
7914  	u8         status[0x8];
7915  	u8         reserved_at_8[0x18];
7916  
7917  	u8         syndrome[0x20];
7918  
7919  	u8         output_num_entries[0x20];
7920  
7921  	u8         reserved_at_60[0x20];
7922  
7923  	u8         pas[][0x40];
7924  };
7925  
7926  enum {
7927  	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7928  	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7929  	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7930  };
7931  
7932  struct mlx5_ifc_manage_pages_in_bits {
7933  	u8         opcode[0x10];
7934  	u8         reserved_at_10[0x10];
7935  
7936  	u8         reserved_at_20[0x10];
7937  	u8         op_mod[0x10];
7938  
7939  	u8         embedded_cpu_function[0x1];
7940  	u8         reserved_at_41[0xf];
7941  	u8         function_id[0x10];
7942  
7943  	u8         input_num_entries[0x20];
7944  
7945  	u8         pas[][0x40];
7946  };
7947  
7948  struct mlx5_ifc_mad_ifc_out_bits {
7949  	u8         status[0x8];
7950  	u8         reserved_at_8[0x18];
7951  
7952  	u8         syndrome[0x20];
7953  
7954  	u8         reserved_at_40[0x40];
7955  
7956  	u8         response_mad_packet[256][0x8];
7957  };
7958  
7959  struct mlx5_ifc_mad_ifc_in_bits {
7960  	u8         opcode[0x10];
7961  	u8         reserved_at_10[0x10];
7962  
7963  	u8         reserved_at_20[0x10];
7964  	u8         op_mod[0x10];
7965  
7966  	u8         remote_lid[0x10];
7967  	u8         plane_index[0x8];
7968  	u8         port[0x8];
7969  
7970  	u8         reserved_at_60[0x20];
7971  
7972  	u8         mad[256][0x8];
7973  };
7974  
7975  struct mlx5_ifc_init_hca_out_bits {
7976  	u8         status[0x8];
7977  	u8         reserved_at_8[0x18];
7978  
7979  	u8         syndrome[0x20];
7980  
7981  	u8         reserved_at_40[0x40];
7982  };
7983  
7984  struct mlx5_ifc_init_hca_in_bits {
7985  	u8         opcode[0x10];
7986  	u8         reserved_at_10[0x10];
7987  
7988  	u8         reserved_at_20[0x10];
7989  	u8         op_mod[0x10];
7990  
7991  	u8         reserved_at_40[0x20];
7992  
7993  	u8         reserved_at_60[0x2];
7994  	u8         sw_vhca_id[0xe];
7995  	u8         reserved_at_70[0x10];
7996  
7997  	u8	   sw_owner_id[4][0x20];
7998  };
7999  
8000  struct mlx5_ifc_init2rtr_qp_out_bits {
8001  	u8         status[0x8];
8002  	u8         reserved_at_8[0x18];
8003  
8004  	u8         syndrome[0x20];
8005  
8006  	u8         reserved_at_40[0x20];
8007  	u8         ece[0x20];
8008  };
8009  
8010  struct mlx5_ifc_init2rtr_qp_in_bits {
8011  	u8         opcode[0x10];
8012  	u8         uid[0x10];
8013  
8014  	u8         reserved_at_20[0x10];
8015  	u8         op_mod[0x10];
8016  
8017  	u8         reserved_at_40[0x8];
8018  	u8         qpn[0x18];
8019  
8020  	u8         reserved_at_60[0x20];
8021  
8022  	u8         opt_param_mask[0x20];
8023  
8024  	u8         ece[0x20];
8025  
8026  	struct mlx5_ifc_qpc_bits qpc;
8027  
8028  	u8         reserved_at_800[0x80];
8029  };
8030  
8031  struct mlx5_ifc_init2init_qp_out_bits {
8032  	u8         status[0x8];
8033  	u8         reserved_at_8[0x18];
8034  
8035  	u8         syndrome[0x20];
8036  
8037  	u8         reserved_at_40[0x20];
8038  	u8         ece[0x20];
8039  };
8040  
8041  struct mlx5_ifc_init2init_qp_in_bits {
8042  	u8         opcode[0x10];
8043  	u8         uid[0x10];
8044  
8045  	u8         reserved_at_20[0x10];
8046  	u8         op_mod[0x10];
8047  
8048  	u8         reserved_at_40[0x8];
8049  	u8         qpn[0x18];
8050  
8051  	u8         reserved_at_60[0x20];
8052  
8053  	u8         opt_param_mask[0x20];
8054  
8055  	u8         ece[0x20];
8056  
8057  	struct mlx5_ifc_qpc_bits qpc;
8058  
8059  	u8         reserved_at_800[0x80];
8060  };
8061  
8062  struct mlx5_ifc_get_dropped_packet_log_out_bits {
8063  	u8         status[0x8];
8064  	u8         reserved_at_8[0x18];
8065  
8066  	u8         syndrome[0x20];
8067  
8068  	u8         reserved_at_40[0x40];
8069  
8070  	u8         packet_headers_log[128][0x8];
8071  
8072  	u8         packet_syndrome[64][0x8];
8073  };
8074  
8075  struct mlx5_ifc_get_dropped_packet_log_in_bits {
8076  	u8         opcode[0x10];
8077  	u8         reserved_at_10[0x10];
8078  
8079  	u8         reserved_at_20[0x10];
8080  	u8         op_mod[0x10];
8081  
8082  	u8         reserved_at_40[0x40];
8083  };
8084  
8085  struct mlx5_ifc_gen_eqe_in_bits {
8086  	u8         opcode[0x10];
8087  	u8         reserved_at_10[0x10];
8088  
8089  	u8         reserved_at_20[0x10];
8090  	u8         op_mod[0x10];
8091  
8092  	u8         reserved_at_40[0x18];
8093  	u8         eq_number[0x8];
8094  
8095  	u8         reserved_at_60[0x20];
8096  
8097  	u8         eqe[64][0x8];
8098  };
8099  
8100  struct mlx5_ifc_gen_eq_out_bits {
8101  	u8         status[0x8];
8102  	u8         reserved_at_8[0x18];
8103  
8104  	u8         syndrome[0x20];
8105  
8106  	u8         reserved_at_40[0x40];
8107  };
8108  
8109  struct mlx5_ifc_enable_hca_out_bits {
8110  	u8         status[0x8];
8111  	u8         reserved_at_8[0x18];
8112  
8113  	u8         syndrome[0x20];
8114  
8115  	u8         reserved_at_40[0x20];
8116  };
8117  
8118  struct mlx5_ifc_enable_hca_in_bits {
8119  	u8         opcode[0x10];
8120  	u8         reserved_at_10[0x10];
8121  
8122  	u8         reserved_at_20[0x10];
8123  	u8         op_mod[0x10];
8124  
8125  	u8         embedded_cpu_function[0x1];
8126  	u8         reserved_at_41[0xf];
8127  	u8         function_id[0x10];
8128  
8129  	u8         reserved_at_60[0x20];
8130  };
8131  
8132  struct mlx5_ifc_drain_dct_out_bits {
8133  	u8         status[0x8];
8134  	u8         reserved_at_8[0x18];
8135  
8136  	u8         syndrome[0x20];
8137  
8138  	u8         reserved_at_40[0x40];
8139  };
8140  
8141  struct mlx5_ifc_drain_dct_in_bits {
8142  	u8         opcode[0x10];
8143  	u8         uid[0x10];
8144  
8145  	u8         reserved_at_20[0x10];
8146  	u8         op_mod[0x10];
8147  
8148  	u8         reserved_at_40[0x8];
8149  	u8         dctn[0x18];
8150  
8151  	u8         reserved_at_60[0x20];
8152  };
8153  
8154  struct mlx5_ifc_disable_hca_out_bits {
8155  	u8         status[0x8];
8156  	u8         reserved_at_8[0x18];
8157  
8158  	u8         syndrome[0x20];
8159  
8160  	u8         reserved_at_40[0x20];
8161  };
8162  
8163  struct mlx5_ifc_disable_hca_in_bits {
8164  	u8         opcode[0x10];
8165  	u8         reserved_at_10[0x10];
8166  
8167  	u8         reserved_at_20[0x10];
8168  	u8         op_mod[0x10];
8169  
8170  	u8         embedded_cpu_function[0x1];
8171  	u8         reserved_at_41[0xf];
8172  	u8         function_id[0x10];
8173  
8174  	u8         reserved_at_60[0x20];
8175  };
8176  
8177  struct mlx5_ifc_detach_from_mcg_out_bits {
8178  	u8         status[0x8];
8179  	u8         reserved_at_8[0x18];
8180  
8181  	u8         syndrome[0x20];
8182  
8183  	u8         reserved_at_40[0x40];
8184  };
8185  
8186  struct mlx5_ifc_detach_from_mcg_in_bits {
8187  	u8         opcode[0x10];
8188  	u8         uid[0x10];
8189  
8190  	u8         reserved_at_20[0x10];
8191  	u8         op_mod[0x10];
8192  
8193  	u8         reserved_at_40[0x8];
8194  	u8         qpn[0x18];
8195  
8196  	u8         reserved_at_60[0x20];
8197  
8198  	u8         multicast_gid[16][0x8];
8199  };
8200  
8201  struct mlx5_ifc_destroy_xrq_out_bits {
8202  	u8         status[0x8];
8203  	u8         reserved_at_8[0x18];
8204  
8205  	u8         syndrome[0x20];
8206  
8207  	u8         reserved_at_40[0x40];
8208  };
8209  
8210  struct mlx5_ifc_destroy_xrq_in_bits {
8211  	u8         opcode[0x10];
8212  	u8         uid[0x10];
8213  
8214  	u8         reserved_at_20[0x10];
8215  	u8         op_mod[0x10];
8216  
8217  	u8         reserved_at_40[0x8];
8218  	u8         xrqn[0x18];
8219  
8220  	u8         reserved_at_60[0x20];
8221  };
8222  
8223  struct mlx5_ifc_destroy_xrc_srq_out_bits {
8224  	u8         status[0x8];
8225  	u8         reserved_at_8[0x18];
8226  
8227  	u8         syndrome[0x20];
8228  
8229  	u8         reserved_at_40[0x40];
8230  };
8231  
8232  struct mlx5_ifc_destroy_xrc_srq_in_bits {
8233  	u8         opcode[0x10];
8234  	u8         uid[0x10];
8235  
8236  	u8         reserved_at_20[0x10];
8237  	u8         op_mod[0x10];
8238  
8239  	u8         reserved_at_40[0x8];
8240  	u8         xrc_srqn[0x18];
8241  
8242  	u8         reserved_at_60[0x20];
8243  };
8244  
8245  struct mlx5_ifc_destroy_tis_out_bits {
8246  	u8         status[0x8];
8247  	u8         reserved_at_8[0x18];
8248  
8249  	u8         syndrome[0x20];
8250  
8251  	u8         reserved_at_40[0x40];
8252  };
8253  
8254  struct mlx5_ifc_destroy_tis_in_bits {
8255  	u8         opcode[0x10];
8256  	u8         uid[0x10];
8257  
8258  	u8         reserved_at_20[0x10];
8259  	u8         op_mod[0x10];
8260  
8261  	u8         reserved_at_40[0x8];
8262  	u8         tisn[0x18];
8263  
8264  	u8         reserved_at_60[0x20];
8265  };
8266  
8267  struct mlx5_ifc_destroy_tir_out_bits {
8268  	u8         status[0x8];
8269  	u8         reserved_at_8[0x18];
8270  
8271  	u8         syndrome[0x20];
8272  
8273  	u8         reserved_at_40[0x40];
8274  };
8275  
8276  struct mlx5_ifc_destroy_tir_in_bits {
8277  	u8         opcode[0x10];
8278  	u8         uid[0x10];
8279  
8280  	u8         reserved_at_20[0x10];
8281  	u8         op_mod[0x10];
8282  
8283  	u8         reserved_at_40[0x8];
8284  	u8         tirn[0x18];
8285  
8286  	u8         reserved_at_60[0x20];
8287  };
8288  
8289  struct mlx5_ifc_destroy_srq_out_bits {
8290  	u8         status[0x8];
8291  	u8         reserved_at_8[0x18];
8292  
8293  	u8         syndrome[0x20];
8294  
8295  	u8         reserved_at_40[0x40];
8296  };
8297  
8298  struct mlx5_ifc_destroy_srq_in_bits {
8299  	u8         opcode[0x10];
8300  	u8         uid[0x10];
8301  
8302  	u8         reserved_at_20[0x10];
8303  	u8         op_mod[0x10];
8304  
8305  	u8         reserved_at_40[0x8];
8306  	u8         srqn[0x18];
8307  
8308  	u8         reserved_at_60[0x20];
8309  };
8310  
8311  struct mlx5_ifc_destroy_sq_out_bits {
8312  	u8         status[0x8];
8313  	u8         reserved_at_8[0x18];
8314  
8315  	u8         syndrome[0x20];
8316  
8317  	u8         reserved_at_40[0x40];
8318  };
8319  
8320  struct mlx5_ifc_destroy_sq_in_bits {
8321  	u8         opcode[0x10];
8322  	u8         uid[0x10];
8323  
8324  	u8         reserved_at_20[0x10];
8325  	u8         op_mod[0x10];
8326  
8327  	u8         reserved_at_40[0x8];
8328  	u8         sqn[0x18];
8329  
8330  	u8         reserved_at_60[0x20];
8331  };
8332  
8333  struct mlx5_ifc_destroy_scheduling_element_out_bits {
8334  	u8         status[0x8];
8335  	u8         reserved_at_8[0x18];
8336  
8337  	u8         syndrome[0x20];
8338  
8339  	u8         reserved_at_40[0x1c0];
8340  };
8341  
8342  struct mlx5_ifc_destroy_scheduling_element_in_bits {
8343  	u8         opcode[0x10];
8344  	u8         reserved_at_10[0x10];
8345  
8346  	u8         reserved_at_20[0x10];
8347  	u8         op_mod[0x10];
8348  
8349  	u8         scheduling_hierarchy[0x8];
8350  	u8         reserved_at_48[0x18];
8351  
8352  	u8         scheduling_element_id[0x20];
8353  
8354  	u8         reserved_at_80[0x180];
8355  };
8356  
8357  struct mlx5_ifc_destroy_rqt_out_bits {
8358  	u8         status[0x8];
8359  	u8         reserved_at_8[0x18];
8360  
8361  	u8         syndrome[0x20];
8362  
8363  	u8         reserved_at_40[0x40];
8364  };
8365  
8366  struct mlx5_ifc_destroy_rqt_in_bits {
8367  	u8         opcode[0x10];
8368  	u8         uid[0x10];
8369  
8370  	u8         reserved_at_20[0x10];
8371  	u8         op_mod[0x10];
8372  
8373  	u8         reserved_at_40[0x8];
8374  	u8         rqtn[0x18];
8375  
8376  	u8         reserved_at_60[0x20];
8377  };
8378  
8379  struct mlx5_ifc_destroy_rq_out_bits {
8380  	u8         status[0x8];
8381  	u8         reserved_at_8[0x18];
8382  
8383  	u8         syndrome[0x20];
8384  
8385  	u8         reserved_at_40[0x40];
8386  };
8387  
8388  struct mlx5_ifc_destroy_rq_in_bits {
8389  	u8         opcode[0x10];
8390  	u8         uid[0x10];
8391  
8392  	u8         reserved_at_20[0x10];
8393  	u8         op_mod[0x10];
8394  
8395  	u8         reserved_at_40[0x8];
8396  	u8         rqn[0x18];
8397  
8398  	u8         reserved_at_60[0x20];
8399  };
8400  
8401  struct mlx5_ifc_set_delay_drop_params_in_bits {
8402  	u8         opcode[0x10];
8403  	u8         reserved_at_10[0x10];
8404  
8405  	u8         reserved_at_20[0x10];
8406  	u8         op_mod[0x10];
8407  
8408  	u8         reserved_at_40[0x20];
8409  
8410  	u8         reserved_at_60[0x10];
8411  	u8         delay_drop_timeout[0x10];
8412  };
8413  
8414  struct mlx5_ifc_set_delay_drop_params_out_bits {
8415  	u8         status[0x8];
8416  	u8         reserved_at_8[0x18];
8417  
8418  	u8         syndrome[0x20];
8419  
8420  	u8         reserved_at_40[0x40];
8421  };
8422  
8423  struct mlx5_ifc_destroy_rmp_out_bits {
8424  	u8         status[0x8];
8425  	u8         reserved_at_8[0x18];
8426  
8427  	u8         syndrome[0x20];
8428  
8429  	u8         reserved_at_40[0x40];
8430  };
8431  
8432  struct mlx5_ifc_destroy_rmp_in_bits {
8433  	u8         opcode[0x10];
8434  	u8         uid[0x10];
8435  
8436  	u8         reserved_at_20[0x10];
8437  	u8         op_mod[0x10];
8438  
8439  	u8         reserved_at_40[0x8];
8440  	u8         rmpn[0x18];
8441  
8442  	u8         reserved_at_60[0x20];
8443  };
8444  
8445  struct mlx5_ifc_destroy_qp_out_bits {
8446  	u8         status[0x8];
8447  	u8         reserved_at_8[0x18];
8448  
8449  	u8         syndrome[0x20];
8450  
8451  	u8         reserved_at_40[0x40];
8452  };
8453  
8454  struct mlx5_ifc_destroy_qp_in_bits {
8455  	u8         opcode[0x10];
8456  	u8         uid[0x10];
8457  
8458  	u8         reserved_at_20[0x10];
8459  	u8         op_mod[0x10];
8460  
8461  	u8         reserved_at_40[0x8];
8462  	u8         qpn[0x18];
8463  
8464  	u8         reserved_at_60[0x20];
8465  };
8466  
8467  struct mlx5_ifc_destroy_psv_out_bits {
8468  	u8         status[0x8];
8469  	u8         reserved_at_8[0x18];
8470  
8471  	u8         syndrome[0x20];
8472  
8473  	u8         reserved_at_40[0x40];
8474  };
8475  
8476  struct mlx5_ifc_destroy_psv_in_bits {
8477  	u8         opcode[0x10];
8478  	u8         reserved_at_10[0x10];
8479  
8480  	u8         reserved_at_20[0x10];
8481  	u8         op_mod[0x10];
8482  
8483  	u8         reserved_at_40[0x8];
8484  	u8         psvn[0x18];
8485  
8486  	u8         reserved_at_60[0x20];
8487  };
8488  
8489  struct mlx5_ifc_destroy_mkey_out_bits {
8490  	u8         status[0x8];
8491  	u8         reserved_at_8[0x18];
8492  
8493  	u8         syndrome[0x20];
8494  
8495  	u8         reserved_at_40[0x40];
8496  };
8497  
8498  struct mlx5_ifc_destroy_mkey_in_bits {
8499  	u8         opcode[0x10];
8500  	u8         uid[0x10];
8501  
8502  	u8         reserved_at_20[0x10];
8503  	u8         op_mod[0x10];
8504  
8505  	u8         reserved_at_40[0x8];
8506  	u8         mkey_index[0x18];
8507  
8508  	u8         reserved_at_60[0x20];
8509  };
8510  
8511  struct mlx5_ifc_destroy_flow_table_out_bits {
8512  	u8         status[0x8];
8513  	u8         reserved_at_8[0x18];
8514  
8515  	u8         syndrome[0x20];
8516  
8517  	u8         reserved_at_40[0x40];
8518  };
8519  
8520  struct mlx5_ifc_destroy_flow_table_in_bits {
8521  	u8         opcode[0x10];
8522  	u8         reserved_at_10[0x10];
8523  
8524  	u8         reserved_at_20[0x10];
8525  	u8         op_mod[0x10];
8526  
8527  	u8         other_vport[0x1];
8528  	u8         reserved_at_41[0xf];
8529  	u8         vport_number[0x10];
8530  
8531  	u8         reserved_at_60[0x20];
8532  
8533  	u8         table_type[0x8];
8534  	u8         reserved_at_88[0x18];
8535  
8536  	u8         reserved_at_a0[0x8];
8537  	u8         table_id[0x18];
8538  
8539  	u8         reserved_at_c0[0x140];
8540  };
8541  
8542  struct mlx5_ifc_destroy_flow_group_out_bits {
8543  	u8         status[0x8];
8544  	u8         reserved_at_8[0x18];
8545  
8546  	u8         syndrome[0x20];
8547  
8548  	u8         reserved_at_40[0x40];
8549  };
8550  
8551  struct mlx5_ifc_destroy_flow_group_in_bits {
8552  	u8         opcode[0x10];
8553  	u8         reserved_at_10[0x10];
8554  
8555  	u8         reserved_at_20[0x10];
8556  	u8         op_mod[0x10];
8557  
8558  	u8         other_vport[0x1];
8559  	u8         reserved_at_41[0xf];
8560  	u8         vport_number[0x10];
8561  
8562  	u8         reserved_at_60[0x20];
8563  
8564  	u8         table_type[0x8];
8565  	u8         reserved_at_88[0x18];
8566  
8567  	u8         reserved_at_a0[0x8];
8568  	u8         table_id[0x18];
8569  
8570  	u8         group_id[0x20];
8571  
8572  	u8         reserved_at_e0[0x120];
8573  };
8574  
8575  struct mlx5_ifc_destroy_eq_out_bits {
8576  	u8         status[0x8];
8577  	u8         reserved_at_8[0x18];
8578  
8579  	u8         syndrome[0x20];
8580  
8581  	u8         reserved_at_40[0x40];
8582  };
8583  
8584  struct mlx5_ifc_destroy_eq_in_bits {
8585  	u8         opcode[0x10];
8586  	u8         reserved_at_10[0x10];
8587  
8588  	u8         reserved_at_20[0x10];
8589  	u8         op_mod[0x10];
8590  
8591  	u8         reserved_at_40[0x18];
8592  	u8         eq_number[0x8];
8593  
8594  	u8         reserved_at_60[0x20];
8595  };
8596  
8597  struct mlx5_ifc_destroy_dct_out_bits {
8598  	u8         status[0x8];
8599  	u8         reserved_at_8[0x18];
8600  
8601  	u8         syndrome[0x20];
8602  
8603  	u8         reserved_at_40[0x40];
8604  };
8605  
8606  struct mlx5_ifc_destroy_dct_in_bits {
8607  	u8         opcode[0x10];
8608  	u8         uid[0x10];
8609  
8610  	u8         reserved_at_20[0x10];
8611  	u8         op_mod[0x10];
8612  
8613  	u8         reserved_at_40[0x8];
8614  	u8         dctn[0x18];
8615  
8616  	u8         reserved_at_60[0x20];
8617  };
8618  
8619  struct mlx5_ifc_destroy_cq_out_bits {
8620  	u8         status[0x8];
8621  	u8         reserved_at_8[0x18];
8622  
8623  	u8         syndrome[0x20];
8624  
8625  	u8         reserved_at_40[0x40];
8626  };
8627  
8628  struct mlx5_ifc_destroy_cq_in_bits {
8629  	u8         opcode[0x10];
8630  	u8         uid[0x10];
8631  
8632  	u8         reserved_at_20[0x10];
8633  	u8         op_mod[0x10];
8634  
8635  	u8         reserved_at_40[0x8];
8636  	u8         cqn[0x18];
8637  
8638  	u8         reserved_at_60[0x20];
8639  };
8640  
8641  struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8642  	u8         status[0x8];
8643  	u8         reserved_at_8[0x18];
8644  
8645  	u8         syndrome[0x20];
8646  
8647  	u8         reserved_at_40[0x40];
8648  };
8649  
8650  struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8651  	u8         opcode[0x10];
8652  	u8         reserved_at_10[0x10];
8653  
8654  	u8         reserved_at_20[0x10];
8655  	u8         op_mod[0x10];
8656  
8657  	u8         reserved_at_40[0x20];
8658  
8659  	u8         reserved_at_60[0x10];
8660  	u8         vxlan_udp_port[0x10];
8661  };
8662  
8663  struct mlx5_ifc_delete_l2_table_entry_out_bits {
8664  	u8         status[0x8];
8665  	u8         reserved_at_8[0x18];
8666  
8667  	u8         syndrome[0x20];
8668  
8669  	u8         reserved_at_40[0x40];
8670  };
8671  
8672  struct mlx5_ifc_delete_l2_table_entry_in_bits {
8673  	u8         opcode[0x10];
8674  	u8         reserved_at_10[0x10];
8675  
8676  	u8         reserved_at_20[0x10];
8677  	u8         op_mod[0x10];
8678  
8679  	u8         reserved_at_40[0x60];
8680  
8681  	u8         reserved_at_a0[0x8];
8682  	u8         table_index[0x18];
8683  
8684  	u8         reserved_at_c0[0x140];
8685  };
8686  
8687  struct mlx5_ifc_delete_fte_out_bits {
8688  	u8         status[0x8];
8689  	u8         reserved_at_8[0x18];
8690  
8691  	u8         syndrome[0x20];
8692  
8693  	u8         reserved_at_40[0x40];
8694  };
8695  
8696  struct mlx5_ifc_delete_fte_in_bits {
8697  	u8         opcode[0x10];
8698  	u8         reserved_at_10[0x10];
8699  
8700  	u8         reserved_at_20[0x10];
8701  	u8         op_mod[0x10];
8702  
8703  	u8         other_vport[0x1];
8704  	u8         reserved_at_41[0xf];
8705  	u8         vport_number[0x10];
8706  
8707  	u8         reserved_at_60[0x20];
8708  
8709  	u8         table_type[0x8];
8710  	u8         reserved_at_88[0x18];
8711  
8712  	u8         reserved_at_a0[0x8];
8713  	u8         table_id[0x18];
8714  
8715  	u8         reserved_at_c0[0x40];
8716  
8717  	u8         flow_index[0x20];
8718  
8719  	u8         reserved_at_120[0xe0];
8720  };
8721  
8722  struct mlx5_ifc_dealloc_xrcd_out_bits {
8723  	u8         status[0x8];
8724  	u8         reserved_at_8[0x18];
8725  
8726  	u8         syndrome[0x20];
8727  
8728  	u8         reserved_at_40[0x40];
8729  };
8730  
8731  struct mlx5_ifc_dealloc_xrcd_in_bits {
8732  	u8         opcode[0x10];
8733  	u8         uid[0x10];
8734  
8735  	u8         reserved_at_20[0x10];
8736  	u8         op_mod[0x10];
8737  
8738  	u8         reserved_at_40[0x8];
8739  	u8         xrcd[0x18];
8740  
8741  	u8         reserved_at_60[0x20];
8742  };
8743  
8744  struct mlx5_ifc_dealloc_uar_out_bits {
8745  	u8         status[0x8];
8746  	u8         reserved_at_8[0x18];
8747  
8748  	u8         syndrome[0x20];
8749  
8750  	u8         reserved_at_40[0x40];
8751  };
8752  
8753  struct mlx5_ifc_dealloc_uar_in_bits {
8754  	u8         opcode[0x10];
8755  	u8         uid[0x10];
8756  
8757  	u8         reserved_at_20[0x10];
8758  	u8         op_mod[0x10];
8759  
8760  	u8         reserved_at_40[0x8];
8761  	u8         uar[0x18];
8762  
8763  	u8         reserved_at_60[0x20];
8764  };
8765  
8766  struct mlx5_ifc_dealloc_transport_domain_out_bits {
8767  	u8         status[0x8];
8768  	u8         reserved_at_8[0x18];
8769  
8770  	u8         syndrome[0x20];
8771  
8772  	u8         reserved_at_40[0x40];
8773  };
8774  
8775  struct mlx5_ifc_dealloc_transport_domain_in_bits {
8776  	u8         opcode[0x10];
8777  	u8         uid[0x10];
8778  
8779  	u8         reserved_at_20[0x10];
8780  	u8         op_mod[0x10];
8781  
8782  	u8         reserved_at_40[0x8];
8783  	u8         transport_domain[0x18];
8784  
8785  	u8         reserved_at_60[0x20];
8786  };
8787  
8788  struct mlx5_ifc_dealloc_q_counter_out_bits {
8789  	u8         status[0x8];
8790  	u8         reserved_at_8[0x18];
8791  
8792  	u8         syndrome[0x20];
8793  
8794  	u8         reserved_at_40[0x40];
8795  };
8796  
8797  struct mlx5_ifc_dealloc_q_counter_in_bits {
8798  	u8         opcode[0x10];
8799  	u8         reserved_at_10[0x10];
8800  
8801  	u8         reserved_at_20[0x10];
8802  	u8         op_mod[0x10];
8803  
8804  	u8         reserved_at_40[0x18];
8805  	u8         counter_set_id[0x8];
8806  
8807  	u8         reserved_at_60[0x20];
8808  };
8809  
8810  struct mlx5_ifc_dealloc_pd_out_bits {
8811  	u8         status[0x8];
8812  	u8         reserved_at_8[0x18];
8813  
8814  	u8         syndrome[0x20];
8815  
8816  	u8         reserved_at_40[0x40];
8817  };
8818  
8819  struct mlx5_ifc_dealloc_pd_in_bits {
8820  	u8         opcode[0x10];
8821  	u8         uid[0x10];
8822  
8823  	u8         reserved_at_20[0x10];
8824  	u8         op_mod[0x10];
8825  
8826  	u8         reserved_at_40[0x8];
8827  	u8         pd[0x18];
8828  
8829  	u8         reserved_at_60[0x20];
8830  };
8831  
8832  struct mlx5_ifc_dealloc_flow_counter_out_bits {
8833  	u8         status[0x8];
8834  	u8         reserved_at_8[0x18];
8835  
8836  	u8         syndrome[0x20];
8837  
8838  	u8         reserved_at_40[0x40];
8839  };
8840  
8841  struct mlx5_ifc_dealloc_flow_counter_in_bits {
8842  	u8         opcode[0x10];
8843  	u8         reserved_at_10[0x10];
8844  
8845  	u8         reserved_at_20[0x10];
8846  	u8         op_mod[0x10];
8847  
8848  	u8         flow_counter_id[0x20];
8849  
8850  	u8         reserved_at_60[0x20];
8851  };
8852  
8853  struct mlx5_ifc_create_xrq_out_bits {
8854  	u8         status[0x8];
8855  	u8         reserved_at_8[0x18];
8856  
8857  	u8         syndrome[0x20];
8858  
8859  	u8         reserved_at_40[0x8];
8860  	u8         xrqn[0x18];
8861  
8862  	u8         reserved_at_60[0x20];
8863  };
8864  
8865  struct mlx5_ifc_create_xrq_in_bits {
8866  	u8         opcode[0x10];
8867  	u8         uid[0x10];
8868  
8869  	u8         reserved_at_20[0x10];
8870  	u8         op_mod[0x10];
8871  
8872  	u8         reserved_at_40[0x40];
8873  
8874  	struct mlx5_ifc_xrqc_bits xrq_context;
8875  };
8876  
8877  struct mlx5_ifc_create_xrc_srq_out_bits {
8878  	u8         status[0x8];
8879  	u8         reserved_at_8[0x18];
8880  
8881  	u8         syndrome[0x20];
8882  
8883  	u8         reserved_at_40[0x8];
8884  	u8         xrc_srqn[0x18];
8885  
8886  	u8         reserved_at_60[0x20];
8887  };
8888  
8889  struct mlx5_ifc_create_xrc_srq_in_bits {
8890  	u8         opcode[0x10];
8891  	u8         uid[0x10];
8892  
8893  	u8         reserved_at_20[0x10];
8894  	u8         op_mod[0x10];
8895  
8896  	u8         reserved_at_40[0x40];
8897  
8898  	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8899  
8900  	u8         reserved_at_280[0x60];
8901  
8902  	u8         xrc_srq_umem_valid[0x1];
8903  	u8         reserved_at_2e1[0x1f];
8904  
8905  	u8         reserved_at_300[0x580];
8906  
8907  	u8         pas[][0x40];
8908  };
8909  
8910  struct mlx5_ifc_create_tis_out_bits {
8911  	u8         status[0x8];
8912  	u8         reserved_at_8[0x18];
8913  
8914  	u8         syndrome[0x20];
8915  
8916  	u8         reserved_at_40[0x8];
8917  	u8         tisn[0x18];
8918  
8919  	u8         reserved_at_60[0x20];
8920  };
8921  
8922  struct mlx5_ifc_create_tis_in_bits {
8923  	u8         opcode[0x10];
8924  	u8         uid[0x10];
8925  
8926  	u8         reserved_at_20[0x10];
8927  	u8         op_mod[0x10];
8928  
8929  	u8         reserved_at_40[0xc0];
8930  
8931  	struct mlx5_ifc_tisc_bits ctx;
8932  };
8933  
8934  struct mlx5_ifc_create_tir_out_bits {
8935  	u8         status[0x8];
8936  	u8         icm_address_63_40[0x18];
8937  
8938  	u8         syndrome[0x20];
8939  
8940  	u8         icm_address_39_32[0x8];
8941  	u8         tirn[0x18];
8942  
8943  	u8         icm_address_31_0[0x20];
8944  };
8945  
8946  struct mlx5_ifc_create_tir_in_bits {
8947  	u8         opcode[0x10];
8948  	u8         uid[0x10];
8949  
8950  	u8         reserved_at_20[0x10];
8951  	u8         op_mod[0x10];
8952  
8953  	u8         reserved_at_40[0xc0];
8954  
8955  	struct mlx5_ifc_tirc_bits ctx;
8956  };
8957  
8958  struct mlx5_ifc_create_srq_out_bits {
8959  	u8         status[0x8];
8960  	u8         reserved_at_8[0x18];
8961  
8962  	u8         syndrome[0x20];
8963  
8964  	u8         reserved_at_40[0x8];
8965  	u8         srqn[0x18];
8966  
8967  	u8         reserved_at_60[0x20];
8968  };
8969  
8970  struct mlx5_ifc_create_srq_in_bits {
8971  	u8         opcode[0x10];
8972  	u8         uid[0x10];
8973  
8974  	u8         reserved_at_20[0x10];
8975  	u8         op_mod[0x10];
8976  
8977  	u8         reserved_at_40[0x40];
8978  
8979  	struct mlx5_ifc_srqc_bits srq_context_entry;
8980  
8981  	u8         reserved_at_280[0x600];
8982  
8983  	u8         pas[][0x40];
8984  };
8985  
8986  struct mlx5_ifc_create_sq_out_bits {
8987  	u8         status[0x8];
8988  	u8         reserved_at_8[0x18];
8989  
8990  	u8         syndrome[0x20];
8991  
8992  	u8         reserved_at_40[0x8];
8993  	u8         sqn[0x18];
8994  
8995  	u8         reserved_at_60[0x20];
8996  };
8997  
8998  struct mlx5_ifc_create_sq_in_bits {
8999  	u8         opcode[0x10];
9000  	u8         uid[0x10];
9001  
9002  	u8         reserved_at_20[0x10];
9003  	u8         op_mod[0x10];
9004  
9005  	u8         reserved_at_40[0xc0];
9006  
9007  	struct mlx5_ifc_sqc_bits ctx;
9008  };
9009  
9010  struct mlx5_ifc_create_scheduling_element_out_bits {
9011  	u8         status[0x8];
9012  	u8         reserved_at_8[0x18];
9013  
9014  	u8         syndrome[0x20];
9015  
9016  	u8         reserved_at_40[0x40];
9017  
9018  	u8         scheduling_element_id[0x20];
9019  
9020  	u8         reserved_at_a0[0x160];
9021  };
9022  
9023  struct mlx5_ifc_create_scheduling_element_in_bits {
9024  	u8         opcode[0x10];
9025  	u8         reserved_at_10[0x10];
9026  
9027  	u8         reserved_at_20[0x10];
9028  	u8         op_mod[0x10];
9029  
9030  	u8         scheduling_hierarchy[0x8];
9031  	u8         reserved_at_48[0x18];
9032  
9033  	u8         reserved_at_60[0xa0];
9034  
9035  	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9036  
9037  	u8         reserved_at_300[0x100];
9038  };
9039  
9040  struct mlx5_ifc_create_rqt_out_bits {
9041  	u8         status[0x8];
9042  	u8         reserved_at_8[0x18];
9043  
9044  	u8         syndrome[0x20];
9045  
9046  	u8         reserved_at_40[0x8];
9047  	u8         rqtn[0x18];
9048  
9049  	u8         reserved_at_60[0x20];
9050  };
9051  
9052  struct mlx5_ifc_create_rqt_in_bits {
9053  	u8         opcode[0x10];
9054  	u8         uid[0x10];
9055  
9056  	u8         reserved_at_20[0x10];
9057  	u8         op_mod[0x10];
9058  
9059  	u8         reserved_at_40[0xc0];
9060  
9061  	struct mlx5_ifc_rqtc_bits rqt_context;
9062  };
9063  
9064  struct mlx5_ifc_create_rq_out_bits {
9065  	u8         status[0x8];
9066  	u8         reserved_at_8[0x18];
9067  
9068  	u8         syndrome[0x20];
9069  
9070  	u8         reserved_at_40[0x8];
9071  	u8         rqn[0x18];
9072  
9073  	u8         reserved_at_60[0x20];
9074  };
9075  
9076  struct mlx5_ifc_create_rq_in_bits {
9077  	u8         opcode[0x10];
9078  	u8         uid[0x10];
9079  
9080  	u8         reserved_at_20[0x10];
9081  	u8         op_mod[0x10];
9082  
9083  	u8         reserved_at_40[0xc0];
9084  
9085  	struct mlx5_ifc_rqc_bits ctx;
9086  };
9087  
9088  struct mlx5_ifc_create_rmp_out_bits {
9089  	u8         status[0x8];
9090  	u8         reserved_at_8[0x18];
9091  
9092  	u8         syndrome[0x20];
9093  
9094  	u8         reserved_at_40[0x8];
9095  	u8         rmpn[0x18];
9096  
9097  	u8         reserved_at_60[0x20];
9098  };
9099  
9100  struct mlx5_ifc_create_rmp_in_bits {
9101  	u8         opcode[0x10];
9102  	u8         uid[0x10];
9103  
9104  	u8         reserved_at_20[0x10];
9105  	u8         op_mod[0x10];
9106  
9107  	u8         reserved_at_40[0xc0];
9108  
9109  	struct mlx5_ifc_rmpc_bits ctx;
9110  };
9111  
9112  struct mlx5_ifc_create_qp_out_bits {
9113  	u8         status[0x8];
9114  	u8         reserved_at_8[0x18];
9115  
9116  	u8         syndrome[0x20];
9117  
9118  	u8         reserved_at_40[0x8];
9119  	u8         qpn[0x18];
9120  
9121  	u8         ece[0x20];
9122  };
9123  
9124  struct mlx5_ifc_create_qp_in_bits {
9125  	u8         opcode[0x10];
9126  	u8         uid[0x10];
9127  
9128  	u8         reserved_at_20[0x10];
9129  	u8         op_mod[0x10];
9130  
9131  	u8         qpc_ext[0x1];
9132  	u8         reserved_at_41[0x7];
9133  	u8         input_qpn[0x18];
9134  
9135  	u8         reserved_at_60[0x20];
9136  	u8         opt_param_mask[0x20];
9137  
9138  	u8         ece[0x20];
9139  
9140  	struct mlx5_ifc_qpc_bits qpc;
9141  
9142  	u8         wq_umem_offset[0x40];
9143  
9144  	u8         wq_umem_id[0x20];
9145  
9146  	u8         wq_umem_valid[0x1];
9147  	u8         reserved_at_861[0x1f];
9148  
9149  	u8         pas[][0x40];
9150  };
9151  
9152  struct mlx5_ifc_create_psv_out_bits {
9153  	u8         status[0x8];
9154  	u8         reserved_at_8[0x18];
9155  
9156  	u8         syndrome[0x20];
9157  
9158  	u8         reserved_at_40[0x40];
9159  
9160  	u8         reserved_at_80[0x8];
9161  	u8         psv0_index[0x18];
9162  
9163  	u8         reserved_at_a0[0x8];
9164  	u8         psv1_index[0x18];
9165  
9166  	u8         reserved_at_c0[0x8];
9167  	u8         psv2_index[0x18];
9168  
9169  	u8         reserved_at_e0[0x8];
9170  	u8         psv3_index[0x18];
9171  };
9172  
9173  struct mlx5_ifc_create_psv_in_bits {
9174  	u8         opcode[0x10];
9175  	u8         reserved_at_10[0x10];
9176  
9177  	u8         reserved_at_20[0x10];
9178  	u8         op_mod[0x10];
9179  
9180  	u8         num_psv[0x4];
9181  	u8         reserved_at_44[0x4];
9182  	u8         pd[0x18];
9183  
9184  	u8         reserved_at_60[0x20];
9185  };
9186  
9187  struct mlx5_ifc_create_mkey_out_bits {
9188  	u8         status[0x8];
9189  	u8         reserved_at_8[0x18];
9190  
9191  	u8         syndrome[0x20];
9192  
9193  	u8         reserved_at_40[0x8];
9194  	u8         mkey_index[0x18];
9195  
9196  	u8         reserved_at_60[0x20];
9197  };
9198  
9199  struct mlx5_ifc_create_mkey_in_bits {
9200  	u8         opcode[0x10];
9201  	u8         uid[0x10];
9202  
9203  	u8         reserved_at_20[0x10];
9204  	u8         op_mod[0x10];
9205  
9206  	u8         reserved_at_40[0x20];
9207  
9208  	u8         pg_access[0x1];
9209  	u8         mkey_umem_valid[0x1];
9210  	u8         data_direct[0x1];
9211  	u8         reserved_at_63[0x1d];
9212  
9213  	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9214  
9215  	u8         reserved_at_280[0x80];
9216  
9217  	u8         translations_octword_actual_size[0x20];
9218  
9219  	u8         reserved_at_320[0x560];
9220  
9221  	u8         klm_pas_mtt[][0x20];
9222  };
9223  
9224  enum {
9225  	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9226  	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9227  	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9228  	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9229  	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9230  	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9231  	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9232  };
9233  
9234  struct mlx5_ifc_create_flow_table_out_bits {
9235  	u8         status[0x8];
9236  	u8         icm_address_63_40[0x18];
9237  
9238  	u8         syndrome[0x20];
9239  
9240  	u8         icm_address_39_32[0x8];
9241  	u8         table_id[0x18];
9242  
9243  	u8         icm_address_31_0[0x20];
9244  };
9245  
9246  struct mlx5_ifc_create_flow_table_in_bits {
9247  	u8         opcode[0x10];
9248  	u8         uid[0x10];
9249  
9250  	u8         reserved_at_20[0x10];
9251  	u8         op_mod[0x10];
9252  
9253  	u8         other_vport[0x1];
9254  	u8         reserved_at_41[0xf];
9255  	u8         vport_number[0x10];
9256  
9257  	u8         reserved_at_60[0x20];
9258  
9259  	u8         table_type[0x8];
9260  	u8         reserved_at_88[0x18];
9261  
9262  	u8         reserved_at_a0[0x20];
9263  
9264  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9265  };
9266  
9267  struct mlx5_ifc_create_flow_group_out_bits {
9268  	u8         status[0x8];
9269  	u8         reserved_at_8[0x18];
9270  
9271  	u8         syndrome[0x20];
9272  
9273  	u8         reserved_at_40[0x8];
9274  	u8         group_id[0x18];
9275  
9276  	u8         reserved_at_60[0x20];
9277  };
9278  
9279  enum {
9280  	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9281  	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9282  };
9283  
9284  enum {
9285  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9286  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9287  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9288  	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9289  };
9290  
9291  struct mlx5_ifc_create_flow_group_in_bits {
9292  	u8         opcode[0x10];
9293  	u8         reserved_at_10[0x10];
9294  
9295  	u8         reserved_at_20[0x10];
9296  	u8         op_mod[0x10];
9297  
9298  	u8         other_vport[0x1];
9299  	u8         reserved_at_41[0xf];
9300  	u8         vport_number[0x10];
9301  
9302  	u8         reserved_at_60[0x20];
9303  
9304  	u8         table_type[0x8];
9305  	u8         reserved_at_88[0x4];
9306  	u8         group_type[0x4];
9307  	u8         reserved_at_90[0x10];
9308  
9309  	u8         reserved_at_a0[0x8];
9310  	u8         table_id[0x18];
9311  
9312  	u8         source_eswitch_owner_vhca_id_valid[0x1];
9313  
9314  	u8         reserved_at_c1[0x1f];
9315  
9316  	u8         start_flow_index[0x20];
9317  
9318  	u8         reserved_at_100[0x20];
9319  
9320  	u8         end_flow_index[0x20];
9321  
9322  	u8         reserved_at_140[0x10];
9323  	u8         match_definer_id[0x10];
9324  
9325  	u8         reserved_at_160[0x80];
9326  
9327  	u8         reserved_at_1e0[0x18];
9328  	u8         match_criteria_enable[0x8];
9329  
9330  	struct mlx5_ifc_fte_match_param_bits match_criteria;
9331  
9332  	u8         reserved_at_1200[0xe00];
9333  };
9334  
9335  struct mlx5_ifc_create_eq_out_bits {
9336  	u8         status[0x8];
9337  	u8         reserved_at_8[0x18];
9338  
9339  	u8         syndrome[0x20];
9340  
9341  	u8         reserved_at_40[0x18];
9342  	u8         eq_number[0x8];
9343  
9344  	u8         reserved_at_60[0x20];
9345  };
9346  
9347  struct mlx5_ifc_create_eq_in_bits {
9348  	u8         opcode[0x10];
9349  	u8         uid[0x10];
9350  
9351  	u8         reserved_at_20[0x10];
9352  	u8         op_mod[0x10];
9353  
9354  	u8         reserved_at_40[0x40];
9355  
9356  	struct mlx5_ifc_eqc_bits eq_context_entry;
9357  
9358  	u8         reserved_at_280[0x40];
9359  
9360  	u8         event_bitmask[4][0x40];
9361  
9362  	u8         reserved_at_3c0[0x4c0];
9363  
9364  	u8         pas[][0x40];
9365  };
9366  
9367  struct mlx5_ifc_create_dct_out_bits {
9368  	u8         status[0x8];
9369  	u8         reserved_at_8[0x18];
9370  
9371  	u8         syndrome[0x20];
9372  
9373  	u8         reserved_at_40[0x8];
9374  	u8         dctn[0x18];
9375  
9376  	u8         ece[0x20];
9377  };
9378  
9379  struct mlx5_ifc_create_dct_in_bits {
9380  	u8         opcode[0x10];
9381  	u8         uid[0x10];
9382  
9383  	u8         reserved_at_20[0x10];
9384  	u8         op_mod[0x10];
9385  
9386  	u8         reserved_at_40[0x40];
9387  
9388  	struct mlx5_ifc_dctc_bits dct_context_entry;
9389  
9390  	u8         reserved_at_280[0x180];
9391  };
9392  
9393  struct mlx5_ifc_create_cq_out_bits {
9394  	u8         status[0x8];
9395  	u8         reserved_at_8[0x18];
9396  
9397  	u8         syndrome[0x20];
9398  
9399  	u8         reserved_at_40[0x8];
9400  	u8         cqn[0x18];
9401  
9402  	u8         reserved_at_60[0x20];
9403  };
9404  
9405  struct mlx5_ifc_create_cq_in_bits {
9406  	u8         opcode[0x10];
9407  	u8         uid[0x10];
9408  
9409  	u8         reserved_at_20[0x10];
9410  	u8         op_mod[0x10];
9411  
9412  	u8         reserved_at_40[0x40];
9413  
9414  	struct mlx5_ifc_cqc_bits cq_context;
9415  
9416  	u8         reserved_at_280[0x60];
9417  
9418  	u8         cq_umem_valid[0x1];
9419  	u8         reserved_at_2e1[0x59f];
9420  
9421  	u8         pas[][0x40];
9422  };
9423  
9424  struct mlx5_ifc_config_int_moderation_out_bits {
9425  	u8         status[0x8];
9426  	u8         reserved_at_8[0x18];
9427  
9428  	u8         syndrome[0x20];
9429  
9430  	u8         reserved_at_40[0x4];
9431  	u8         min_delay[0xc];
9432  	u8         int_vector[0x10];
9433  
9434  	u8         reserved_at_60[0x20];
9435  };
9436  
9437  enum {
9438  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9439  	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9440  };
9441  
9442  struct mlx5_ifc_config_int_moderation_in_bits {
9443  	u8         opcode[0x10];
9444  	u8         reserved_at_10[0x10];
9445  
9446  	u8         reserved_at_20[0x10];
9447  	u8         op_mod[0x10];
9448  
9449  	u8         reserved_at_40[0x4];
9450  	u8         min_delay[0xc];
9451  	u8         int_vector[0x10];
9452  
9453  	u8         reserved_at_60[0x20];
9454  };
9455  
9456  struct mlx5_ifc_attach_to_mcg_out_bits {
9457  	u8         status[0x8];
9458  	u8         reserved_at_8[0x18];
9459  
9460  	u8         syndrome[0x20];
9461  
9462  	u8         reserved_at_40[0x40];
9463  };
9464  
9465  struct mlx5_ifc_attach_to_mcg_in_bits {
9466  	u8         opcode[0x10];
9467  	u8         uid[0x10];
9468  
9469  	u8         reserved_at_20[0x10];
9470  	u8         op_mod[0x10];
9471  
9472  	u8         reserved_at_40[0x8];
9473  	u8         qpn[0x18];
9474  
9475  	u8         reserved_at_60[0x20];
9476  
9477  	u8         multicast_gid[16][0x8];
9478  };
9479  
9480  struct mlx5_ifc_arm_xrq_out_bits {
9481  	u8         status[0x8];
9482  	u8         reserved_at_8[0x18];
9483  
9484  	u8         syndrome[0x20];
9485  
9486  	u8         reserved_at_40[0x40];
9487  };
9488  
9489  struct mlx5_ifc_arm_xrq_in_bits {
9490  	u8         opcode[0x10];
9491  	u8         reserved_at_10[0x10];
9492  
9493  	u8         reserved_at_20[0x10];
9494  	u8         op_mod[0x10];
9495  
9496  	u8         reserved_at_40[0x8];
9497  	u8         xrqn[0x18];
9498  
9499  	u8         reserved_at_60[0x10];
9500  	u8         lwm[0x10];
9501  };
9502  
9503  struct mlx5_ifc_arm_xrc_srq_out_bits {
9504  	u8         status[0x8];
9505  	u8         reserved_at_8[0x18];
9506  
9507  	u8         syndrome[0x20];
9508  
9509  	u8         reserved_at_40[0x40];
9510  };
9511  
9512  enum {
9513  	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9514  };
9515  
9516  struct mlx5_ifc_arm_xrc_srq_in_bits {
9517  	u8         opcode[0x10];
9518  	u8         uid[0x10];
9519  
9520  	u8         reserved_at_20[0x10];
9521  	u8         op_mod[0x10];
9522  
9523  	u8         reserved_at_40[0x8];
9524  	u8         xrc_srqn[0x18];
9525  
9526  	u8         reserved_at_60[0x10];
9527  	u8         lwm[0x10];
9528  };
9529  
9530  struct mlx5_ifc_arm_rq_out_bits {
9531  	u8         status[0x8];
9532  	u8         reserved_at_8[0x18];
9533  
9534  	u8         syndrome[0x20];
9535  
9536  	u8         reserved_at_40[0x40];
9537  };
9538  
9539  enum {
9540  	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9541  	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9542  };
9543  
9544  struct mlx5_ifc_arm_rq_in_bits {
9545  	u8         opcode[0x10];
9546  	u8         uid[0x10];
9547  
9548  	u8         reserved_at_20[0x10];
9549  	u8         op_mod[0x10];
9550  
9551  	u8         reserved_at_40[0x8];
9552  	u8         srq_number[0x18];
9553  
9554  	u8         reserved_at_60[0x10];
9555  	u8         lwm[0x10];
9556  };
9557  
9558  struct mlx5_ifc_arm_dct_out_bits {
9559  	u8         status[0x8];
9560  	u8         reserved_at_8[0x18];
9561  
9562  	u8         syndrome[0x20];
9563  
9564  	u8         reserved_at_40[0x40];
9565  };
9566  
9567  struct mlx5_ifc_arm_dct_in_bits {
9568  	u8         opcode[0x10];
9569  	u8         reserved_at_10[0x10];
9570  
9571  	u8         reserved_at_20[0x10];
9572  	u8         op_mod[0x10];
9573  
9574  	u8         reserved_at_40[0x8];
9575  	u8         dct_number[0x18];
9576  
9577  	u8         reserved_at_60[0x20];
9578  };
9579  
9580  struct mlx5_ifc_alloc_xrcd_out_bits {
9581  	u8         status[0x8];
9582  	u8         reserved_at_8[0x18];
9583  
9584  	u8         syndrome[0x20];
9585  
9586  	u8         reserved_at_40[0x8];
9587  	u8         xrcd[0x18];
9588  
9589  	u8         reserved_at_60[0x20];
9590  };
9591  
9592  struct mlx5_ifc_alloc_xrcd_in_bits {
9593  	u8         opcode[0x10];
9594  	u8         uid[0x10];
9595  
9596  	u8         reserved_at_20[0x10];
9597  	u8         op_mod[0x10];
9598  
9599  	u8         reserved_at_40[0x40];
9600  };
9601  
9602  struct mlx5_ifc_alloc_uar_out_bits {
9603  	u8         status[0x8];
9604  	u8         reserved_at_8[0x18];
9605  
9606  	u8         syndrome[0x20];
9607  
9608  	u8         reserved_at_40[0x8];
9609  	u8         uar[0x18];
9610  
9611  	u8         reserved_at_60[0x20];
9612  };
9613  
9614  struct mlx5_ifc_alloc_uar_in_bits {
9615  	u8         opcode[0x10];
9616  	u8         uid[0x10];
9617  
9618  	u8         reserved_at_20[0x10];
9619  	u8         op_mod[0x10];
9620  
9621  	u8         reserved_at_40[0x40];
9622  };
9623  
9624  struct mlx5_ifc_alloc_transport_domain_out_bits {
9625  	u8         status[0x8];
9626  	u8         reserved_at_8[0x18];
9627  
9628  	u8         syndrome[0x20];
9629  
9630  	u8         reserved_at_40[0x8];
9631  	u8         transport_domain[0x18];
9632  
9633  	u8         reserved_at_60[0x20];
9634  };
9635  
9636  struct mlx5_ifc_alloc_transport_domain_in_bits {
9637  	u8         opcode[0x10];
9638  	u8         uid[0x10];
9639  
9640  	u8         reserved_at_20[0x10];
9641  	u8         op_mod[0x10];
9642  
9643  	u8         reserved_at_40[0x40];
9644  };
9645  
9646  struct mlx5_ifc_alloc_q_counter_out_bits {
9647  	u8         status[0x8];
9648  	u8         reserved_at_8[0x18];
9649  
9650  	u8         syndrome[0x20];
9651  
9652  	u8         reserved_at_40[0x18];
9653  	u8         counter_set_id[0x8];
9654  
9655  	u8         reserved_at_60[0x20];
9656  };
9657  
9658  struct mlx5_ifc_alloc_q_counter_in_bits {
9659  	u8         opcode[0x10];
9660  	u8         uid[0x10];
9661  
9662  	u8         reserved_at_20[0x10];
9663  	u8         op_mod[0x10];
9664  
9665  	u8         reserved_at_40[0x40];
9666  };
9667  
9668  struct mlx5_ifc_alloc_pd_out_bits {
9669  	u8         status[0x8];
9670  	u8         reserved_at_8[0x18];
9671  
9672  	u8         syndrome[0x20];
9673  
9674  	u8         reserved_at_40[0x8];
9675  	u8         pd[0x18];
9676  
9677  	u8         reserved_at_60[0x20];
9678  };
9679  
9680  struct mlx5_ifc_alloc_pd_in_bits {
9681  	u8         opcode[0x10];
9682  	u8         uid[0x10];
9683  
9684  	u8         reserved_at_20[0x10];
9685  	u8         op_mod[0x10];
9686  
9687  	u8         reserved_at_40[0x40];
9688  };
9689  
9690  struct mlx5_ifc_alloc_flow_counter_out_bits {
9691  	u8         status[0x8];
9692  	u8         reserved_at_8[0x18];
9693  
9694  	u8         syndrome[0x20];
9695  
9696  	u8         flow_counter_id[0x20];
9697  
9698  	u8         reserved_at_60[0x20];
9699  };
9700  
9701  struct mlx5_ifc_alloc_flow_counter_in_bits {
9702  	u8         opcode[0x10];
9703  	u8         reserved_at_10[0x10];
9704  
9705  	u8         reserved_at_20[0x10];
9706  	u8         op_mod[0x10];
9707  
9708  	u8         reserved_at_40[0x33];
9709  	u8         flow_counter_bulk_log_size[0x5];
9710  	u8         flow_counter_bulk[0x8];
9711  };
9712  
9713  struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9714  	u8         status[0x8];
9715  	u8         reserved_at_8[0x18];
9716  
9717  	u8         syndrome[0x20];
9718  
9719  	u8         reserved_at_40[0x40];
9720  };
9721  
9722  struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9723  	u8         opcode[0x10];
9724  	u8         reserved_at_10[0x10];
9725  
9726  	u8         reserved_at_20[0x10];
9727  	u8         op_mod[0x10];
9728  
9729  	u8         reserved_at_40[0x20];
9730  
9731  	u8         reserved_at_60[0x10];
9732  	u8         vxlan_udp_port[0x10];
9733  };
9734  
9735  struct mlx5_ifc_set_pp_rate_limit_out_bits {
9736  	u8         status[0x8];
9737  	u8         reserved_at_8[0x18];
9738  
9739  	u8         syndrome[0x20];
9740  
9741  	u8         reserved_at_40[0x40];
9742  };
9743  
9744  struct mlx5_ifc_set_pp_rate_limit_context_bits {
9745  	u8         rate_limit[0x20];
9746  
9747  	u8	   burst_upper_bound[0x20];
9748  
9749  	u8         reserved_at_40[0x10];
9750  	u8	   typical_packet_size[0x10];
9751  
9752  	u8         reserved_at_60[0x120];
9753  };
9754  
9755  struct mlx5_ifc_set_pp_rate_limit_in_bits {
9756  	u8         opcode[0x10];
9757  	u8         uid[0x10];
9758  
9759  	u8         reserved_at_20[0x10];
9760  	u8         op_mod[0x10];
9761  
9762  	u8         reserved_at_40[0x10];
9763  	u8         rate_limit_index[0x10];
9764  
9765  	u8         reserved_at_60[0x20];
9766  
9767  	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9768  };
9769  
9770  struct mlx5_ifc_access_register_out_bits {
9771  	u8         status[0x8];
9772  	u8         reserved_at_8[0x18];
9773  
9774  	u8         syndrome[0x20];
9775  
9776  	u8         reserved_at_40[0x40];
9777  
9778  	u8         register_data[][0x20];
9779  };
9780  
9781  enum {
9782  	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9783  	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9784  };
9785  
9786  struct mlx5_ifc_access_register_in_bits {
9787  	u8         opcode[0x10];
9788  	u8         reserved_at_10[0x10];
9789  
9790  	u8         reserved_at_20[0x10];
9791  	u8         op_mod[0x10];
9792  
9793  	u8         reserved_at_40[0x10];
9794  	u8         register_id[0x10];
9795  
9796  	u8         argument[0x20];
9797  
9798  	u8         register_data[][0x20];
9799  };
9800  
9801  struct mlx5_ifc_sltp_reg_bits {
9802  	u8         status[0x4];
9803  	u8         version[0x4];
9804  	u8         local_port[0x8];
9805  	u8         pnat[0x2];
9806  	u8         reserved_at_12[0x2];
9807  	u8         lane[0x4];
9808  	u8         reserved_at_18[0x8];
9809  
9810  	u8         reserved_at_20[0x20];
9811  
9812  	u8         reserved_at_40[0x7];
9813  	u8         polarity[0x1];
9814  	u8         ob_tap0[0x8];
9815  	u8         ob_tap1[0x8];
9816  	u8         ob_tap2[0x8];
9817  
9818  	u8         reserved_at_60[0xc];
9819  	u8         ob_preemp_mode[0x4];
9820  	u8         ob_reg[0x8];
9821  	u8         ob_bias[0x8];
9822  
9823  	u8         reserved_at_80[0x20];
9824  };
9825  
9826  struct mlx5_ifc_slrg_reg_bits {
9827  	u8         status[0x4];
9828  	u8         version[0x4];
9829  	u8         local_port[0x8];
9830  	u8         pnat[0x2];
9831  	u8         reserved_at_12[0x2];
9832  	u8         lane[0x4];
9833  	u8         reserved_at_18[0x8];
9834  
9835  	u8         time_to_link_up[0x10];
9836  	u8         reserved_at_30[0xc];
9837  	u8         grade_lane_speed[0x4];
9838  
9839  	u8         grade_version[0x8];
9840  	u8         grade[0x18];
9841  
9842  	u8         reserved_at_60[0x4];
9843  	u8         height_grade_type[0x4];
9844  	u8         height_grade[0x18];
9845  
9846  	u8         height_dz[0x10];
9847  	u8         height_dv[0x10];
9848  
9849  	u8         reserved_at_a0[0x10];
9850  	u8         height_sigma[0x10];
9851  
9852  	u8         reserved_at_c0[0x20];
9853  
9854  	u8         reserved_at_e0[0x4];
9855  	u8         phase_grade_type[0x4];
9856  	u8         phase_grade[0x18];
9857  
9858  	u8         reserved_at_100[0x8];
9859  	u8         phase_eo_pos[0x8];
9860  	u8         reserved_at_110[0x8];
9861  	u8         phase_eo_neg[0x8];
9862  
9863  	u8         ffe_set_tested[0x10];
9864  	u8         test_errors_per_lane[0x10];
9865  };
9866  
9867  struct mlx5_ifc_pvlc_reg_bits {
9868  	u8         reserved_at_0[0x8];
9869  	u8         local_port[0x8];
9870  	u8         reserved_at_10[0x10];
9871  
9872  	u8         reserved_at_20[0x1c];
9873  	u8         vl_hw_cap[0x4];
9874  
9875  	u8         reserved_at_40[0x1c];
9876  	u8         vl_admin[0x4];
9877  
9878  	u8         reserved_at_60[0x1c];
9879  	u8         vl_operational[0x4];
9880  };
9881  
9882  struct mlx5_ifc_pude_reg_bits {
9883  	u8         swid[0x8];
9884  	u8         local_port[0x8];
9885  	u8         reserved_at_10[0x4];
9886  	u8         admin_status[0x4];
9887  	u8         reserved_at_18[0x4];
9888  	u8         oper_status[0x4];
9889  
9890  	u8         reserved_at_20[0x60];
9891  };
9892  
9893  struct mlx5_ifc_ptys_reg_bits {
9894  	u8         reserved_at_0[0x1];
9895  	u8         an_disable_admin[0x1];
9896  	u8         an_disable_cap[0x1];
9897  	u8         reserved_at_3[0x5];
9898  	u8         local_port[0x8];
9899  	u8         reserved_at_10[0x8];
9900  	u8         plane_ind[0x4];
9901  	u8         reserved_at_1c[0x1];
9902  	u8         proto_mask[0x3];
9903  
9904  	u8         an_status[0x4];
9905  	u8         reserved_at_24[0xc];
9906  	u8         data_rate_oper[0x10];
9907  
9908  	u8         ext_eth_proto_capability[0x20];
9909  
9910  	u8         eth_proto_capability[0x20];
9911  
9912  	u8         ib_link_width_capability[0x10];
9913  	u8         ib_proto_capability[0x10];
9914  
9915  	u8         ext_eth_proto_admin[0x20];
9916  
9917  	u8         eth_proto_admin[0x20];
9918  
9919  	u8         ib_link_width_admin[0x10];
9920  	u8         ib_proto_admin[0x10];
9921  
9922  	u8         ext_eth_proto_oper[0x20];
9923  
9924  	u8         eth_proto_oper[0x20];
9925  
9926  	u8         ib_link_width_oper[0x10];
9927  	u8         ib_proto_oper[0x10];
9928  
9929  	u8         reserved_at_160[0x1c];
9930  	u8         connector_type[0x4];
9931  
9932  	u8         eth_proto_lp_advertise[0x20];
9933  
9934  	u8         reserved_at_1a0[0x60];
9935  };
9936  
9937  struct mlx5_ifc_mlcr_reg_bits {
9938  	u8         reserved_at_0[0x8];
9939  	u8         local_port[0x8];
9940  	u8         reserved_at_10[0x20];
9941  
9942  	u8         beacon_duration[0x10];
9943  	u8         reserved_at_40[0x10];
9944  
9945  	u8         beacon_remain[0x10];
9946  };
9947  
9948  struct mlx5_ifc_ptas_reg_bits {
9949  	u8         reserved_at_0[0x20];
9950  
9951  	u8         algorithm_options[0x10];
9952  	u8         reserved_at_30[0x4];
9953  	u8         repetitions_mode[0x4];
9954  	u8         num_of_repetitions[0x8];
9955  
9956  	u8         grade_version[0x8];
9957  	u8         height_grade_type[0x4];
9958  	u8         phase_grade_type[0x4];
9959  	u8         height_grade_weight[0x8];
9960  	u8         phase_grade_weight[0x8];
9961  
9962  	u8         gisim_measure_bits[0x10];
9963  	u8         adaptive_tap_measure_bits[0x10];
9964  
9965  	u8         ber_bath_high_error_threshold[0x10];
9966  	u8         ber_bath_mid_error_threshold[0x10];
9967  
9968  	u8         ber_bath_low_error_threshold[0x10];
9969  	u8         one_ratio_high_threshold[0x10];
9970  
9971  	u8         one_ratio_high_mid_threshold[0x10];
9972  	u8         one_ratio_low_mid_threshold[0x10];
9973  
9974  	u8         one_ratio_low_threshold[0x10];
9975  	u8         ndeo_error_threshold[0x10];
9976  
9977  	u8         mixer_offset_step_size[0x10];
9978  	u8         reserved_at_110[0x8];
9979  	u8         mix90_phase_for_voltage_bath[0x8];
9980  
9981  	u8         mixer_offset_start[0x10];
9982  	u8         mixer_offset_end[0x10];
9983  
9984  	u8         reserved_at_140[0x15];
9985  	u8         ber_test_time[0xb];
9986  };
9987  
9988  struct mlx5_ifc_pspa_reg_bits {
9989  	u8         swid[0x8];
9990  	u8         local_port[0x8];
9991  	u8         sub_port[0x8];
9992  	u8         reserved_at_18[0x8];
9993  
9994  	u8         reserved_at_20[0x20];
9995  };
9996  
9997  struct mlx5_ifc_pqdr_reg_bits {
9998  	u8         reserved_at_0[0x8];
9999  	u8         local_port[0x8];
10000  	u8         reserved_at_10[0x5];
10001  	u8         prio[0x3];
10002  	u8         reserved_at_18[0x6];
10003  	u8         mode[0x2];
10004  
10005  	u8         reserved_at_20[0x20];
10006  
10007  	u8         reserved_at_40[0x10];
10008  	u8         min_threshold[0x10];
10009  
10010  	u8         reserved_at_60[0x10];
10011  	u8         max_threshold[0x10];
10012  
10013  	u8         reserved_at_80[0x10];
10014  	u8         mark_probability_denominator[0x10];
10015  
10016  	u8         reserved_at_a0[0x60];
10017  };
10018  
10019  struct mlx5_ifc_ppsc_reg_bits {
10020  	u8         reserved_at_0[0x8];
10021  	u8         local_port[0x8];
10022  	u8         reserved_at_10[0x10];
10023  
10024  	u8         reserved_at_20[0x60];
10025  
10026  	u8         reserved_at_80[0x1c];
10027  	u8         wrps_admin[0x4];
10028  
10029  	u8         reserved_at_a0[0x1c];
10030  	u8         wrps_status[0x4];
10031  
10032  	u8         reserved_at_c0[0x8];
10033  	u8         up_threshold[0x8];
10034  	u8         reserved_at_d0[0x8];
10035  	u8         down_threshold[0x8];
10036  
10037  	u8         reserved_at_e0[0x20];
10038  
10039  	u8         reserved_at_100[0x1c];
10040  	u8         srps_admin[0x4];
10041  
10042  	u8         reserved_at_120[0x1c];
10043  	u8         srps_status[0x4];
10044  
10045  	u8         reserved_at_140[0x40];
10046  };
10047  
10048  struct mlx5_ifc_pplr_reg_bits {
10049  	u8         reserved_at_0[0x8];
10050  	u8         local_port[0x8];
10051  	u8         reserved_at_10[0x10];
10052  
10053  	u8         reserved_at_20[0x8];
10054  	u8         lb_cap[0x8];
10055  	u8         reserved_at_30[0x8];
10056  	u8         lb_en[0x8];
10057  };
10058  
10059  struct mlx5_ifc_pplm_reg_bits {
10060  	u8         reserved_at_0[0x8];
10061  	u8	   local_port[0x8];
10062  	u8	   reserved_at_10[0x10];
10063  
10064  	u8	   reserved_at_20[0x20];
10065  
10066  	u8	   port_profile_mode[0x8];
10067  	u8	   static_port_profile[0x8];
10068  	u8	   active_port_profile[0x8];
10069  	u8	   reserved_at_58[0x8];
10070  
10071  	u8	   retransmission_active[0x8];
10072  	u8	   fec_mode_active[0x18];
10073  
10074  	u8	   rs_fec_correction_bypass_cap[0x4];
10075  	u8	   reserved_at_84[0x8];
10076  	u8	   fec_override_cap_56g[0x4];
10077  	u8	   fec_override_cap_100g[0x4];
10078  	u8	   fec_override_cap_50g[0x4];
10079  	u8	   fec_override_cap_25g[0x4];
10080  	u8	   fec_override_cap_10g_40g[0x4];
10081  
10082  	u8	   rs_fec_correction_bypass_admin[0x4];
10083  	u8	   reserved_at_a4[0x8];
10084  	u8	   fec_override_admin_56g[0x4];
10085  	u8	   fec_override_admin_100g[0x4];
10086  	u8	   fec_override_admin_50g[0x4];
10087  	u8	   fec_override_admin_25g[0x4];
10088  	u8	   fec_override_admin_10g_40g[0x4];
10089  
10090  	u8         fec_override_cap_400g_8x[0x10];
10091  	u8         fec_override_cap_200g_4x[0x10];
10092  
10093  	u8         fec_override_cap_100g_2x[0x10];
10094  	u8         fec_override_cap_50g_1x[0x10];
10095  
10096  	u8         fec_override_admin_400g_8x[0x10];
10097  	u8         fec_override_admin_200g_4x[0x10];
10098  
10099  	u8         fec_override_admin_100g_2x[0x10];
10100  	u8         fec_override_admin_50g_1x[0x10];
10101  
10102  	u8         fec_override_cap_800g_8x[0x10];
10103  	u8         fec_override_cap_400g_4x[0x10];
10104  
10105  	u8         fec_override_cap_200g_2x[0x10];
10106  	u8         fec_override_cap_100g_1x[0x10];
10107  
10108  	u8         reserved_at_180[0xa0];
10109  
10110  	u8         fec_override_admin_800g_8x[0x10];
10111  	u8         fec_override_admin_400g_4x[0x10];
10112  
10113  	u8         fec_override_admin_200g_2x[0x10];
10114  	u8         fec_override_admin_100g_1x[0x10];
10115  
10116  	u8         reserved_at_260[0x20];
10117  };
10118  
10119  struct mlx5_ifc_ppcnt_reg_bits {
10120  	u8         swid[0x8];
10121  	u8         local_port[0x8];
10122  	u8         pnat[0x2];
10123  	u8         reserved_at_12[0x8];
10124  	u8         grp[0x6];
10125  
10126  	u8         clr[0x1];
10127  	u8         reserved_at_21[0x13];
10128  	u8         plane_ind[0x4];
10129  	u8         reserved_at_38[0x3];
10130  	u8         prio_tc[0x5];
10131  
10132  	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10133  };
10134  
10135  struct mlx5_ifc_mpein_reg_bits {
10136  	u8         reserved_at_0[0x2];
10137  	u8         depth[0x6];
10138  	u8         pcie_index[0x8];
10139  	u8         node[0x8];
10140  	u8         reserved_at_18[0x8];
10141  
10142  	u8         capability_mask[0x20];
10143  
10144  	u8         reserved_at_40[0x8];
10145  	u8         link_width_enabled[0x8];
10146  	u8         link_speed_enabled[0x10];
10147  
10148  	u8         lane0_physical_position[0x8];
10149  	u8         link_width_active[0x8];
10150  	u8         link_speed_active[0x10];
10151  
10152  	u8         num_of_pfs[0x10];
10153  	u8         num_of_vfs[0x10];
10154  
10155  	u8         bdf0[0x10];
10156  	u8         reserved_at_b0[0x10];
10157  
10158  	u8         max_read_request_size[0x4];
10159  	u8         max_payload_size[0x4];
10160  	u8         reserved_at_c8[0x5];
10161  	u8         pwr_status[0x3];
10162  	u8         port_type[0x4];
10163  	u8         reserved_at_d4[0xb];
10164  	u8         lane_reversal[0x1];
10165  
10166  	u8         reserved_at_e0[0x14];
10167  	u8         pci_power[0xc];
10168  
10169  	u8         reserved_at_100[0x20];
10170  
10171  	u8         device_status[0x10];
10172  	u8         port_state[0x8];
10173  	u8         reserved_at_138[0x8];
10174  
10175  	u8         reserved_at_140[0x10];
10176  	u8         receiver_detect_result[0x10];
10177  
10178  	u8         reserved_at_160[0x20];
10179  };
10180  
10181  struct mlx5_ifc_mpcnt_reg_bits {
10182  	u8         reserved_at_0[0x8];
10183  	u8         pcie_index[0x8];
10184  	u8         reserved_at_10[0xa];
10185  	u8         grp[0x6];
10186  
10187  	u8         clr[0x1];
10188  	u8         reserved_at_21[0x1f];
10189  
10190  	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10191  };
10192  
10193  struct mlx5_ifc_ppad_reg_bits {
10194  	u8         reserved_at_0[0x3];
10195  	u8         single_mac[0x1];
10196  	u8         reserved_at_4[0x4];
10197  	u8         local_port[0x8];
10198  	u8         mac_47_32[0x10];
10199  
10200  	u8         mac_31_0[0x20];
10201  
10202  	u8         reserved_at_40[0x40];
10203  };
10204  
10205  struct mlx5_ifc_pmtu_reg_bits {
10206  	u8         reserved_at_0[0x8];
10207  	u8         local_port[0x8];
10208  	u8         reserved_at_10[0x10];
10209  
10210  	u8         max_mtu[0x10];
10211  	u8         reserved_at_30[0x10];
10212  
10213  	u8         admin_mtu[0x10];
10214  	u8         reserved_at_50[0x10];
10215  
10216  	u8         oper_mtu[0x10];
10217  	u8         reserved_at_70[0x10];
10218  };
10219  
10220  struct mlx5_ifc_pmpr_reg_bits {
10221  	u8         reserved_at_0[0x8];
10222  	u8         module[0x8];
10223  	u8         reserved_at_10[0x10];
10224  
10225  	u8         reserved_at_20[0x18];
10226  	u8         attenuation_5g[0x8];
10227  
10228  	u8         reserved_at_40[0x18];
10229  	u8         attenuation_7g[0x8];
10230  
10231  	u8         reserved_at_60[0x18];
10232  	u8         attenuation_12g[0x8];
10233  };
10234  
10235  struct mlx5_ifc_pmpe_reg_bits {
10236  	u8         reserved_at_0[0x8];
10237  	u8         module[0x8];
10238  	u8         reserved_at_10[0xc];
10239  	u8         module_status[0x4];
10240  
10241  	u8         reserved_at_20[0x60];
10242  };
10243  
10244  struct mlx5_ifc_pmpc_reg_bits {
10245  	u8         module_state_updated[32][0x8];
10246  };
10247  
10248  struct mlx5_ifc_pmlpn_reg_bits {
10249  	u8         reserved_at_0[0x4];
10250  	u8         mlpn_status[0x4];
10251  	u8         local_port[0x8];
10252  	u8         reserved_at_10[0x10];
10253  
10254  	u8         e[0x1];
10255  	u8         reserved_at_21[0x1f];
10256  };
10257  
10258  struct mlx5_ifc_pmlp_reg_bits {
10259  	u8         rxtx[0x1];
10260  	u8         reserved_at_1[0x7];
10261  	u8         local_port[0x8];
10262  	u8         reserved_at_10[0x8];
10263  	u8         width[0x8];
10264  
10265  	u8         lane0_module_mapping[0x20];
10266  
10267  	u8         lane1_module_mapping[0x20];
10268  
10269  	u8         lane2_module_mapping[0x20];
10270  
10271  	u8         lane3_module_mapping[0x20];
10272  
10273  	u8         reserved_at_a0[0x160];
10274  };
10275  
10276  struct mlx5_ifc_pmaos_reg_bits {
10277  	u8         reserved_at_0[0x8];
10278  	u8         module[0x8];
10279  	u8         reserved_at_10[0x4];
10280  	u8         admin_status[0x4];
10281  	u8         reserved_at_18[0x4];
10282  	u8         oper_status[0x4];
10283  
10284  	u8         ase[0x1];
10285  	u8         ee[0x1];
10286  	u8         reserved_at_22[0x1c];
10287  	u8         e[0x2];
10288  
10289  	u8         reserved_at_40[0x40];
10290  };
10291  
10292  struct mlx5_ifc_plpc_reg_bits {
10293  	u8         reserved_at_0[0x4];
10294  	u8         profile_id[0xc];
10295  	u8         reserved_at_10[0x4];
10296  	u8         proto_mask[0x4];
10297  	u8         reserved_at_18[0x8];
10298  
10299  	u8         reserved_at_20[0x10];
10300  	u8         lane_speed[0x10];
10301  
10302  	u8         reserved_at_40[0x17];
10303  	u8         lpbf[0x1];
10304  	u8         fec_mode_policy[0x8];
10305  
10306  	u8         retransmission_capability[0x8];
10307  	u8         fec_mode_capability[0x18];
10308  
10309  	u8         retransmission_support_admin[0x8];
10310  	u8         fec_mode_support_admin[0x18];
10311  
10312  	u8         retransmission_request_admin[0x8];
10313  	u8         fec_mode_request_admin[0x18];
10314  
10315  	u8         reserved_at_c0[0x80];
10316  };
10317  
10318  struct mlx5_ifc_plib_reg_bits {
10319  	u8         reserved_at_0[0x8];
10320  	u8         local_port[0x8];
10321  	u8         reserved_at_10[0x8];
10322  	u8         ib_port[0x8];
10323  
10324  	u8         reserved_at_20[0x60];
10325  };
10326  
10327  struct mlx5_ifc_plbf_reg_bits {
10328  	u8         reserved_at_0[0x8];
10329  	u8         local_port[0x8];
10330  	u8         reserved_at_10[0xd];
10331  	u8         lbf_mode[0x3];
10332  
10333  	u8         reserved_at_20[0x20];
10334  };
10335  
10336  struct mlx5_ifc_pipg_reg_bits {
10337  	u8         reserved_at_0[0x8];
10338  	u8         local_port[0x8];
10339  	u8         reserved_at_10[0x10];
10340  
10341  	u8         dic[0x1];
10342  	u8         reserved_at_21[0x19];
10343  	u8         ipg[0x4];
10344  	u8         reserved_at_3e[0x2];
10345  };
10346  
10347  struct mlx5_ifc_pifr_reg_bits {
10348  	u8         reserved_at_0[0x8];
10349  	u8         local_port[0x8];
10350  	u8         reserved_at_10[0x10];
10351  
10352  	u8         reserved_at_20[0xe0];
10353  
10354  	u8         port_filter[8][0x20];
10355  
10356  	u8         port_filter_update_en[8][0x20];
10357  };
10358  
10359  struct mlx5_ifc_pfcc_reg_bits {
10360  	u8         reserved_at_0[0x8];
10361  	u8         local_port[0x8];
10362  	u8         reserved_at_10[0xb];
10363  	u8         ppan_mask_n[0x1];
10364  	u8         minor_stall_mask[0x1];
10365  	u8         critical_stall_mask[0x1];
10366  	u8         reserved_at_1e[0x2];
10367  
10368  	u8         ppan[0x4];
10369  	u8         reserved_at_24[0x4];
10370  	u8         prio_mask_tx[0x8];
10371  	u8         reserved_at_30[0x8];
10372  	u8         prio_mask_rx[0x8];
10373  
10374  	u8         pptx[0x1];
10375  	u8         aptx[0x1];
10376  	u8         pptx_mask_n[0x1];
10377  	u8         reserved_at_43[0x5];
10378  	u8         pfctx[0x8];
10379  	u8         reserved_at_50[0x10];
10380  
10381  	u8         pprx[0x1];
10382  	u8         aprx[0x1];
10383  	u8         pprx_mask_n[0x1];
10384  	u8         reserved_at_63[0x5];
10385  	u8         pfcrx[0x8];
10386  	u8         reserved_at_70[0x10];
10387  
10388  	u8         device_stall_minor_watermark[0x10];
10389  	u8         device_stall_critical_watermark[0x10];
10390  
10391  	u8         reserved_at_a0[0x60];
10392  };
10393  
10394  struct mlx5_ifc_pelc_reg_bits {
10395  	u8         op[0x4];
10396  	u8         reserved_at_4[0x4];
10397  	u8         local_port[0x8];
10398  	u8         reserved_at_10[0x10];
10399  
10400  	u8         op_admin[0x8];
10401  	u8         op_capability[0x8];
10402  	u8         op_request[0x8];
10403  	u8         op_active[0x8];
10404  
10405  	u8         admin[0x40];
10406  
10407  	u8         capability[0x40];
10408  
10409  	u8         request[0x40];
10410  
10411  	u8         active[0x40];
10412  
10413  	u8         reserved_at_140[0x80];
10414  };
10415  
10416  struct mlx5_ifc_peir_reg_bits {
10417  	u8         reserved_at_0[0x8];
10418  	u8         local_port[0x8];
10419  	u8         reserved_at_10[0x10];
10420  
10421  	u8         reserved_at_20[0xc];
10422  	u8         error_count[0x4];
10423  	u8         reserved_at_30[0x10];
10424  
10425  	u8         reserved_at_40[0xc];
10426  	u8         lane[0x4];
10427  	u8         reserved_at_50[0x8];
10428  	u8         error_type[0x8];
10429  };
10430  
10431  struct mlx5_ifc_mpegc_reg_bits {
10432  	u8         reserved_at_0[0x30];
10433  	u8         field_select[0x10];
10434  
10435  	u8         tx_overflow_sense[0x1];
10436  	u8         mark_cqe[0x1];
10437  	u8         mark_cnp[0x1];
10438  	u8         reserved_at_43[0x1b];
10439  	u8         tx_lossy_overflow_oper[0x2];
10440  
10441  	u8         reserved_at_60[0x100];
10442  };
10443  
10444  struct mlx5_ifc_mpir_reg_bits {
10445  	u8         sdm[0x1];
10446  	u8         reserved_at_1[0x1b];
10447  	u8         host_buses[0x4];
10448  
10449  	u8         reserved_at_20[0x20];
10450  
10451  	u8         local_port[0x8];
10452  	u8         reserved_at_28[0x18];
10453  
10454  	u8         reserved_at_60[0x20];
10455  };
10456  
10457  enum {
10458  	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10459  	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10460  };
10461  
10462  enum {
10463  	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10464  	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10465  	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10466  };
10467  
10468  struct mlx5_ifc_mtutc_reg_bits {
10469  	u8         reserved_at_0[0x5];
10470  	u8         freq_adj_units[0x3];
10471  	u8         reserved_at_8[0x3];
10472  	u8         log_max_freq_adjustment[0x5];
10473  
10474  	u8         reserved_at_10[0xc];
10475  	u8         operation[0x4];
10476  
10477  	u8         freq_adjustment[0x20];
10478  
10479  	u8         reserved_at_40[0x40];
10480  
10481  	u8         utc_sec[0x20];
10482  
10483  	u8         reserved_at_a0[0x2];
10484  	u8         utc_nsec[0x1e];
10485  
10486  	u8         time_adjustment[0x20];
10487  };
10488  
10489  struct mlx5_ifc_pcam_enhanced_features_bits {
10490  	u8         reserved_at_0[0x48];
10491  	u8         fec_100G_per_lane_in_pplm[0x1];
10492  	u8         reserved_at_49[0x1f];
10493  	u8         fec_50G_per_lane_in_pplm[0x1];
10494  	u8         reserved_at_69[0x4];
10495  	u8         rx_icrc_encapsulated_counter[0x1];
10496  	u8	   reserved_at_6e[0x4];
10497  	u8         ptys_extended_ethernet[0x1];
10498  	u8	   reserved_at_73[0x3];
10499  	u8         pfcc_mask[0x1];
10500  	u8         reserved_at_77[0x3];
10501  	u8         per_lane_error_counters[0x1];
10502  	u8         rx_buffer_fullness_counters[0x1];
10503  	u8         ptys_connector_type[0x1];
10504  	u8         reserved_at_7d[0x1];
10505  	u8         ppcnt_discard_group[0x1];
10506  	u8         ppcnt_statistical_group[0x1];
10507  };
10508  
10509  struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10510  	u8         port_access_reg_cap_mask_127_to_96[0x20];
10511  	u8         port_access_reg_cap_mask_95_to_64[0x20];
10512  
10513  	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10514  	u8         pplm[0x1];
10515  	u8         port_access_reg_cap_mask_34_to_32[0x3];
10516  
10517  	u8         port_access_reg_cap_mask_31_to_13[0x13];
10518  	u8         pbmc[0x1];
10519  	u8         pptb[0x1];
10520  	u8         port_access_reg_cap_mask_10_to_09[0x2];
10521  	u8         ppcnt[0x1];
10522  	u8         port_access_reg_cap_mask_07_to_00[0x8];
10523  };
10524  
10525  struct mlx5_ifc_pcam_reg_bits {
10526  	u8         reserved_at_0[0x8];
10527  	u8         feature_group[0x8];
10528  	u8         reserved_at_10[0x8];
10529  	u8         access_reg_group[0x8];
10530  
10531  	u8         reserved_at_20[0x20];
10532  
10533  	union {
10534  		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10535  		u8         reserved_at_0[0x80];
10536  	} port_access_reg_cap_mask;
10537  
10538  	u8         reserved_at_c0[0x80];
10539  
10540  	union {
10541  		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10542  		u8         reserved_at_0[0x80];
10543  	} feature_cap_mask;
10544  
10545  	u8         reserved_at_1c0[0xc0];
10546  };
10547  
10548  struct mlx5_ifc_mcam_enhanced_features_bits {
10549  	u8         reserved_at_0[0x50];
10550  	u8         mtutc_freq_adj_units[0x1];
10551  	u8         mtutc_time_adjustment_extended_range[0x1];
10552  	u8         reserved_at_52[0xb];
10553  	u8         mcia_32dwords[0x1];
10554  	u8         out_pulse_duration_ns[0x1];
10555  	u8         npps_period[0x1];
10556  	u8         reserved_at_60[0xa];
10557  	u8         reset_state[0x1];
10558  	u8         ptpcyc2realtime_modify[0x1];
10559  	u8         reserved_at_6c[0x2];
10560  	u8         pci_status_and_power[0x1];
10561  	u8         reserved_at_6f[0x5];
10562  	u8         mark_tx_action_cnp[0x1];
10563  	u8         mark_tx_action_cqe[0x1];
10564  	u8         dynamic_tx_overflow[0x1];
10565  	u8         reserved_at_77[0x4];
10566  	u8         pcie_outbound_stalled[0x1];
10567  	u8         tx_overflow_buffer_pkt[0x1];
10568  	u8         mtpps_enh_out_per_adj[0x1];
10569  	u8         mtpps_fs[0x1];
10570  	u8         pcie_performance_group[0x1];
10571  };
10572  
10573  struct mlx5_ifc_mcam_access_reg_bits {
10574  	u8         reserved_at_0[0x1c];
10575  	u8         mcda[0x1];
10576  	u8         mcc[0x1];
10577  	u8         mcqi[0x1];
10578  	u8         mcqs[0x1];
10579  
10580  	u8         regs_95_to_90[0x6];
10581  	u8         mpir[0x1];
10582  	u8         regs_88_to_87[0x2];
10583  	u8         mpegc[0x1];
10584  	u8         mtutc[0x1];
10585  	u8         regs_84_to_68[0x11];
10586  	u8         tracer_registers[0x4];
10587  
10588  	u8         regs_63_to_46[0x12];
10589  	u8         mrtc[0x1];
10590  	u8         regs_44_to_41[0x4];
10591  	u8         mfrl[0x1];
10592  	u8         regs_39_to_32[0x8];
10593  
10594  	u8         regs_31_to_11[0x15];
10595  	u8         mtmp[0x1];
10596  	u8         regs_9_to_0[0xa];
10597  };
10598  
10599  struct mlx5_ifc_mcam_access_reg_bits1 {
10600  	u8         regs_127_to_96[0x20];
10601  
10602  	u8         regs_95_to_64[0x20];
10603  
10604  	u8         regs_63_to_32[0x20];
10605  
10606  	u8         regs_31_to_0[0x20];
10607  };
10608  
10609  struct mlx5_ifc_mcam_access_reg_bits2 {
10610  	u8         regs_127_to_99[0x1d];
10611  	u8         mirc[0x1];
10612  	u8         regs_97_to_96[0x2];
10613  
10614  	u8         regs_95_to_87[0x09];
10615  	u8         synce_registers[0x2];
10616  	u8         regs_84_to_64[0x15];
10617  
10618  	u8         regs_63_to_32[0x20];
10619  
10620  	u8         regs_31_to_0[0x20];
10621  };
10622  
10623  struct mlx5_ifc_mcam_access_reg_bits3 {
10624  	u8         regs_127_to_96[0x20];
10625  
10626  	u8         regs_95_to_64[0x20];
10627  
10628  	u8         regs_63_to_32[0x20];
10629  
10630  	u8         regs_31_to_2[0x1e];
10631  	u8         mtctr[0x1];
10632  	u8         mtptm[0x1];
10633  };
10634  
10635  struct mlx5_ifc_mcam_reg_bits {
10636  	u8         reserved_at_0[0x8];
10637  	u8         feature_group[0x8];
10638  	u8         reserved_at_10[0x8];
10639  	u8         access_reg_group[0x8];
10640  
10641  	u8         reserved_at_20[0x20];
10642  
10643  	union {
10644  		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10645  		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10646  		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10647  		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10648  		u8         reserved_at_0[0x80];
10649  	} mng_access_reg_cap_mask;
10650  
10651  	u8         reserved_at_c0[0x80];
10652  
10653  	union {
10654  		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10655  		u8         reserved_at_0[0x80];
10656  	} mng_feature_cap_mask;
10657  
10658  	u8         reserved_at_1c0[0x80];
10659  };
10660  
10661  struct mlx5_ifc_qcam_access_reg_cap_mask {
10662  	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10663  	u8         qpdpm[0x1];
10664  	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10665  	u8         qdpm[0x1];
10666  	u8         qpts[0x1];
10667  	u8         qcap[0x1];
10668  	u8         qcam_access_reg_cap_mask_0[0x1];
10669  };
10670  
10671  struct mlx5_ifc_qcam_qos_feature_cap_mask {
10672  	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10673  	u8         qpts_trust_both[0x1];
10674  };
10675  
10676  struct mlx5_ifc_qcam_reg_bits {
10677  	u8         reserved_at_0[0x8];
10678  	u8         feature_group[0x8];
10679  	u8         reserved_at_10[0x8];
10680  	u8         access_reg_group[0x8];
10681  	u8         reserved_at_20[0x20];
10682  
10683  	union {
10684  		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10685  		u8  reserved_at_0[0x80];
10686  	} qos_access_reg_cap_mask;
10687  
10688  	u8         reserved_at_c0[0x80];
10689  
10690  	union {
10691  		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10692  		u8  reserved_at_0[0x80];
10693  	} qos_feature_cap_mask;
10694  
10695  	u8         reserved_at_1c0[0x80];
10696  };
10697  
10698  struct mlx5_ifc_core_dump_reg_bits {
10699  	u8         reserved_at_0[0x18];
10700  	u8         core_dump_type[0x8];
10701  
10702  	u8         reserved_at_20[0x30];
10703  	u8         vhca_id[0x10];
10704  
10705  	u8         reserved_at_60[0x8];
10706  	u8         qpn[0x18];
10707  	u8         reserved_at_80[0x180];
10708  };
10709  
10710  struct mlx5_ifc_pcap_reg_bits {
10711  	u8         reserved_at_0[0x8];
10712  	u8         local_port[0x8];
10713  	u8         reserved_at_10[0x10];
10714  
10715  	u8         port_capability_mask[4][0x20];
10716  };
10717  
10718  struct mlx5_ifc_paos_reg_bits {
10719  	u8         swid[0x8];
10720  	u8         local_port[0x8];
10721  	u8         reserved_at_10[0x4];
10722  	u8         admin_status[0x4];
10723  	u8         reserved_at_18[0x4];
10724  	u8         oper_status[0x4];
10725  
10726  	u8         ase[0x1];
10727  	u8         ee[0x1];
10728  	u8         reserved_at_22[0x1c];
10729  	u8         e[0x2];
10730  
10731  	u8         reserved_at_40[0x40];
10732  };
10733  
10734  struct mlx5_ifc_pamp_reg_bits {
10735  	u8         reserved_at_0[0x8];
10736  	u8         opamp_group[0x8];
10737  	u8         reserved_at_10[0xc];
10738  	u8         opamp_group_type[0x4];
10739  
10740  	u8         start_index[0x10];
10741  	u8         reserved_at_30[0x4];
10742  	u8         num_of_indices[0xc];
10743  
10744  	u8         index_data[18][0x10];
10745  };
10746  
10747  struct mlx5_ifc_pcmr_reg_bits {
10748  	u8         reserved_at_0[0x8];
10749  	u8         local_port[0x8];
10750  	u8         reserved_at_10[0x10];
10751  
10752  	u8         entropy_force_cap[0x1];
10753  	u8         entropy_calc_cap[0x1];
10754  	u8         entropy_gre_calc_cap[0x1];
10755  	u8         reserved_at_23[0xf];
10756  	u8         rx_ts_over_crc_cap[0x1];
10757  	u8         reserved_at_33[0xb];
10758  	u8         fcs_cap[0x1];
10759  	u8         reserved_at_3f[0x1];
10760  
10761  	u8         entropy_force[0x1];
10762  	u8         entropy_calc[0x1];
10763  	u8         entropy_gre_calc[0x1];
10764  	u8         reserved_at_43[0xf];
10765  	u8         rx_ts_over_crc[0x1];
10766  	u8         reserved_at_53[0xb];
10767  	u8         fcs_chk[0x1];
10768  	u8         reserved_at_5f[0x1];
10769  };
10770  
10771  struct mlx5_ifc_lane_2_module_mapping_bits {
10772  	u8         reserved_at_0[0x4];
10773  	u8         rx_lane[0x4];
10774  	u8         reserved_at_8[0x4];
10775  	u8         tx_lane[0x4];
10776  	u8         reserved_at_10[0x8];
10777  	u8         module[0x8];
10778  };
10779  
10780  struct mlx5_ifc_bufferx_reg_bits {
10781  	u8         reserved_at_0[0x6];
10782  	u8         lossy[0x1];
10783  	u8         epsb[0x1];
10784  	u8         reserved_at_8[0x8];
10785  	u8         size[0x10];
10786  
10787  	u8         xoff_threshold[0x10];
10788  	u8         xon_threshold[0x10];
10789  };
10790  
10791  struct mlx5_ifc_set_node_in_bits {
10792  	u8         node_description[64][0x8];
10793  };
10794  
10795  struct mlx5_ifc_register_power_settings_bits {
10796  	u8         reserved_at_0[0x18];
10797  	u8         power_settings_level[0x8];
10798  
10799  	u8         reserved_at_20[0x60];
10800  };
10801  
10802  struct mlx5_ifc_register_host_endianness_bits {
10803  	u8         he[0x1];
10804  	u8         reserved_at_1[0x1f];
10805  
10806  	u8         reserved_at_20[0x60];
10807  };
10808  
10809  struct mlx5_ifc_umr_pointer_desc_argument_bits {
10810  	u8         reserved_at_0[0x20];
10811  
10812  	u8         mkey[0x20];
10813  
10814  	u8         addressh_63_32[0x20];
10815  
10816  	u8         addressl_31_0[0x20];
10817  };
10818  
10819  struct mlx5_ifc_ud_adrs_vector_bits {
10820  	u8         dc_key[0x40];
10821  
10822  	u8         ext[0x1];
10823  	u8         reserved_at_41[0x7];
10824  	u8         destination_qp_dct[0x18];
10825  
10826  	u8         static_rate[0x4];
10827  	u8         sl_eth_prio[0x4];
10828  	u8         fl[0x1];
10829  	u8         mlid[0x7];
10830  	u8         rlid_udp_sport[0x10];
10831  
10832  	u8         reserved_at_80[0x20];
10833  
10834  	u8         rmac_47_16[0x20];
10835  
10836  	u8         rmac_15_0[0x10];
10837  	u8         tclass[0x8];
10838  	u8         hop_limit[0x8];
10839  
10840  	u8         reserved_at_e0[0x1];
10841  	u8         grh[0x1];
10842  	u8         reserved_at_e2[0x2];
10843  	u8         src_addr_index[0x8];
10844  	u8         flow_label[0x14];
10845  
10846  	u8         rgid_rip[16][0x8];
10847  };
10848  
10849  struct mlx5_ifc_pages_req_event_bits {
10850  	u8         reserved_at_0[0x10];
10851  	u8         function_id[0x10];
10852  
10853  	u8         num_pages[0x20];
10854  
10855  	u8         reserved_at_40[0xa0];
10856  };
10857  
10858  struct mlx5_ifc_eqe_bits {
10859  	u8         reserved_at_0[0x8];
10860  	u8         event_type[0x8];
10861  	u8         reserved_at_10[0x8];
10862  	u8         event_sub_type[0x8];
10863  
10864  	u8         reserved_at_20[0xe0];
10865  
10866  	union mlx5_ifc_event_auto_bits event_data;
10867  
10868  	u8         reserved_at_1e0[0x10];
10869  	u8         signature[0x8];
10870  	u8         reserved_at_1f8[0x7];
10871  	u8         owner[0x1];
10872  };
10873  
10874  enum {
10875  	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10876  };
10877  
10878  struct mlx5_ifc_cmd_queue_entry_bits {
10879  	u8         type[0x8];
10880  	u8         reserved_at_8[0x18];
10881  
10882  	u8         input_length[0x20];
10883  
10884  	u8         input_mailbox_pointer_63_32[0x20];
10885  
10886  	u8         input_mailbox_pointer_31_9[0x17];
10887  	u8         reserved_at_77[0x9];
10888  
10889  	u8         command_input_inline_data[16][0x8];
10890  
10891  	u8         command_output_inline_data[16][0x8];
10892  
10893  	u8         output_mailbox_pointer_63_32[0x20];
10894  
10895  	u8         output_mailbox_pointer_31_9[0x17];
10896  	u8         reserved_at_1b7[0x9];
10897  
10898  	u8         output_length[0x20];
10899  
10900  	u8         token[0x8];
10901  	u8         signature[0x8];
10902  	u8         reserved_at_1f0[0x8];
10903  	u8         status[0x7];
10904  	u8         ownership[0x1];
10905  };
10906  
10907  struct mlx5_ifc_cmd_out_bits {
10908  	u8         status[0x8];
10909  	u8         reserved_at_8[0x18];
10910  
10911  	u8         syndrome[0x20];
10912  
10913  	u8         command_output[0x20];
10914  };
10915  
10916  struct mlx5_ifc_cmd_in_bits {
10917  	u8         opcode[0x10];
10918  	u8         reserved_at_10[0x10];
10919  
10920  	u8         reserved_at_20[0x10];
10921  	u8         op_mod[0x10];
10922  
10923  	u8         command[][0x20];
10924  };
10925  
10926  struct mlx5_ifc_cmd_if_box_bits {
10927  	u8         mailbox_data[512][0x8];
10928  
10929  	u8         reserved_at_1000[0x180];
10930  
10931  	u8         next_pointer_63_32[0x20];
10932  
10933  	u8         next_pointer_31_10[0x16];
10934  	u8         reserved_at_11b6[0xa];
10935  
10936  	u8         block_number[0x20];
10937  
10938  	u8         reserved_at_11e0[0x8];
10939  	u8         token[0x8];
10940  	u8         ctrl_signature[0x8];
10941  	u8         signature[0x8];
10942  };
10943  
10944  struct mlx5_ifc_mtt_bits {
10945  	u8         ptag_63_32[0x20];
10946  
10947  	u8         ptag_31_8[0x18];
10948  	u8         reserved_at_38[0x6];
10949  	u8         wr_en[0x1];
10950  	u8         rd_en[0x1];
10951  };
10952  
10953  struct mlx5_ifc_query_wol_rol_out_bits {
10954  	u8         status[0x8];
10955  	u8         reserved_at_8[0x18];
10956  
10957  	u8         syndrome[0x20];
10958  
10959  	u8         reserved_at_40[0x10];
10960  	u8         rol_mode[0x8];
10961  	u8         wol_mode[0x8];
10962  
10963  	u8         reserved_at_60[0x20];
10964  };
10965  
10966  struct mlx5_ifc_query_wol_rol_in_bits {
10967  	u8         opcode[0x10];
10968  	u8         reserved_at_10[0x10];
10969  
10970  	u8         reserved_at_20[0x10];
10971  	u8         op_mod[0x10];
10972  
10973  	u8         reserved_at_40[0x40];
10974  };
10975  
10976  struct mlx5_ifc_set_wol_rol_out_bits {
10977  	u8         status[0x8];
10978  	u8         reserved_at_8[0x18];
10979  
10980  	u8         syndrome[0x20];
10981  
10982  	u8         reserved_at_40[0x40];
10983  };
10984  
10985  struct mlx5_ifc_set_wol_rol_in_bits {
10986  	u8         opcode[0x10];
10987  	u8         reserved_at_10[0x10];
10988  
10989  	u8         reserved_at_20[0x10];
10990  	u8         op_mod[0x10];
10991  
10992  	u8         rol_mode_valid[0x1];
10993  	u8         wol_mode_valid[0x1];
10994  	u8         reserved_at_42[0xe];
10995  	u8         rol_mode[0x8];
10996  	u8         wol_mode[0x8];
10997  
10998  	u8         reserved_at_60[0x20];
10999  };
11000  
11001  enum {
11002  	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11003  	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11004  	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11005  	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11006  };
11007  
11008  enum {
11009  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11010  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11011  	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11012  };
11013  
11014  enum {
11015  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11016  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11017  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11018  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11019  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11020  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11021  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11022  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11023  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11024  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11025  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11026  	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11027  };
11028  
11029  struct mlx5_ifc_initial_seg_bits {
11030  	u8         fw_rev_minor[0x10];
11031  	u8         fw_rev_major[0x10];
11032  
11033  	u8         cmd_interface_rev[0x10];
11034  	u8         fw_rev_subminor[0x10];
11035  
11036  	u8         reserved_at_40[0x40];
11037  
11038  	u8         cmdq_phy_addr_63_32[0x20];
11039  
11040  	u8         cmdq_phy_addr_31_12[0x14];
11041  	u8         reserved_at_b4[0x2];
11042  	u8         nic_interface[0x2];
11043  	u8         log_cmdq_size[0x4];
11044  	u8         log_cmdq_stride[0x4];
11045  
11046  	u8         command_doorbell_vector[0x20];
11047  
11048  	u8         reserved_at_e0[0xf00];
11049  
11050  	u8         initializing[0x1];
11051  	u8         reserved_at_fe1[0x4];
11052  	u8         nic_interface_supported[0x3];
11053  	u8         embedded_cpu[0x1];
11054  	u8         reserved_at_fe9[0x17];
11055  
11056  	struct mlx5_ifc_health_buffer_bits health_buffer;
11057  
11058  	u8         no_dram_nic_offset[0x20];
11059  
11060  	u8         reserved_at_1220[0x6e40];
11061  
11062  	u8         reserved_at_8060[0x1f];
11063  	u8         clear_int[0x1];
11064  
11065  	u8         health_syndrome[0x8];
11066  	u8         health_counter[0x18];
11067  
11068  	u8         reserved_at_80a0[0x17fc0];
11069  };
11070  
11071  struct mlx5_ifc_mtpps_reg_bits {
11072  	u8         reserved_at_0[0xc];
11073  	u8         cap_number_of_pps_pins[0x4];
11074  	u8         reserved_at_10[0x4];
11075  	u8         cap_max_num_of_pps_in_pins[0x4];
11076  	u8         reserved_at_18[0x4];
11077  	u8         cap_max_num_of_pps_out_pins[0x4];
11078  
11079  	u8         reserved_at_20[0x13];
11080  	u8         cap_log_min_npps_period[0x5];
11081  	u8         reserved_at_38[0x3];
11082  	u8         cap_log_min_out_pulse_duration_ns[0x5];
11083  
11084  	u8         reserved_at_40[0x4];
11085  	u8         cap_pin_3_mode[0x4];
11086  	u8         reserved_at_48[0x4];
11087  	u8         cap_pin_2_mode[0x4];
11088  	u8         reserved_at_50[0x4];
11089  	u8         cap_pin_1_mode[0x4];
11090  	u8         reserved_at_58[0x4];
11091  	u8         cap_pin_0_mode[0x4];
11092  
11093  	u8         reserved_at_60[0x4];
11094  	u8         cap_pin_7_mode[0x4];
11095  	u8         reserved_at_68[0x4];
11096  	u8         cap_pin_6_mode[0x4];
11097  	u8         reserved_at_70[0x4];
11098  	u8         cap_pin_5_mode[0x4];
11099  	u8         reserved_at_78[0x4];
11100  	u8         cap_pin_4_mode[0x4];
11101  
11102  	u8         field_select[0x20];
11103  	u8         reserved_at_a0[0x20];
11104  
11105  	u8         npps_period[0x40];
11106  
11107  	u8         enable[0x1];
11108  	u8         reserved_at_101[0xb];
11109  	u8         pattern[0x4];
11110  	u8         reserved_at_110[0x4];
11111  	u8         pin_mode[0x4];
11112  	u8         pin[0x8];
11113  
11114  	u8         reserved_at_120[0x2];
11115  	u8         out_pulse_duration_ns[0x1e];
11116  
11117  	u8         time_stamp[0x40];
11118  
11119  	u8         out_pulse_duration[0x10];
11120  	u8         out_periodic_adjustment[0x10];
11121  	u8         enhanced_out_periodic_adjustment[0x20];
11122  
11123  	u8         reserved_at_1c0[0x20];
11124  };
11125  
11126  struct mlx5_ifc_mtppse_reg_bits {
11127  	u8         reserved_at_0[0x18];
11128  	u8         pin[0x8];
11129  	u8         event_arm[0x1];
11130  	u8         reserved_at_21[0x1b];
11131  	u8         event_generation_mode[0x4];
11132  	u8         reserved_at_40[0x40];
11133  };
11134  
11135  struct mlx5_ifc_mcqs_reg_bits {
11136  	u8         last_index_flag[0x1];
11137  	u8         reserved_at_1[0x7];
11138  	u8         fw_device[0x8];
11139  	u8         component_index[0x10];
11140  
11141  	u8         reserved_at_20[0x10];
11142  	u8         identifier[0x10];
11143  
11144  	u8         reserved_at_40[0x17];
11145  	u8         component_status[0x5];
11146  	u8         component_update_state[0x4];
11147  
11148  	u8         last_update_state_changer_type[0x4];
11149  	u8         last_update_state_changer_host_id[0x4];
11150  	u8         reserved_at_68[0x18];
11151  };
11152  
11153  struct mlx5_ifc_mcqi_cap_bits {
11154  	u8         supported_info_bitmask[0x20];
11155  
11156  	u8         component_size[0x20];
11157  
11158  	u8         max_component_size[0x20];
11159  
11160  	u8         log_mcda_word_size[0x4];
11161  	u8         reserved_at_64[0xc];
11162  	u8         mcda_max_write_size[0x10];
11163  
11164  	u8         rd_en[0x1];
11165  	u8         reserved_at_81[0x1];
11166  	u8         match_chip_id[0x1];
11167  	u8         match_psid[0x1];
11168  	u8         check_user_timestamp[0x1];
11169  	u8         match_base_guid_mac[0x1];
11170  	u8         reserved_at_86[0x1a];
11171  };
11172  
11173  struct mlx5_ifc_mcqi_version_bits {
11174  	u8         reserved_at_0[0x2];
11175  	u8         build_time_valid[0x1];
11176  	u8         user_defined_time_valid[0x1];
11177  	u8         reserved_at_4[0x14];
11178  	u8         version_string_length[0x8];
11179  
11180  	u8         version[0x20];
11181  
11182  	u8         build_time[0x40];
11183  
11184  	u8         user_defined_time[0x40];
11185  
11186  	u8         build_tool_version[0x20];
11187  
11188  	u8         reserved_at_e0[0x20];
11189  
11190  	u8         version_string[92][0x8];
11191  };
11192  
11193  struct mlx5_ifc_mcqi_activation_method_bits {
11194  	u8         pending_server_ac_power_cycle[0x1];
11195  	u8         pending_server_dc_power_cycle[0x1];
11196  	u8         pending_server_reboot[0x1];
11197  	u8         pending_fw_reset[0x1];
11198  	u8         auto_activate[0x1];
11199  	u8         all_hosts_sync[0x1];
11200  	u8         device_hw_reset[0x1];
11201  	u8         reserved_at_7[0x19];
11202  };
11203  
11204  union mlx5_ifc_mcqi_reg_data_bits {
11205  	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11206  	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11207  	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11208  };
11209  
11210  struct mlx5_ifc_mcqi_reg_bits {
11211  	u8         read_pending_component[0x1];
11212  	u8         reserved_at_1[0xf];
11213  	u8         component_index[0x10];
11214  
11215  	u8         reserved_at_20[0x20];
11216  
11217  	u8         reserved_at_40[0x1b];
11218  	u8         info_type[0x5];
11219  
11220  	u8         info_size[0x20];
11221  
11222  	u8         offset[0x20];
11223  
11224  	u8         reserved_at_a0[0x10];
11225  	u8         data_size[0x10];
11226  
11227  	union mlx5_ifc_mcqi_reg_data_bits data[];
11228  };
11229  
11230  struct mlx5_ifc_mcc_reg_bits {
11231  	u8         reserved_at_0[0x4];
11232  	u8         time_elapsed_since_last_cmd[0xc];
11233  	u8         reserved_at_10[0x8];
11234  	u8         instruction[0x8];
11235  
11236  	u8         reserved_at_20[0x10];
11237  	u8         component_index[0x10];
11238  
11239  	u8         reserved_at_40[0x8];
11240  	u8         update_handle[0x18];
11241  
11242  	u8         handle_owner_type[0x4];
11243  	u8         handle_owner_host_id[0x4];
11244  	u8         reserved_at_68[0x1];
11245  	u8         control_progress[0x7];
11246  	u8         error_code[0x8];
11247  	u8         reserved_at_78[0x4];
11248  	u8         control_state[0x4];
11249  
11250  	u8         component_size[0x20];
11251  
11252  	u8         reserved_at_a0[0x60];
11253  };
11254  
11255  struct mlx5_ifc_mcda_reg_bits {
11256  	u8         reserved_at_0[0x8];
11257  	u8         update_handle[0x18];
11258  
11259  	u8         offset[0x20];
11260  
11261  	u8         reserved_at_40[0x10];
11262  	u8         size[0x10];
11263  
11264  	u8         reserved_at_60[0x20];
11265  
11266  	u8         data[][0x20];
11267  };
11268  
11269  enum {
11270  	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11271  	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11272  };
11273  
11274  enum {
11275  	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11276  	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11277  	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11278  	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11279  	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11280  	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11281  };
11282  
11283  enum {
11284  	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11285  	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11286  };
11287  
11288  enum {
11289  	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11290  	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11291  	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11292  };
11293  
11294  struct mlx5_ifc_mfrl_reg_bits {
11295  	u8         reserved_at_0[0x20];
11296  
11297  	u8         reserved_at_20[0x2];
11298  	u8         pci_sync_for_fw_update_start[0x1];
11299  	u8         pci_sync_for_fw_update_resp[0x2];
11300  	u8         rst_type_sel[0x3];
11301  	u8         pci_reset_req_method[0x3];
11302  	u8         reserved_at_2b[0x1];
11303  	u8         reset_state[0x4];
11304  	u8         reset_type[0x8];
11305  	u8         reset_level[0x8];
11306  };
11307  
11308  struct mlx5_ifc_mirc_reg_bits {
11309  	u8         reserved_at_0[0x18];
11310  	u8         status_code[0x8];
11311  
11312  	u8         reserved_at_20[0x20];
11313  };
11314  
11315  struct mlx5_ifc_pddr_monitor_opcode_bits {
11316  	u8         reserved_at_0[0x10];
11317  	u8         monitor_opcode[0x10];
11318  };
11319  
11320  union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11321  	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11322  	u8         reserved_at_0[0x20];
11323  };
11324  
11325  enum {
11326  	/* Monitor opcodes */
11327  	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11328  };
11329  
11330  struct mlx5_ifc_pddr_troubleshooting_page_bits {
11331  	u8         reserved_at_0[0x10];
11332  	u8         group_opcode[0x10];
11333  
11334  	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11335  
11336  	u8         reserved_at_40[0x20];
11337  
11338  	u8         status_message[59][0x20];
11339  };
11340  
11341  union mlx5_ifc_pddr_reg_page_data_auto_bits {
11342  	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11343  	u8         reserved_at_0[0x7c0];
11344  };
11345  
11346  enum {
11347  	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11348  };
11349  
11350  struct mlx5_ifc_pddr_reg_bits {
11351  	u8         reserved_at_0[0x8];
11352  	u8         local_port[0x8];
11353  	u8         pnat[0x2];
11354  	u8         reserved_at_12[0xe];
11355  
11356  	u8         reserved_at_20[0x18];
11357  	u8         page_select[0x8];
11358  
11359  	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11360  };
11361  
11362  struct mlx5_ifc_mrtc_reg_bits {
11363  	u8         time_synced[0x1];
11364  	u8         reserved_at_1[0x1f];
11365  
11366  	u8         reserved_at_20[0x20];
11367  
11368  	u8         time_h[0x20];
11369  
11370  	u8         time_l[0x20];
11371  };
11372  
11373  struct mlx5_ifc_mtcap_reg_bits {
11374  	u8         reserved_at_0[0x19];
11375  	u8         sensor_count[0x7];
11376  
11377  	u8         reserved_at_20[0x20];
11378  
11379  	u8         sensor_map[0x40];
11380  };
11381  
11382  struct mlx5_ifc_mtmp_reg_bits {
11383  	u8         reserved_at_0[0x14];
11384  	u8         sensor_index[0xc];
11385  
11386  	u8         reserved_at_20[0x10];
11387  	u8         temperature[0x10];
11388  
11389  	u8         mte[0x1];
11390  	u8         mtr[0x1];
11391  	u8         reserved_at_42[0xe];
11392  	u8         max_temperature[0x10];
11393  
11394  	u8         tee[0x2];
11395  	u8         reserved_at_62[0xe];
11396  	u8         temp_threshold_hi[0x10];
11397  
11398  	u8         reserved_at_80[0x10];
11399  	u8         temp_threshold_lo[0x10];
11400  
11401  	u8         reserved_at_a0[0x20];
11402  
11403  	u8         sensor_name_hi[0x20];
11404  	u8         sensor_name_lo[0x20];
11405  };
11406  
11407  struct mlx5_ifc_mtptm_reg_bits {
11408  	u8         reserved_at_0[0x10];
11409  	u8         psta[0x1];
11410  	u8         reserved_at_11[0xf];
11411  
11412  	u8         reserved_at_20[0x60];
11413  };
11414  
11415  enum {
11416  	MLX5_MTCTR_REQUEST_NOP = 0x0,
11417  	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11418  	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11419  	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11420  };
11421  
11422  struct mlx5_ifc_mtctr_reg_bits {
11423  	u8         first_clock_timestamp_request[0x8];
11424  	u8         second_clock_timestamp_request[0x8];
11425  	u8         reserved_at_10[0x10];
11426  
11427  	u8         first_clock_valid[0x1];
11428  	u8         second_clock_valid[0x1];
11429  	u8         reserved_at_22[0x1e];
11430  
11431  	u8         first_clock_timestamp[0x40];
11432  	u8         second_clock_timestamp[0x40];
11433  };
11434  
11435  union mlx5_ifc_ports_control_registers_document_bits {
11436  	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11437  	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11438  	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11439  	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11440  	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11441  	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11442  	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11443  	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11444  	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11445  	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11446  	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11447  	struct mlx5_ifc_paos_reg_bits paos_reg;
11448  	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11449  	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11450  	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11451  	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11452  	struct mlx5_ifc_peir_reg_bits peir_reg;
11453  	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11454  	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11455  	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11456  	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11457  	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11458  	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11459  	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11460  	struct mlx5_ifc_plib_reg_bits plib_reg;
11461  	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11462  	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11463  	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11464  	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11465  	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11466  	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11467  	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11468  	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11469  	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11470  	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11471  	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11472  	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11473  	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11474  	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11475  	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11476  	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11477  	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11478  	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11479  	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11480  	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11481  	struct mlx5_ifc_pude_reg_bits pude_reg;
11482  	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11483  	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11484  	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11485  	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11486  	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11487  	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11488  	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11489  	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11490  	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11491  	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11492  	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11493  	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11494  	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11495  	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11496  	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11497  	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11498  	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11499  	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11500  	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11501  	u8         reserved_at_0[0x60e0];
11502  };
11503  
11504  union mlx5_ifc_debug_enhancements_document_bits {
11505  	struct mlx5_ifc_health_buffer_bits health_buffer;
11506  	u8         reserved_at_0[0x200];
11507  };
11508  
11509  union mlx5_ifc_uplink_pci_interface_document_bits {
11510  	struct mlx5_ifc_initial_seg_bits initial_seg;
11511  	u8         reserved_at_0[0x20060];
11512  };
11513  
11514  struct mlx5_ifc_set_flow_table_root_out_bits {
11515  	u8         status[0x8];
11516  	u8         reserved_at_8[0x18];
11517  
11518  	u8         syndrome[0x20];
11519  
11520  	u8         reserved_at_40[0x40];
11521  };
11522  
11523  struct mlx5_ifc_set_flow_table_root_in_bits {
11524  	u8         opcode[0x10];
11525  	u8         reserved_at_10[0x10];
11526  
11527  	u8         reserved_at_20[0x10];
11528  	u8         op_mod[0x10];
11529  
11530  	u8         other_vport[0x1];
11531  	u8         reserved_at_41[0xf];
11532  	u8         vport_number[0x10];
11533  
11534  	u8         reserved_at_60[0x20];
11535  
11536  	u8         table_type[0x8];
11537  	u8         reserved_at_88[0x7];
11538  	u8         table_of_other_vport[0x1];
11539  	u8         table_vport_number[0x10];
11540  
11541  	u8         reserved_at_a0[0x8];
11542  	u8         table_id[0x18];
11543  
11544  	u8         reserved_at_c0[0x8];
11545  	u8         underlay_qpn[0x18];
11546  	u8         table_eswitch_owner_vhca_id_valid[0x1];
11547  	u8         reserved_at_e1[0xf];
11548  	u8         table_eswitch_owner_vhca_id[0x10];
11549  	u8         reserved_at_100[0x100];
11550  };
11551  
11552  enum {
11553  	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11554  	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11555  };
11556  
11557  struct mlx5_ifc_modify_flow_table_out_bits {
11558  	u8         status[0x8];
11559  	u8         reserved_at_8[0x18];
11560  
11561  	u8         syndrome[0x20];
11562  
11563  	u8         reserved_at_40[0x40];
11564  };
11565  
11566  struct mlx5_ifc_modify_flow_table_in_bits {
11567  	u8         opcode[0x10];
11568  	u8         reserved_at_10[0x10];
11569  
11570  	u8         reserved_at_20[0x10];
11571  	u8         op_mod[0x10];
11572  
11573  	u8         other_vport[0x1];
11574  	u8         reserved_at_41[0xf];
11575  	u8         vport_number[0x10];
11576  
11577  	u8         reserved_at_60[0x10];
11578  	u8         modify_field_select[0x10];
11579  
11580  	u8         table_type[0x8];
11581  	u8         reserved_at_88[0x18];
11582  
11583  	u8         reserved_at_a0[0x8];
11584  	u8         table_id[0x18];
11585  
11586  	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11587  };
11588  
11589  struct mlx5_ifc_ets_tcn_config_reg_bits {
11590  	u8         g[0x1];
11591  	u8         b[0x1];
11592  	u8         r[0x1];
11593  	u8         reserved_at_3[0x9];
11594  	u8         group[0x4];
11595  	u8         reserved_at_10[0x9];
11596  	u8         bw_allocation[0x7];
11597  
11598  	u8         reserved_at_20[0xc];
11599  	u8         max_bw_units[0x4];
11600  	u8         reserved_at_30[0x8];
11601  	u8         max_bw_value[0x8];
11602  };
11603  
11604  struct mlx5_ifc_ets_global_config_reg_bits {
11605  	u8         reserved_at_0[0x2];
11606  	u8         r[0x1];
11607  	u8         reserved_at_3[0x1d];
11608  
11609  	u8         reserved_at_20[0xc];
11610  	u8         max_bw_units[0x4];
11611  	u8         reserved_at_30[0x8];
11612  	u8         max_bw_value[0x8];
11613  };
11614  
11615  struct mlx5_ifc_qetc_reg_bits {
11616  	u8                                         reserved_at_0[0x8];
11617  	u8                                         port_number[0x8];
11618  	u8                                         reserved_at_10[0x30];
11619  
11620  	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11621  	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11622  };
11623  
11624  struct mlx5_ifc_qpdpm_dscp_reg_bits {
11625  	u8         e[0x1];
11626  	u8         reserved_at_01[0x0b];
11627  	u8         prio[0x04];
11628  };
11629  
11630  struct mlx5_ifc_qpdpm_reg_bits {
11631  	u8                                     reserved_at_0[0x8];
11632  	u8                                     local_port[0x8];
11633  	u8                                     reserved_at_10[0x10];
11634  	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11635  };
11636  
11637  struct mlx5_ifc_qpts_reg_bits {
11638  	u8         reserved_at_0[0x8];
11639  	u8         local_port[0x8];
11640  	u8         reserved_at_10[0x2d];
11641  	u8         trust_state[0x3];
11642  };
11643  
11644  struct mlx5_ifc_pptb_reg_bits {
11645  	u8         reserved_at_0[0x2];
11646  	u8         mm[0x2];
11647  	u8         reserved_at_4[0x4];
11648  	u8         local_port[0x8];
11649  	u8         reserved_at_10[0x6];
11650  	u8         cm[0x1];
11651  	u8         um[0x1];
11652  	u8         pm[0x8];
11653  
11654  	u8         prio_x_buff[0x20];
11655  
11656  	u8         pm_msb[0x8];
11657  	u8         reserved_at_48[0x10];
11658  	u8         ctrl_buff[0x4];
11659  	u8         untagged_buff[0x4];
11660  };
11661  
11662  struct mlx5_ifc_sbcam_reg_bits {
11663  	u8         reserved_at_0[0x8];
11664  	u8         feature_group[0x8];
11665  	u8         reserved_at_10[0x8];
11666  	u8         access_reg_group[0x8];
11667  
11668  	u8         reserved_at_20[0x20];
11669  
11670  	u8         sb_access_reg_cap_mask[4][0x20];
11671  
11672  	u8         reserved_at_c0[0x80];
11673  
11674  	u8         sb_feature_cap_mask[4][0x20];
11675  
11676  	u8         reserved_at_1c0[0x40];
11677  
11678  	u8         cap_total_buffer_size[0x20];
11679  
11680  	u8         cap_cell_size[0x10];
11681  	u8         cap_max_pg_buffers[0x8];
11682  	u8         cap_num_pool_supported[0x8];
11683  
11684  	u8         reserved_at_240[0x8];
11685  	u8         cap_sbsr_stat_size[0x8];
11686  	u8         cap_max_tclass_data[0x8];
11687  	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11688  };
11689  
11690  struct mlx5_ifc_pbmc_reg_bits {
11691  	u8         reserved_at_0[0x8];
11692  	u8         local_port[0x8];
11693  	u8         reserved_at_10[0x10];
11694  
11695  	u8         xoff_timer_value[0x10];
11696  	u8         xoff_refresh[0x10];
11697  
11698  	u8         reserved_at_40[0x9];
11699  	u8         fullness_threshold[0x7];
11700  	u8         port_buffer_size[0x10];
11701  
11702  	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11703  
11704  	u8         reserved_at_2e0[0x80];
11705  };
11706  
11707  struct mlx5_ifc_sbpr_reg_bits {
11708  	u8         desc[0x1];
11709  	u8         snap[0x1];
11710  	u8         reserved_at_2[0x4];
11711  	u8         dir[0x2];
11712  	u8         reserved_at_8[0x14];
11713  	u8         pool[0x4];
11714  
11715  	u8         infi_size[0x1];
11716  	u8         reserved_at_21[0x7];
11717  	u8         size[0x18];
11718  
11719  	u8         reserved_at_40[0x1c];
11720  	u8         mode[0x4];
11721  
11722  	u8         reserved_at_60[0x8];
11723  	u8         buff_occupancy[0x18];
11724  
11725  	u8         clr[0x1];
11726  	u8         reserved_at_81[0x7];
11727  	u8         max_buff_occupancy[0x18];
11728  
11729  	u8         reserved_at_a0[0x8];
11730  	u8         ext_buff_occupancy[0x18];
11731  };
11732  
11733  struct mlx5_ifc_sbcm_reg_bits {
11734  	u8         desc[0x1];
11735  	u8         snap[0x1];
11736  	u8         reserved_at_2[0x6];
11737  	u8         local_port[0x8];
11738  	u8         pnat[0x2];
11739  	u8         pg_buff[0x6];
11740  	u8         reserved_at_18[0x6];
11741  	u8         dir[0x2];
11742  
11743  	u8         reserved_at_20[0x1f];
11744  	u8         exc[0x1];
11745  
11746  	u8         reserved_at_40[0x40];
11747  
11748  	u8         reserved_at_80[0x8];
11749  	u8         buff_occupancy[0x18];
11750  
11751  	u8         clr[0x1];
11752  	u8         reserved_at_a1[0x7];
11753  	u8         max_buff_occupancy[0x18];
11754  
11755  	u8         reserved_at_c0[0x8];
11756  	u8         min_buff[0x18];
11757  
11758  	u8         infi_max[0x1];
11759  	u8         reserved_at_e1[0x7];
11760  	u8         max_buff[0x18];
11761  
11762  	u8         reserved_at_100[0x20];
11763  
11764  	u8         reserved_at_120[0x1c];
11765  	u8         pool[0x4];
11766  };
11767  
11768  struct mlx5_ifc_qtct_reg_bits {
11769  	u8         reserved_at_0[0x8];
11770  	u8         port_number[0x8];
11771  	u8         reserved_at_10[0xd];
11772  	u8         prio[0x3];
11773  
11774  	u8         reserved_at_20[0x1d];
11775  	u8         tclass[0x3];
11776  };
11777  
11778  struct mlx5_ifc_mcia_reg_bits {
11779  	u8         l[0x1];
11780  	u8         reserved_at_1[0x7];
11781  	u8         module[0x8];
11782  	u8         reserved_at_10[0x8];
11783  	u8         status[0x8];
11784  
11785  	u8         i2c_device_address[0x8];
11786  	u8         page_number[0x8];
11787  	u8         device_address[0x10];
11788  
11789  	u8         reserved_at_40[0x10];
11790  	u8         size[0x10];
11791  
11792  	u8         reserved_at_60[0x20];
11793  
11794  	u8         dword_0[0x20];
11795  	u8         dword_1[0x20];
11796  	u8         dword_2[0x20];
11797  	u8         dword_3[0x20];
11798  	u8         dword_4[0x20];
11799  	u8         dword_5[0x20];
11800  	u8         dword_6[0x20];
11801  	u8         dword_7[0x20];
11802  	u8         dword_8[0x20];
11803  	u8         dword_9[0x20];
11804  	u8         dword_10[0x20];
11805  	u8         dword_11[0x20];
11806  };
11807  
11808  struct mlx5_ifc_dcbx_param_bits {
11809  	u8         dcbx_cee_cap[0x1];
11810  	u8         dcbx_ieee_cap[0x1];
11811  	u8         dcbx_standby_cap[0x1];
11812  	u8         reserved_at_3[0x5];
11813  	u8         port_number[0x8];
11814  	u8         reserved_at_10[0xa];
11815  	u8         max_application_table_size[6];
11816  	u8         reserved_at_20[0x15];
11817  	u8         version_oper[0x3];
11818  	u8         reserved_at_38[5];
11819  	u8         version_admin[0x3];
11820  	u8         willing_admin[0x1];
11821  	u8         reserved_at_41[0x3];
11822  	u8         pfc_cap_oper[0x4];
11823  	u8         reserved_at_48[0x4];
11824  	u8         pfc_cap_admin[0x4];
11825  	u8         reserved_at_50[0x4];
11826  	u8         num_of_tc_oper[0x4];
11827  	u8         reserved_at_58[0x4];
11828  	u8         num_of_tc_admin[0x4];
11829  	u8         remote_willing[0x1];
11830  	u8         reserved_at_61[3];
11831  	u8         remote_pfc_cap[4];
11832  	u8         reserved_at_68[0x14];
11833  	u8         remote_num_of_tc[0x4];
11834  	u8         reserved_at_80[0x18];
11835  	u8         error[0x8];
11836  	u8         reserved_at_a0[0x160];
11837  };
11838  
11839  enum {
11840  	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11841  	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11842  	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11843  };
11844  
11845  struct mlx5_ifc_lagc_bits {
11846  	u8         fdb_selection_mode[0x1];
11847  	u8         reserved_at_1[0x14];
11848  	u8         port_select_mode[0x3];
11849  	u8         reserved_at_18[0x5];
11850  	u8         lag_state[0x3];
11851  
11852  	u8         reserved_at_20[0xc];
11853  	u8         active_port[0x4];
11854  	u8         reserved_at_30[0x4];
11855  	u8         tx_remap_affinity_2[0x4];
11856  	u8         reserved_at_38[0x4];
11857  	u8         tx_remap_affinity_1[0x4];
11858  };
11859  
11860  struct mlx5_ifc_create_lag_out_bits {
11861  	u8         status[0x8];
11862  	u8         reserved_at_8[0x18];
11863  
11864  	u8         syndrome[0x20];
11865  
11866  	u8         reserved_at_40[0x40];
11867  };
11868  
11869  struct mlx5_ifc_create_lag_in_bits {
11870  	u8         opcode[0x10];
11871  	u8         reserved_at_10[0x10];
11872  
11873  	u8         reserved_at_20[0x10];
11874  	u8         op_mod[0x10];
11875  
11876  	struct mlx5_ifc_lagc_bits ctx;
11877  };
11878  
11879  struct mlx5_ifc_modify_lag_out_bits {
11880  	u8         status[0x8];
11881  	u8         reserved_at_8[0x18];
11882  
11883  	u8         syndrome[0x20];
11884  
11885  	u8         reserved_at_40[0x40];
11886  };
11887  
11888  struct mlx5_ifc_modify_lag_in_bits {
11889  	u8         opcode[0x10];
11890  	u8         reserved_at_10[0x10];
11891  
11892  	u8         reserved_at_20[0x10];
11893  	u8         op_mod[0x10];
11894  
11895  	u8         reserved_at_40[0x20];
11896  	u8         field_select[0x20];
11897  
11898  	struct mlx5_ifc_lagc_bits ctx;
11899  };
11900  
11901  struct mlx5_ifc_query_lag_out_bits {
11902  	u8         status[0x8];
11903  	u8         reserved_at_8[0x18];
11904  
11905  	u8         syndrome[0x20];
11906  
11907  	struct mlx5_ifc_lagc_bits ctx;
11908  };
11909  
11910  struct mlx5_ifc_query_lag_in_bits {
11911  	u8         opcode[0x10];
11912  	u8         reserved_at_10[0x10];
11913  
11914  	u8         reserved_at_20[0x10];
11915  	u8         op_mod[0x10];
11916  
11917  	u8         reserved_at_40[0x40];
11918  };
11919  
11920  struct mlx5_ifc_destroy_lag_out_bits {
11921  	u8         status[0x8];
11922  	u8         reserved_at_8[0x18];
11923  
11924  	u8         syndrome[0x20];
11925  
11926  	u8         reserved_at_40[0x40];
11927  };
11928  
11929  struct mlx5_ifc_destroy_lag_in_bits {
11930  	u8         opcode[0x10];
11931  	u8         reserved_at_10[0x10];
11932  
11933  	u8         reserved_at_20[0x10];
11934  	u8         op_mod[0x10];
11935  
11936  	u8         reserved_at_40[0x40];
11937  };
11938  
11939  struct mlx5_ifc_create_vport_lag_out_bits {
11940  	u8         status[0x8];
11941  	u8         reserved_at_8[0x18];
11942  
11943  	u8         syndrome[0x20];
11944  
11945  	u8         reserved_at_40[0x40];
11946  };
11947  
11948  struct mlx5_ifc_create_vport_lag_in_bits {
11949  	u8         opcode[0x10];
11950  	u8         reserved_at_10[0x10];
11951  
11952  	u8         reserved_at_20[0x10];
11953  	u8         op_mod[0x10];
11954  
11955  	u8         reserved_at_40[0x40];
11956  };
11957  
11958  struct mlx5_ifc_destroy_vport_lag_out_bits {
11959  	u8         status[0x8];
11960  	u8         reserved_at_8[0x18];
11961  
11962  	u8         syndrome[0x20];
11963  
11964  	u8         reserved_at_40[0x40];
11965  };
11966  
11967  struct mlx5_ifc_destroy_vport_lag_in_bits {
11968  	u8         opcode[0x10];
11969  	u8         reserved_at_10[0x10];
11970  
11971  	u8         reserved_at_20[0x10];
11972  	u8         op_mod[0x10];
11973  
11974  	u8         reserved_at_40[0x40];
11975  };
11976  
11977  enum {
11978  	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11979  	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11980  };
11981  
11982  struct mlx5_ifc_modify_memic_in_bits {
11983  	u8         opcode[0x10];
11984  	u8         uid[0x10];
11985  
11986  	u8         reserved_at_20[0x10];
11987  	u8         op_mod[0x10];
11988  
11989  	u8         reserved_at_40[0x20];
11990  
11991  	u8         reserved_at_60[0x18];
11992  	u8         memic_operation_type[0x8];
11993  
11994  	u8         memic_start_addr[0x40];
11995  
11996  	u8         reserved_at_c0[0x140];
11997  };
11998  
11999  struct mlx5_ifc_modify_memic_out_bits {
12000  	u8         status[0x8];
12001  	u8         reserved_at_8[0x18];
12002  
12003  	u8         syndrome[0x20];
12004  
12005  	u8         reserved_at_40[0x40];
12006  
12007  	u8         memic_operation_addr[0x40];
12008  
12009  	u8         reserved_at_c0[0x140];
12010  };
12011  
12012  struct mlx5_ifc_alloc_memic_in_bits {
12013  	u8         opcode[0x10];
12014  	u8         reserved_at_10[0x10];
12015  
12016  	u8         reserved_at_20[0x10];
12017  	u8         op_mod[0x10];
12018  
12019  	u8         reserved_at_30[0x20];
12020  
12021  	u8	   reserved_at_40[0x18];
12022  	u8	   log_memic_addr_alignment[0x8];
12023  
12024  	u8         range_start_addr[0x40];
12025  
12026  	u8         range_size[0x20];
12027  
12028  	u8         memic_size[0x20];
12029  };
12030  
12031  struct mlx5_ifc_alloc_memic_out_bits {
12032  	u8         status[0x8];
12033  	u8         reserved_at_8[0x18];
12034  
12035  	u8         syndrome[0x20];
12036  
12037  	u8         memic_start_addr[0x40];
12038  };
12039  
12040  struct mlx5_ifc_dealloc_memic_in_bits {
12041  	u8         opcode[0x10];
12042  	u8         reserved_at_10[0x10];
12043  
12044  	u8         reserved_at_20[0x10];
12045  	u8         op_mod[0x10];
12046  
12047  	u8         reserved_at_40[0x40];
12048  
12049  	u8         memic_start_addr[0x40];
12050  
12051  	u8         memic_size[0x20];
12052  
12053  	u8         reserved_at_e0[0x20];
12054  };
12055  
12056  struct mlx5_ifc_dealloc_memic_out_bits {
12057  	u8         status[0x8];
12058  	u8         reserved_at_8[0x18];
12059  
12060  	u8         syndrome[0x20];
12061  
12062  	u8         reserved_at_40[0x40];
12063  };
12064  
12065  struct mlx5_ifc_umem_bits {
12066  	u8         reserved_at_0[0x80];
12067  
12068  	u8         ats[0x1];
12069  	u8         reserved_at_81[0x1a];
12070  	u8         log_page_size[0x5];
12071  
12072  	u8         page_offset[0x20];
12073  
12074  	u8         num_of_mtt[0x40];
12075  
12076  	struct mlx5_ifc_mtt_bits  mtt[];
12077  };
12078  
12079  struct mlx5_ifc_uctx_bits {
12080  	u8         cap[0x20];
12081  
12082  	u8         reserved_at_20[0x160];
12083  };
12084  
12085  struct mlx5_ifc_sw_icm_bits {
12086  	u8         modify_field_select[0x40];
12087  
12088  	u8	   reserved_at_40[0x18];
12089  	u8         log_sw_icm_size[0x8];
12090  
12091  	u8         reserved_at_60[0x20];
12092  
12093  	u8         sw_icm_start_addr[0x40];
12094  
12095  	u8         reserved_at_c0[0x140];
12096  };
12097  
12098  struct mlx5_ifc_geneve_tlv_option_bits {
12099  	u8         modify_field_select[0x40];
12100  
12101  	u8         reserved_at_40[0x18];
12102  	u8         geneve_option_fte_index[0x8];
12103  
12104  	u8         option_class[0x10];
12105  	u8         option_type[0x8];
12106  	u8         reserved_at_78[0x3];
12107  	u8         option_data_length[0x5];
12108  
12109  	u8         reserved_at_80[0x180];
12110  };
12111  
12112  struct mlx5_ifc_create_umem_in_bits {
12113  	u8         opcode[0x10];
12114  	u8         uid[0x10];
12115  
12116  	u8         reserved_at_20[0x10];
12117  	u8         op_mod[0x10];
12118  
12119  	u8         reserved_at_40[0x40];
12120  
12121  	struct mlx5_ifc_umem_bits  umem;
12122  };
12123  
12124  struct mlx5_ifc_create_umem_out_bits {
12125  	u8         status[0x8];
12126  	u8         reserved_at_8[0x18];
12127  
12128  	u8         syndrome[0x20];
12129  
12130  	u8         reserved_at_40[0x8];
12131  	u8         umem_id[0x18];
12132  
12133  	u8         reserved_at_60[0x20];
12134  };
12135  
12136  struct mlx5_ifc_destroy_umem_in_bits {
12137  	u8        opcode[0x10];
12138  	u8        uid[0x10];
12139  
12140  	u8        reserved_at_20[0x10];
12141  	u8        op_mod[0x10];
12142  
12143  	u8        reserved_at_40[0x8];
12144  	u8        umem_id[0x18];
12145  
12146  	u8        reserved_at_60[0x20];
12147  };
12148  
12149  struct mlx5_ifc_destroy_umem_out_bits {
12150  	u8        status[0x8];
12151  	u8        reserved_at_8[0x18];
12152  
12153  	u8        syndrome[0x20];
12154  
12155  	u8        reserved_at_40[0x40];
12156  };
12157  
12158  struct mlx5_ifc_create_uctx_in_bits {
12159  	u8         opcode[0x10];
12160  	u8         reserved_at_10[0x10];
12161  
12162  	u8         reserved_at_20[0x10];
12163  	u8         op_mod[0x10];
12164  
12165  	u8         reserved_at_40[0x40];
12166  
12167  	struct mlx5_ifc_uctx_bits  uctx;
12168  };
12169  
12170  struct mlx5_ifc_create_uctx_out_bits {
12171  	u8         status[0x8];
12172  	u8         reserved_at_8[0x18];
12173  
12174  	u8         syndrome[0x20];
12175  
12176  	u8         reserved_at_40[0x10];
12177  	u8         uid[0x10];
12178  
12179  	u8         reserved_at_60[0x20];
12180  };
12181  
12182  struct mlx5_ifc_destroy_uctx_in_bits {
12183  	u8         opcode[0x10];
12184  	u8         reserved_at_10[0x10];
12185  
12186  	u8         reserved_at_20[0x10];
12187  	u8         op_mod[0x10];
12188  
12189  	u8         reserved_at_40[0x10];
12190  	u8         uid[0x10];
12191  
12192  	u8         reserved_at_60[0x20];
12193  };
12194  
12195  struct mlx5_ifc_destroy_uctx_out_bits {
12196  	u8         status[0x8];
12197  	u8         reserved_at_8[0x18];
12198  
12199  	u8         syndrome[0x20];
12200  
12201  	u8          reserved_at_40[0x40];
12202  };
12203  
12204  struct mlx5_ifc_create_sw_icm_in_bits {
12205  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12206  	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12207  };
12208  
12209  struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12210  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12211  	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12212  };
12213  
12214  struct mlx5_ifc_mtrc_string_db_param_bits {
12215  	u8         string_db_base_address[0x20];
12216  
12217  	u8         reserved_at_20[0x8];
12218  	u8         string_db_size[0x18];
12219  };
12220  
12221  struct mlx5_ifc_mtrc_cap_bits {
12222  	u8         trace_owner[0x1];
12223  	u8         trace_to_memory[0x1];
12224  	u8         reserved_at_2[0x4];
12225  	u8         trc_ver[0x2];
12226  	u8         reserved_at_8[0x14];
12227  	u8         num_string_db[0x4];
12228  
12229  	u8         first_string_trace[0x8];
12230  	u8         num_string_trace[0x8];
12231  	u8         reserved_at_30[0x28];
12232  
12233  	u8         log_max_trace_buffer_size[0x8];
12234  
12235  	u8         reserved_at_60[0x20];
12236  
12237  	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12238  
12239  	u8         reserved_at_280[0x180];
12240  };
12241  
12242  struct mlx5_ifc_mtrc_conf_bits {
12243  	u8         reserved_at_0[0x1c];
12244  	u8         trace_mode[0x4];
12245  	u8         reserved_at_20[0x18];
12246  	u8         log_trace_buffer_size[0x8];
12247  	u8         trace_mkey[0x20];
12248  	u8         reserved_at_60[0x3a0];
12249  };
12250  
12251  struct mlx5_ifc_mtrc_stdb_bits {
12252  	u8         string_db_index[0x4];
12253  	u8         reserved_at_4[0x4];
12254  	u8         read_size[0x18];
12255  	u8         start_offset[0x20];
12256  	u8         string_db_data[];
12257  };
12258  
12259  struct mlx5_ifc_mtrc_ctrl_bits {
12260  	u8         trace_status[0x2];
12261  	u8         reserved_at_2[0x2];
12262  	u8         arm_event[0x1];
12263  	u8         reserved_at_5[0xb];
12264  	u8         modify_field_select[0x10];
12265  	u8         reserved_at_20[0x2b];
12266  	u8         current_timestamp52_32[0x15];
12267  	u8         current_timestamp31_0[0x20];
12268  	u8         reserved_at_80[0x180];
12269  };
12270  
12271  struct mlx5_ifc_host_params_context_bits {
12272  	u8         host_number[0x8];
12273  	u8         reserved_at_8[0x7];
12274  	u8         host_pf_disabled[0x1];
12275  	u8         host_num_of_vfs[0x10];
12276  
12277  	u8         host_total_vfs[0x10];
12278  	u8         host_pci_bus[0x10];
12279  
12280  	u8         reserved_at_40[0x10];
12281  	u8         host_pci_device[0x10];
12282  
12283  	u8         reserved_at_60[0x10];
12284  	u8         host_pci_function[0x10];
12285  
12286  	u8         reserved_at_80[0x180];
12287  };
12288  
12289  struct mlx5_ifc_query_esw_functions_in_bits {
12290  	u8         opcode[0x10];
12291  	u8         reserved_at_10[0x10];
12292  
12293  	u8         reserved_at_20[0x10];
12294  	u8         op_mod[0x10];
12295  
12296  	u8         reserved_at_40[0x40];
12297  };
12298  
12299  struct mlx5_ifc_query_esw_functions_out_bits {
12300  	u8         status[0x8];
12301  	u8         reserved_at_8[0x18];
12302  
12303  	u8         syndrome[0x20];
12304  
12305  	u8         reserved_at_40[0x40];
12306  
12307  	struct mlx5_ifc_host_params_context_bits host_params_context;
12308  
12309  	u8         reserved_at_280[0x180];
12310  	u8         host_sf_enable[][0x40];
12311  };
12312  
12313  struct mlx5_ifc_sf_partition_bits {
12314  	u8         reserved_at_0[0x10];
12315  	u8         log_num_sf[0x8];
12316  	u8         log_sf_bar_size[0x8];
12317  };
12318  
12319  struct mlx5_ifc_query_sf_partitions_out_bits {
12320  	u8         status[0x8];
12321  	u8         reserved_at_8[0x18];
12322  
12323  	u8         syndrome[0x20];
12324  
12325  	u8         reserved_at_40[0x18];
12326  	u8         num_sf_partitions[0x8];
12327  
12328  	u8         reserved_at_60[0x20];
12329  
12330  	struct mlx5_ifc_sf_partition_bits sf_partition[];
12331  };
12332  
12333  struct mlx5_ifc_query_sf_partitions_in_bits {
12334  	u8         opcode[0x10];
12335  	u8         reserved_at_10[0x10];
12336  
12337  	u8         reserved_at_20[0x10];
12338  	u8         op_mod[0x10];
12339  
12340  	u8         reserved_at_40[0x40];
12341  };
12342  
12343  struct mlx5_ifc_dealloc_sf_out_bits {
12344  	u8         status[0x8];
12345  	u8         reserved_at_8[0x18];
12346  
12347  	u8         syndrome[0x20];
12348  
12349  	u8         reserved_at_40[0x40];
12350  };
12351  
12352  struct mlx5_ifc_dealloc_sf_in_bits {
12353  	u8         opcode[0x10];
12354  	u8         reserved_at_10[0x10];
12355  
12356  	u8         reserved_at_20[0x10];
12357  	u8         op_mod[0x10];
12358  
12359  	u8         reserved_at_40[0x10];
12360  	u8         function_id[0x10];
12361  
12362  	u8         reserved_at_60[0x20];
12363  };
12364  
12365  struct mlx5_ifc_alloc_sf_out_bits {
12366  	u8         status[0x8];
12367  	u8         reserved_at_8[0x18];
12368  
12369  	u8         syndrome[0x20];
12370  
12371  	u8         reserved_at_40[0x40];
12372  };
12373  
12374  struct mlx5_ifc_alloc_sf_in_bits {
12375  	u8         opcode[0x10];
12376  	u8         reserved_at_10[0x10];
12377  
12378  	u8         reserved_at_20[0x10];
12379  	u8         op_mod[0x10];
12380  
12381  	u8         reserved_at_40[0x10];
12382  	u8         function_id[0x10];
12383  
12384  	u8         reserved_at_60[0x20];
12385  };
12386  
12387  struct mlx5_ifc_affiliated_event_header_bits {
12388  	u8         reserved_at_0[0x10];
12389  	u8         obj_type[0x10];
12390  
12391  	u8         obj_id[0x20];
12392  };
12393  
12394  enum {
12395  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12396  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12397  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12398  	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12399  };
12400  
12401  enum {
12402  	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12403  	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12404  	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12405  	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12406  	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12407  	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12408  	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12409  };
12410  
12411  enum {
12412  	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12413  };
12414  
12415  enum {
12416  	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12417  	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12418  	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12419  	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12420  };
12421  
12422  enum {
12423  	MLX5_IPSEC_ASO_MODE              = 0x0,
12424  	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12425  	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12426  };
12427  
12428  enum {
12429  	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12430  	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12431  	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12432  	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12433  };
12434  
12435  struct mlx5_ifc_ipsec_aso_bits {
12436  	u8         valid[0x1];
12437  	u8         reserved_at_201[0x1];
12438  	u8         mode[0x2];
12439  	u8         window_sz[0x2];
12440  	u8         soft_lft_arm[0x1];
12441  	u8         hard_lft_arm[0x1];
12442  	u8         remove_flow_enable[0x1];
12443  	u8         esn_event_arm[0x1];
12444  	u8         reserved_at_20a[0x16];
12445  
12446  	u8         remove_flow_pkt_cnt[0x20];
12447  
12448  	u8         remove_flow_soft_lft[0x20];
12449  
12450  	u8         reserved_at_260[0x80];
12451  
12452  	u8         mode_parameter[0x20];
12453  
12454  	u8         replay_protection_window[0x100];
12455  };
12456  
12457  struct mlx5_ifc_ipsec_obj_bits {
12458  	u8         modify_field_select[0x40];
12459  	u8         full_offload[0x1];
12460  	u8         reserved_at_41[0x1];
12461  	u8         esn_en[0x1];
12462  	u8         esn_overlap[0x1];
12463  	u8         reserved_at_44[0x2];
12464  	u8         icv_length[0x2];
12465  	u8         reserved_at_48[0x4];
12466  	u8         aso_return_reg[0x4];
12467  	u8         reserved_at_50[0x10];
12468  
12469  	u8         esn_msb[0x20];
12470  
12471  	u8         reserved_at_80[0x8];
12472  	u8         dekn[0x18];
12473  
12474  	u8         salt[0x20];
12475  
12476  	u8         implicit_iv[0x40];
12477  
12478  	u8         reserved_at_100[0x8];
12479  	u8         ipsec_aso_access_pd[0x18];
12480  	u8         reserved_at_120[0xe0];
12481  
12482  	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12483  };
12484  
12485  struct mlx5_ifc_create_ipsec_obj_in_bits {
12486  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12487  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12488  };
12489  
12490  enum {
12491  	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12492  	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12493  };
12494  
12495  struct mlx5_ifc_query_ipsec_obj_out_bits {
12496  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12497  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12498  };
12499  
12500  struct mlx5_ifc_modify_ipsec_obj_in_bits {
12501  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12502  	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12503  };
12504  
12505  enum {
12506  	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12507  };
12508  
12509  enum {
12510  	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12511  	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12512  	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12513  	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12514  };
12515  
12516  #define MLX5_MACSEC_ASO_INC_SN  0x2
12517  #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12518  
12519  struct mlx5_ifc_macsec_aso_bits {
12520  	u8    valid[0x1];
12521  	u8    reserved_at_1[0x1];
12522  	u8    mode[0x2];
12523  	u8    window_size[0x2];
12524  	u8    soft_lifetime_arm[0x1];
12525  	u8    hard_lifetime_arm[0x1];
12526  	u8    remove_flow_enable[0x1];
12527  	u8    epn_event_arm[0x1];
12528  	u8    reserved_at_a[0x16];
12529  
12530  	u8    remove_flow_packet_count[0x20];
12531  
12532  	u8    remove_flow_soft_lifetime[0x20];
12533  
12534  	u8    reserved_at_60[0x80];
12535  
12536  	u8    mode_parameter[0x20];
12537  
12538  	u8    replay_protection_window[8][0x20];
12539  };
12540  
12541  struct mlx5_ifc_macsec_offload_obj_bits {
12542  	u8    modify_field_select[0x40];
12543  
12544  	u8    confidentiality_en[0x1];
12545  	u8    reserved_at_41[0x1];
12546  	u8    epn_en[0x1];
12547  	u8    epn_overlap[0x1];
12548  	u8    reserved_at_44[0x2];
12549  	u8    confidentiality_offset[0x2];
12550  	u8    reserved_at_48[0x4];
12551  	u8    aso_return_reg[0x4];
12552  	u8    reserved_at_50[0x10];
12553  
12554  	u8    epn_msb[0x20];
12555  
12556  	u8    reserved_at_80[0x8];
12557  	u8    dekn[0x18];
12558  
12559  	u8    reserved_at_a0[0x20];
12560  
12561  	u8    sci[0x40];
12562  
12563  	u8    reserved_at_100[0x8];
12564  	u8    macsec_aso_access_pd[0x18];
12565  
12566  	u8    reserved_at_120[0x60];
12567  
12568  	u8    salt[3][0x20];
12569  
12570  	u8    reserved_at_1e0[0x20];
12571  
12572  	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12573  };
12574  
12575  struct mlx5_ifc_create_macsec_obj_in_bits {
12576  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12577  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12578  };
12579  
12580  struct mlx5_ifc_modify_macsec_obj_in_bits {
12581  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12582  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12583  };
12584  
12585  enum {
12586  	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12587  	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12588  };
12589  
12590  struct mlx5_ifc_query_macsec_obj_out_bits {
12591  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12592  	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12593  };
12594  
12595  struct mlx5_ifc_wrapped_dek_bits {
12596  	u8         gcm_iv[0x60];
12597  
12598  	u8         reserved_at_60[0x20];
12599  
12600  	u8         const0[0x1];
12601  	u8         key_size[0x1];
12602  	u8         reserved_at_82[0x2];
12603  	u8         key2_invalid[0x1];
12604  	u8         reserved_at_85[0x3];
12605  	u8         pd[0x18];
12606  
12607  	u8         key_purpose[0x5];
12608  	u8         reserved_at_a5[0x13];
12609  	u8         kek_id[0x8];
12610  
12611  	u8         reserved_at_c0[0x40];
12612  
12613  	u8         key1[0x8][0x20];
12614  
12615  	u8         key2[0x8][0x20];
12616  
12617  	u8         reserved_at_300[0x40];
12618  
12619  	u8         const1[0x1];
12620  	u8         reserved_at_341[0x1f];
12621  
12622  	u8         reserved_at_360[0x20];
12623  
12624  	u8         auth_tag[0x80];
12625  };
12626  
12627  struct mlx5_ifc_encryption_key_obj_bits {
12628  	u8         modify_field_select[0x40];
12629  
12630  	u8         state[0x8];
12631  	u8         sw_wrapped[0x1];
12632  	u8         reserved_at_49[0xb];
12633  	u8         key_size[0x4];
12634  	u8         reserved_at_58[0x4];
12635  	u8         key_purpose[0x4];
12636  
12637  	u8         reserved_at_60[0x8];
12638  	u8         pd[0x18];
12639  
12640  	u8         reserved_at_80[0x100];
12641  
12642  	u8         opaque[0x40];
12643  
12644  	u8         reserved_at_1c0[0x40];
12645  
12646  	u8         key[8][0x80];
12647  
12648  	u8         sw_wrapped_dek[8][0x80];
12649  
12650  	u8         reserved_at_a00[0x600];
12651  };
12652  
12653  struct mlx5_ifc_create_encryption_key_in_bits {
12654  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12655  	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12656  };
12657  
12658  struct mlx5_ifc_modify_encryption_key_in_bits {
12659  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12660  	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12661  };
12662  
12663  enum {
12664  	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12665  	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12666  	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12667  	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12668  };
12669  
12670  struct mlx5_ifc_flow_meter_parameters_bits {
12671  	u8         valid[0x1];
12672  	u8         bucket_overflow[0x1];
12673  	u8         start_color[0x2];
12674  	u8         both_buckets_on_green[0x1];
12675  	u8         reserved_at_5[0x1];
12676  	u8         meter_mode[0x2];
12677  	u8         reserved_at_8[0x18];
12678  
12679  	u8         reserved_at_20[0x20];
12680  
12681  	u8         reserved_at_40[0x3];
12682  	u8         cbs_exponent[0x5];
12683  	u8         cbs_mantissa[0x8];
12684  	u8         reserved_at_50[0x3];
12685  	u8         cir_exponent[0x5];
12686  	u8         cir_mantissa[0x8];
12687  
12688  	u8         reserved_at_60[0x20];
12689  
12690  	u8         reserved_at_80[0x3];
12691  	u8         ebs_exponent[0x5];
12692  	u8         ebs_mantissa[0x8];
12693  	u8         reserved_at_90[0x3];
12694  	u8         eir_exponent[0x5];
12695  	u8         eir_mantissa[0x8];
12696  
12697  	u8         reserved_at_a0[0x60];
12698  };
12699  
12700  struct mlx5_ifc_flow_meter_aso_obj_bits {
12701  	u8         modify_field_select[0x40];
12702  
12703  	u8         reserved_at_40[0x40];
12704  
12705  	u8         reserved_at_80[0x8];
12706  	u8         meter_aso_access_pd[0x18];
12707  
12708  	u8         reserved_at_a0[0x160];
12709  
12710  	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12711  };
12712  
12713  struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12714  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12715  	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12716  };
12717  
12718  struct mlx5_ifc_int_kek_obj_bits {
12719  	u8         modify_field_select[0x40];
12720  
12721  	u8         state[0x8];
12722  	u8         auto_gen[0x1];
12723  	u8         reserved_at_49[0xb];
12724  	u8         key_size[0x4];
12725  	u8         reserved_at_58[0x8];
12726  
12727  	u8         reserved_at_60[0x8];
12728  	u8         pd[0x18];
12729  
12730  	u8         reserved_at_80[0x180];
12731  	u8         key[8][0x80];
12732  
12733  	u8         reserved_at_600[0x200];
12734  };
12735  
12736  struct mlx5_ifc_create_int_kek_obj_in_bits {
12737  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12738  	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12739  };
12740  
12741  struct mlx5_ifc_create_int_kek_obj_out_bits {
12742  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12743  	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12744  };
12745  
12746  struct mlx5_ifc_sampler_obj_bits {
12747  	u8         modify_field_select[0x40];
12748  
12749  	u8         table_type[0x8];
12750  	u8         level[0x8];
12751  	u8         reserved_at_50[0xf];
12752  	u8         ignore_flow_level[0x1];
12753  
12754  	u8         sample_ratio[0x20];
12755  
12756  	u8         reserved_at_80[0x8];
12757  	u8         sample_table_id[0x18];
12758  
12759  	u8         reserved_at_a0[0x8];
12760  	u8         default_table_id[0x18];
12761  
12762  	u8         sw_steering_icm_address_rx[0x40];
12763  	u8         sw_steering_icm_address_tx[0x40];
12764  
12765  	u8         reserved_at_140[0xa0];
12766  };
12767  
12768  struct mlx5_ifc_create_sampler_obj_in_bits {
12769  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12770  	struct mlx5_ifc_sampler_obj_bits sampler_object;
12771  };
12772  
12773  struct mlx5_ifc_query_sampler_obj_out_bits {
12774  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12775  	struct mlx5_ifc_sampler_obj_bits sampler_object;
12776  };
12777  
12778  enum {
12779  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12780  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12781  };
12782  
12783  enum {
12784  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12785  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12786  	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12787  };
12788  
12789  struct mlx5_ifc_tls_static_params_bits {
12790  	u8         const_2[0x2];
12791  	u8         tls_version[0x4];
12792  	u8         const_1[0x2];
12793  	u8         reserved_at_8[0x14];
12794  	u8         encryption_standard[0x4];
12795  
12796  	u8         reserved_at_20[0x20];
12797  
12798  	u8         initial_record_number[0x40];
12799  
12800  	u8         resync_tcp_sn[0x20];
12801  
12802  	u8         gcm_iv[0x20];
12803  
12804  	u8         implicit_iv[0x40];
12805  
12806  	u8         reserved_at_100[0x8];
12807  	u8         dek_index[0x18];
12808  
12809  	u8         reserved_at_120[0xe0];
12810  };
12811  
12812  struct mlx5_ifc_tls_progress_params_bits {
12813  	u8         next_record_tcp_sn[0x20];
12814  
12815  	u8         hw_resync_tcp_sn[0x20];
12816  
12817  	u8         record_tracker_state[0x2];
12818  	u8         auth_state[0x2];
12819  	u8         reserved_at_44[0x4];
12820  	u8         hw_offset_record_number[0x18];
12821  };
12822  
12823  enum {
12824  	MLX5_MTT_PERM_READ	= 1 << 0,
12825  	MLX5_MTT_PERM_WRITE	= 1 << 1,
12826  	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12827  };
12828  
12829  enum {
12830  	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12831  	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12832  };
12833  
12834  struct mlx5_ifc_suspend_vhca_in_bits {
12835  	u8         opcode[0x10];
12836  	u8         uid[0x10];
12837  
12838  	u8         reserved_at_20[0x10];
12839  	u8         op_mod[0x10];
12840  
12841  	u8         reserved_at_40[0x10];
12842  	u8         vhca_id[0x10];
12843  
12844  	u8         reserved_at_60[0x20];
12845  };
12846  
12847  struct mlx5_ifc_suspend_vhca_out_bits {
12848  	u8         status[0x8];
12849  	u8         reserved_at_8[0x18];
12850  
12851  	u8         syndrome[0x20];
12852  
12853  	u8         reserved_at_40[0x40];
12854  };
12855  
12856  enum {
12857  	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12858  	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12859  };
12860  
12861  struct mlx5_ifc_resume_vhca_in_bits {
12862  	u8         opcode[0x10];
12863  	u8         uid[0x10];
12864  
12865  	u8         reserved_at_20[0x10];
12866  	u8         op_mod[0x10];
12867  
12868  	u8         reserved_at_40[0x10];
12869  	u8         vhca_id[0x10];
12870  
12871  	u8         reserved_at_60[0x20];
12872  };
12873  
12874  struct mlx5_ifc_resume_vhca_out_bits {
12875  	u8         status[0x8];
12876  	u8         reserved_at_8[0x18];
12877  
12878  	u8         syndrome[0x20];
12879  
12880  	u8         reserved_at_40[0x40];
12881  };
12882  
12883  struct mlx5_ifc_query_vhca_migration_state_in_bits {
12884  	u8         opcode[0x10];
12885  	u8         uid[0x10];
12886  
12887  	u8         reserved_at_20[0x10];
12888  	u8         op_mod[0x10];
12889  
12890  	u8         incremental[0x1];
12891  	u8         chunk[0x1];
12892  	u8         reserved_at_42[0xe];
12893  	u8         vhca_id[0x10];
12894  
12895  	u8         reserved_at_60[0x20];
12896  };
12897  
12898  struct mlx5_ifc_query_vhca_migration_state_out_bits {
12899  	u8         status[0x8];
12900  	u8         reserved_at_8[0x18];
12901  
12902  	u8         syndrome[0x20];
12903  
12904  	u8         reserved_at_40[0x40];
12905  
12906  	u8         required_umem_size[0x20];
12907  
12908  	u8         reserved_at_a0[0x20];
12909  
12910  	u8         remaining_total_size[0x40];
12911  
12912  	u8         reserved_at_100[0x100];
12913  };
12914  
12915  struct mlx5_ifc_save_vhca_state_in_bits {
12916  	u8         opcode[0x10];
12917  	u8         uid[0x10];
12918  
12919  	u8         reserved_at_20[0x10];
12920  	u8         op_mod[0x10];
12921  
12922  	u8         incremental[0x1];
12923  	u8         set_track[0x1];
12924  	u8         reserved_at_42[0xe];
12925  	u8         vhca_id[0x10];
12926  
12927  	u8         reserved_at_60[0x20];
12928  
12929  	u8         va[0x40];
12930  
12931  	u8         mkey[0x20];
12932  
12933  	u8         size[0x20];
12934  };
12935  
12936  struct mlx5_ifc_save_vhca_state_out_bits {
12937  	u8         status[0x8];
12938  	u8         reserved_at_8[0x18];
12939  
12940  	u8         syndrome[0x20];
12941  
12942  	u8         actual_image_size[0x20];
12943  
12944  	u8         next_required_umem_size[0x20];
12945  };
12946  
12947  struct mlx5_ifc_load_vhca_state_in_bits {
12948  	u8         opcode[0x10];
12949  	u8         uid[0x10];
12950  
12951  	u8         reserved_at_20[0x10];
12952  	u8         op_mod[0x10];
12953  
12954  	u8         reserved_at_40[0x10];
12955  	u8         vhca_id[0x10];
12956  
12957  	u8         reserved_at_60[0x20];
12958  
12959  	u8         va[0x40];
12960  
12961  	u8         mkey[0x20];
12962  
12963  	u8         size[0x20];
12964  };
12965  
12966  struct mlx5_ifc_load_vhca_state_out_bits {
12967  	u8         status[0x8];
12968  	u8         reserved_at_8[0x18];
12969  
12970  	u8         syndrome[0x20];
12971  
12972  	u8         reserved_at_40[0x40];
12973  };
12974  
12975  struct mlx5_ifc_adv_virtualization_cap_bits {
12976  	u8         reserved_at_0[0x3];
12977  	u8         pg_track_log_max_num[0x5];
12978  	u8         pg_track_max_num_range[0x8];
12979  	u8         pg_track_log_min_addr_space[0x8];
12980  	u8         pg_track_log_max_addr_space[0x8];
12981  
12982  	u8         reserved_at_20[0x3];
12983  	u8         pg_track_log_min_msg_size[0x5];
12984  	u8         reserved_at_28[0x3];
12985  	u8         pg_track_log_max_msg_size[0x5];
12986  	u8         reserved_at_30[0x3];
12987  	u8         pg_track_log_min_page_size[0x5];
12988  	u8         reserved_at_38[0x3];
12989  	u8         pg_track_log_max_page_size[0x5];
12990  
12991  	u8         reserved_at_40[0x7c0];
12992  };
12993  
12994  struct mlx5_ifc_page_track_report_entry_bits {
12995  	u8         dirty_address_high[0x20];
12996  
12997  	u8         dirty_address_low[0x20];
12998  };
12999  
13000  enum {
13001  	MLX5_PAGE_TRACK_STATE_TRACKING,
13002  	MLX5_PAGE_TRACK_STATE_REPORTING,
13003  	MLX5_PAGE_TRACK_STATE_ERROR,
13004  };
13005  
13006  struct mlx5_ifc_page_track_range_bits {
13007  	u8         start_address[0x40];
13008  
13009  	u8         length[0x40];
13010  };
13011  
13012  struct mlx5_ifc_page_track_bits {
13013  	u8         modify_field_select[0x40];
13014  
13015  	u8         reserved_at_40[0x10];
13016  	u8         vhca_id[0x10];
13017  
13018  	u8         reserved_at_60[0x20];
13019  
13020  	u8         state[0x4];
13021  	u8         track_type[0x4];
13022  	u8         log_addr_space_size[0x8];
13023  	u8         reserved_at_90[0x3];
13024  	u8         log_page_size[0x5];
13025  	u8         reserved_at_98[0x3];
13026  	u8         log_msg_size[0x5];
13027  
13028  	u8         reserved_at_a0[0x8];
13029  	u8         reporting_qpn[0x18];
13030  
13031  	u8         reserved_at_c0[0x18];
13032  	u8         num_ranges[0x8];
13033  
13034  	u8         reserved_at_e0[0x20];
13035  
13036  	u8         range_start_address[0x40];
13037  
13038  	u8         length[0x40];
13039  
13040  	struct     mlx5_ifc_page_track_range_bits track_range[0];
13041  };
13042  
13043  struct mlx5_ifc_create_page_track_obj_in_bits {
13044  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13045  	struct mlx5_ifc_page_track_bits obj_context;
13046  };
13047  
13048  struct mlx5_ifc_modify_page_track_obj_in_bits {
13049  	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13050  	struct mlx5_ifc_page_track_bits obj_context;
13051  };
13052  
13053  struct mlx5_ifc_query_page_track_obj_out_bits {
13054  	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13055  	struct mlx5_ifc_page_track_bits obj_context;
13056  };
13057  
13058  struct mlx5_ifc_msecq_reg_bits {
13059  	u8         reserved_at_0[0x20];
13060  
13061  	u8         reserved_at_20[0x12];
13062  	u8         network_option[0x2];
13063  	u8         local_ssm_code[0x4];
13064  	u8         local_enhanced_ssm_code[0x8];
13065  
13066  	u8         local_clock_identity[0x40];
13067  
13068  	u8         reserved_at_80[0x180];
13069  };
13070  
13071  enum {
13072  	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13073  	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13074  	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13075  };
13076  
13077  enum mlx5_msees_admin_status {
13078  	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13079  	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13080  };
13081  
13082  enum mlx5_msees_oper_status {
13083  	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13084  	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13085  	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13086  	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13087  	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13088  	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13089  };
13090  
13091  enum mlx5_msees_failure_reason {
13092  	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13093  	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13094  	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13095  	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13096  	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13097  };
13098  
13099  struct mlx5_ifc_msees_reg_bits {
13100  	u8         reserved_at_0[0x8];
13101  	u8         local_port[0x8];
13102  	u8         pnat[0x2];
13103  	u8         lp_msb[0x2];
13104  	u8         reserved_at_14[0xc];
13105  
13106  	u8         field_select[0x20];
13107  
13108  	u8         admin_status[0x4];
13109  	u8         oper_status[0x4];
13110  	u8         ho_acq[0x1];
13111  	u8         reserved_at_49[0xc];
13112  	u8         admin_freq_measure[0x1];
13113  	u8         oper_freq_measure[0x1];
13114  	u8         failure_reason[0x9];
13115  
13116  	u8         frequency_diff[0x20];
13117  
13118  	u8         reserved_at_80[0x180];
13119  };
13120  
13121  #endif /* MLX5_IFC_H */
13122