| /linux-6.12.1/drivers/infiniband/hw/erdma/ |
| D | erdma_eq.c | 190 struct erdma_eq_cb *eqc = &dev->ceqs[ceqn]; in erdma_set_ceq_irq() local
193 snprintf(eqc->irq.name, ERDMA_IRQNAME_SIZE, "erdma-ceq%u@pci:%s", ceqn, in erdma_set_ceq_irq()
195 eqc->irq.msix_vector = pci_irq_vector(dev->pdev, ceqn + 1); in erdma_set_ceq_irq()
201 &eqc->irq.affinity_hint_mask); in erdma_set_ceq_irq()
203 err = request_irq(eqc->irq.msix_vector, erdma_intr_ceq_handler, 0, in erdma_set_ceq_irq()
204 eqc->irq.name, eqc); in erdma_set_ceq_irq()
210 irq_set_affinity_hint(eqc->irq.msix_vector, in erdma_set_ceq_irq()
211 &eqc->irq.affinity_hint_mask); in erdma_set_ceq_irq()
218 struct erdma_eq_cb *eqc = &dev->ceqs[ceqn]; in erdma_free_ceq_irq() local
220 irq_set_affinity_hint(eqc->irq.msix_vector, NULL); in erdma_free_ceq_irq()
[all …]
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| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/ |
| D | eq.c | 275 void *eqc; in create_map_eq() local
319 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); in create_map_eq()
320 MLX5_SET(eqc, eqc, log_eq_size, eq->fbc.log_sz); in create_map_eq()
321 MLX5_SET(eqc, eqc, uar_page, priv->uar->index); in create_map_eq()
322 MLX5_SET(eqc, eqc, intr, vecidx); in create_map_eq()
323 MLX5_SET(eqc, eqc, log_page_size, in create_map_eq()
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| D | debugfs.c | 408 param = 1 << MLX5_GET(eqc, ctx, log_eq_size); in eq_read_field()
411 param = MLX5_GET(eqc, ctx, intr); in eq_read_field()
414 param = MLX5_GET(eqc, ctx, log_page_size) + 12; in eq_read_field()
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| /linux-6.12.1/arch/s390/include/asm/ |
| D | eadm.h | 31 u8 eqc; member
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| /linux-6.12.1/drivers/infiniband/hw/hns/ |
| D | hns_roce_hw_v2.c | 6441 struct hns_roce_eq_context *eqc; in config_eqc() local
6445 eqc = mb_buf; in config_eqc()
6446 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); in config_eqc()
6460 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); in config_eqc()
6461 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); in config_eqc()
6462 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); in config_eqc()
6463 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); in config_eqc()
6464 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); in config_eqc()
6465 hr_reg_write(eqc, EQC_EQN, eq->eqn); in config_eqc()
6466 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); in config_eqc()
[all …]
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| /linux-6.12.1/drivers/crypto/hisilicon/ |
| D | debugfs.c | 246 struct qm_eqc eqc; in qm_eqc_aeqc_dump() local
260 xeqc = &eqc; in qm_eqc_aeqc_dump()
273 eqc.base_h = cpu_to_le32(QM_XQC_ADDR_MASK); in qm_eqc_aeqc_dump()
274 eqc.base_l = cpu_to_le32(QM_XQC_ADDR_MASK); in qm_eqc_aeqc_dump()
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| D | qm.c | 641 tmp_xqc = qm->xqc_buf.eqc; in qm_set_and_get_xqc()
2985 struct qm_eqc eqc = {0}; in qm_eq_ctx_cfg() local
2987 eqc.base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma)); in qm_eq_ctx_cfg()
2988 eqc.base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma)); in qm_eq_ctx_cfg()
2990 eqc.dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE); in qm_eq_ctx_cfg()
2991 eqc.dw6 = cpu_to_le32(((u32)qm->eq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT)); in qm_eq_ctx_cfg()
2993 return qm_set_and_get_xqc(qm, QM_MB_CMD_EQC, &eqc, 0, 0); in qm_eq_ctx_cfg()
5337 QM_XQC_BUF_INIT(xqc_buf, eqc); in hisi_qm_alloc_rsv_buf()
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| /linux-6.12.1/arch/mips/include/asm/octeon/ |
| D | cvmx-pciercx-defs.h | 258 __BITFIELD_FIELD(uint32_t eqc:1,
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| /linux-6.12.1/include/linux/ |
| D | hisi_acc_qm.h | 318 struct qm_eqc *eqc; member
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| /linux-6.12.1/drivers/s390/block/ |
| D | scm_blk.c | 381 switch (scmrq->aob->response.eqc) { in scm_blk_handle_error()
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| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/ |
| D | resource_tracker.c | 3061 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc) in eq_get_mtt_addr() argument
3063 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8; in eq_get_mtt_addr()
3066 static int eq_get_mtt_size(struct mlx4_eq_context *eqc) in eq_get_mtt_size() argument
3068 int log_eq_size = eqc->log_eq_size & 0x1f; in eq_get_mtt_size()
3069 int page_shift = (eqc->log_page_size & 0x3f) + 12; in eq_get_mtt_size()
3102 struct mlx4_eq_context *eqc = inbox->buf; in mlx4_SW2HW_EQ_wrapper() local
3103 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz; in mlx4_SW2HW_EQ_wrapper()
3104 int mtt_size = eq_get_mtt_size(eqc); in mlx4_SW2HW_EQ_wrapper()
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