Searched refs:drr_config (Results 1 – 8 of 8) sorted by relevance
934 if (master_timing->drr_config.enabled) { in build_synchronized_timing_groups()936 s->pmo_dcn4.group_is_drr_active[timing_group_idx] = !master_timing->drr_config.disallowed && in build_synchronized_timing_groups()937 (master_timing->drr_config.drr_active_fixed || master_timing->drr_config.drr_active_variable); in build_synchronized_timing_groups()1020 if (!stream_descriptor->timing.drr_config.enabled) in all_timings_support_drr()1035 if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 && in all_timings_support_drr()1036 …hed_vtotal - stream_fams2_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtot… in all_timings_support_drr()1425 stream_descriptor->timing.drr_config.enabled && in stream_matches_drr_policy()1426 …(stream_descriptor->timing.drr_config.drr_active_fixed || stream_descriptor->timing.drr_config.drr… in stream_matches_drr_policy()1431 stream_descriptor->timing.drr_config.enabled && in stream_matches_drr_policy()1432 stream_descriptor->timing.drr_config.drr_active_variable) { in stream_matches_drr_policy()[all …]
225 if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
373 timing->drr_config.enabled = stream->ignore_msa_timing_param; in populate_dml21_timing_config_from_stream_state()374 timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz; in populate_dml21_timing_config_from_stream_state()375 timing->drr_config.drr_active_variable = stream->vrr_active_variable; in populate_dml21_timing_config_from_stream_state()376 timing->drr_config.drr_active_fixed = stream->vrr_active_fixed; in populate_dml21_timing_config_from_stream_state()377 timing->drr_config.disallowed = !stream->allow_freesync; in populate_dml21_timing_config_from_stream_state()381 …timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instan… in populate_dml21_timing_config_from_stream_state()383 timing->drr_config.max_instant_vtotal_delta = 0; in populate_dml21_timing_config_from_stream_state()
274 } drr_config; member
429 phantom->timing.drr_config.enabled = false; in create_phantom_stream_from_main_stream()
163 phantom->timing.drr_config.enabled = false; in create_phantom_stream_from_main_stream()
8644 …cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? in dml_core_mode_support()10763 …cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? in dml_core_mode_programming()12338 fams2_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled; in dml2_core_calcs_get_stream_fams2_programming()
404 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()