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Searched refs:dram_type (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/ast/
Dast_main.c169 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
185 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
189 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()
192 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()
195 ast->dram_type = AST_DRAM_8Gx16; in ast_get_dram_info()
201 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()
205 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
208 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()
211 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()
218 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()
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Dast_post.c299 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
301 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
375 u32 dram_type; member
1599 param.dram_type = AST_DDR3; in ast_post_chip_2300()
1602 param.dram_type = AST_DDR2; in ast_post_chip_2300()
1637 if (param.dram_type == AST_DDR3) { in ast_post_chip_2300()
Dast_drv.h180 uint32_t dram_type; member
/linux-6.12.1/drivers/memory/tegra/
Dtegra210-emc-cc-r21021.c371 u32 value, dram_type; in tegra210_emc_r21021_set_clock() local
383 dram_type = value >> EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in tegra210_emc_r21021_set_clock()
390 dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
393 if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
397 (dram_type == DRAM_TYPE_LPDDR2)) in tegra210_emc_r21021_set_clock()
429 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()
606 if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
617 if (dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
619 else if (dram_type == DRAM_TYPE_LPDDR2 || is_lpddr3) in tegra210_emc_r21021_set_clock()
622 else if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
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Dtegra124-emc.c490 enum emc_dram_type dram_type; member
629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
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Dtegra30-emc.c527 enum emc_dram_type dram_type; in emc_prepare_timing_change() local
572 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_prepare_timing_change()
648 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { in emc_prepare_timing_change()
701 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
731 if (dram_type == DRAM_TYPE_DDR3) in emc_prepare_timing_change()
736 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
1120 enum emc_dram_type dram_type; in emc_setup_hw() local
1125 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_setup_hw()
1133 switch (dram_type) { in emc_setup_hw()
1159 switch (dram_type) { in emc_setup_hw()
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Dtegra20-emc.c598 enum emc_dram_type dram_type; in emc_setup_hw() local
638 dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio); in emc_setup_hw()
640 switch (dram_type) { in emc_setup_hw()
662 if (dram_type == DRAM_TYPE_LPDDR2) { in emc_setup_hw()
Dtegra210-emc-core.c772 if ((emc->dram_type != DRAM_TYPE_LPDDR2 && in tegra210_emc_set_refresh()
773 emc->dram_type != DRAM_TYPE_LPDDR4) || in tegra210_emc_set_refresh()
1774 emc->dram_type = value & 0x3; in tegra210_emc_detect()
Dtegra210-emc.h908 unsigned int dram_type; member
/linux-6.12.1/arch/mips/ralink/
Dmt7620.c46 static int dram_type; variable
53 switch (dram_type) { in mt7620_dram_init()
79 switch (dram_type) { in mt7628_dram_init()
233 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; in prom_soc_init()
235 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & in prom_soc_init()
237 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) in prom_soc_init()
238 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; in prom_soc_init()
/linux-6.12.1/drivers/edac/
Damd64_edac.c1163 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1547 umc->dram_type = MEM_EMPTY; in umc_determine_memory_type()
1557 umc->dram_type = MEM_LRDDR5; in umc_determine_memory_type()
1559 umc->dram_type = MEM_RDDR5; in umc_determine_memory_type()
1561 umc->dram_type = MEM_DDR5; in umc_determine_memory_type()
1564 umc->dram_type = MEM_LRDDR4; in umc_determine_memory_type()
1566 umc->dram_type = MEM_RDDR4; in umc_determine_memory_type()
1568 umc->dram_type = MEM_DDR4; in umc_determine_memory_type()
1571 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in umc_determine_memory_type()
1584 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in dct_determine_memory_type()
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Daspeed_edac.c234 u32 nr_pages, dram_type; in init_csrows() local
265 dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3; in init_csrows()
268 dimm->mtype = dram_type; in init_csrows()
Damd64_edac.h311 enum mem_type dram_type; member
380 enum mem_type dram_type; member