Searched refs:dram_bw_table (Results 1 – 6 of 6) sorted by relevance
63 …min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_tab… in build_min_clk_table_fine_grained()65 …min_table->dram_bw_table.entries[i].min_fclk_khz = (unsigned long)((((double)min_table->dram_bw_ta… in build_min_clk_table_fine_grained()67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()70 for (i = min_table->dram_bw_table.num_entries - 1; i > 0; i--) { in build_min_clk_table_fine_grained()71 prev_100 = min_table->dram_bw_table.entries[i - 1].min_fclk_khz; in build_min_clk_table_fine_grained()72 cur_50 = min_table->dram_bw_table.entries[i].min_fclk_khz / 2; in build_min_clk_table_fine_grained()73 min_table->dram_bw_table.entries[i].min_fclk_khz = prev_100 > cur_50 ? prev_100 : cur_50; in build_min_clk_table_fine_grained()76 …min_table->dram_bw_table.entries[i].min_fclk_khz = round_up_to_quantized_values(min_table->dram_bw… in build_min_clk_table_fine_grained()79 min_table->dram_bw_table.entries[0].min_fclk_khz /= 2; in build_min_clk_table_fine_grained()82 for (i = 0; i < (int)min_table->dram_bw_table.num_entries; i++) { in build_min_clk_table_fine_grained()[all …]
75 pmo_init_params.mcg_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries; in dml2_initialize_instance()86 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()
34 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; in get_minimum_clocks_for_latency()35 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()36 …*uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_… in get_minimum_clocks_for_latency()
49 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; member
7047 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml_core_mode_support()7048 …mode_lib->ms.FabricClock = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_in… in dml_core_mode_support()7054 …mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_… in dml_core_mode_support()7055 …mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()7056 …lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_ta… in dml_core_mode_support()9992 …double hard_minimum_dcfclk_mhz = (double)min_clk_table->dram_bw_table.entries[0].min_dcfclk_khz / … in dml_core_mode_programming()10092 …dml2_printf("DML::%s: min_clk_table min_fclk_khz = %d\n", __func__, min_clk_table->dram_bw_table.e… in dml_core_mode_programming()10093 …e uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out… in dml_core_mode_programming()
773 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml2_core_shared_mode_support()774 …mode_lib->ms.FabricClock = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_in… in dml2_core_shared_mode_support()780 …mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_… in dml2_core_shared_mode_support()781 …mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml2_core_shared_mode_support()9923 …dml2_printf("DML::%s: min_clk_table min_fclk_khz = %d\n", __func__, min_clk_table->dram_bw_table.e… in dml2_core_shared_mode_programming()9924 …e uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out… in dml2_core_shared_mode_programming()11389 …double hard_minimum_dcfclk_mhz = (double)min_clk_table->dram_bw_table.entries[0].min_dcfclk_khz / … in dml2_core_shared_mode_programming()