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Searched refs:dppclk (Results 1 – 21 of 21) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
Ddml2_mcg_dcn4.c180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_wrapper.c178 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
180 …in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table. in dml21_calculate_rq_and_dlg_params()
182 …dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] … in dml21_calculate_rq_and_dlg_params()
Ddml21_translation_helper.c200 dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; in dml21_apply_soc_bb_overrides()
202 if (i < dml_clk_table->dppclk.num_clk_values) { in dml21_apply_soc_bb_overrides()
206 dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
207 dml_clk_table->dppclk.num_clk_values = i + 1; in dml21_apply_soc_bb_overrides()
209 dml_clk_table->dppclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()
210 dml_clk_table->dppclk.num_clk_values = i; in dml21_apply_soc_bb_overrides()
213 dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
216 dml_clk_table->dppclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
Ddml_top_soc_parameter_types.h120 struct dml2_clk_table dppclk; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
Ddcn4_soc_bb.h102 .dppclk = {
Ddcn3_soc_bb.h152 .dppclk = {
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h178 uint32_t dppclk; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calc_auto.c1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1300 …>display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1312 …ine_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1423 …=dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1426 …=dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixe… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 …v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispcl… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1654 …v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispc… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1655 …v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_de… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1656 …_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sle… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1786 …pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all …]
Ddcn_calcs.c496 input->clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h391 uint32_t dppclk : 1; member
Ddcn_calcs.h436 float dppclk; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
Ddml2_internal_shared_types.h33 unsigned int dppclk; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
Ddml2_dpmm_dcn4.c354 …_to_next_dpm(&display_cfg->plane_programming[i].min_clocks.dcn4x.dppclk_khz, &state_table->dppclk); in map_min_clocks_to_dpm()
367 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dpprefclk_khz, &state_table->dppclk); in map_min_clocks_to_dpm()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
Ddcn401_clk_mgr.c341 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()
483 clk_register_dump.dppclk, in dcn401_auto_dpm_test_log()
1251 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk; in dcn401_build_update_display_clocks_sequence()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c320 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in rn_dump_clk_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in vg_dump_clk_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.c1501 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1581 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1667 if (pipe_ctx->update_flags.bits.dppclk) in dcn20_update_dchubp_dpp()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr.c916 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
Ddcn32_hwseq.c1455 phantom_pipe->update_flags.bits.dppclk = 1; in dcn32_apply_update_flags_for_phantom()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_shared.c779 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dppclk / 1000; in dml2_core_shared_mode_support()
Ddml2_core_dcn4_calcs.c7053 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dppclk / 1000; in dml_core_mode_support()