| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 628 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
629 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
662 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
675 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega12_setup_default_dpm_tables()
688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega12_setup_default_dpm_tables()
701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega12_setup_default_dpm_tables()
714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega12_setup_default_dpm_tables()
727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega12_setup_default_dpm_tables()
740 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega12_setup_default_dpm_tables()
805 dpm_table->dpm_levels[min_level].value;
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| D | vega20_hwmgr.c | 586 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
629 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega20_setup_memclk_dpm_table()
661 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega20_setup_default_dpm_tables()
688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega20_setup_default_dpm_tables()
701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega20_setup_default_dpm_tables()
714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega20_setup_default_dpm_tables()
727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega20_setup_default_dpm_tables()
773 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; in vega20_setup_default_dpm_tables()
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| D | vega10_hwmgr.c | 1249 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1251 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1253 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1367 dpm_table->dpm_levels[dpm_table->count-1].value; in vega10_setup_default_dpm_tables()
1378 dpm_table->dpm_levels[dpm_table->count-1].value; in vega10_setup_default_dpm_tables()
1384 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1387 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_dpm_tables()
1389 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; in vega10_setup_default_dpm_tables()
1399 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1402 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_dpm_tables()
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| D | smu7_hwmgr.c | 807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
811 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
821 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
825 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
832 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
833 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; in smu7_setup_dpm_tables_v0()
835 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; in smu7_setup_dpm_tables_v0()
844 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
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| D | smu7_hwmgr.h | 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0_7_ppt.c | 594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
595 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
596 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_7_set_default_dpm_table()
597 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v13_0_7_set_default_dpm_table()
610 (dpm_table->dpm_levels[dpm_table->count - 1].value > in smu_v13_0_7_set_default_dpm_table()
612 dpm_table->dpm_levels[dpm_table->count - 1].value = in smu_v13_0_7_set_default_dpm_table()
618 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_7_set_default_dpm_table()
619 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
620 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_7_set_default_dpm_table()
621 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v13_0_7_set_default_dpm_table()
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| D | aldebaran_ppt.c | 362 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in aldebaran_set_default_dpm_table()
363 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
364 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
365 dpm_table->max = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
373 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; in aldebaran_set_default_dpm_table()
374 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
375 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; in aldebaran_set_default_dpm_table()
376 dpm_table->dpm_levels[1].enabled = true; in aldebaran_set_default_dpm_table()
377 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
378 dpm_table->max = dpm_table->dpm_levels[1].value; in aldebaran_set_default_dpm_table()
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| D | smu_v13_0_0_ppt.c | 587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
588 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
589 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_0_set_default_dpm_table()
590 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v13_0_0_set_default_dpm_table()
612 (dpm_table->dpm_levels[dpm_table->count - 1].value > in smu_v13_0_0_set_default_dpm_table()
614 dpm_table->dpm_levels[dpm_table->count - 1].value = in smu_v13_0_0_set_default_dpm_table()
620 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_0_set_default_dpm_table()
621 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
622 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_0_set_default_dpm_table()
623 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v13_0_0_set_default_dpm_table()
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| D | smu_v13_0_6_ppt.c | 803 dpm_table->dpm_levels[0].value = gfxclkmin; in smu_v13_0_6_set_default_dpm_table()
804 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_6_set_default_dpm_table()
805 dpm_table->dpm_levels[1].value = gfxclkmax; in smu_v13_0_6_set_default_dpm_table()
806 dpm_table->dpm_levels[1].enabled = true; in smu_v13_0_6_set_default_dpm_table()
807 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_6_set_default_dpm_table()
808 dpm_table->max = dpm_table->dpm_levels[1].value; in smu_v13_0_6_set_default_dpm_table()
811 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency; in smu_v13_0_6_set_default_dpm_table()
812 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_6_set_default_dpm_table()
813 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v13_0_6_set_default_dpm_table()
814 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v13_0_6_set_default_dpm_table()
[all …]
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| D | aldebaran_ppt.h | 49 struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| D | smu_v14_0_2_ppt.c | 518 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v14_0_2_set_default_dpm_table()
519 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
520 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v14_0_2_set_default_dpm_table()
521 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v14_0_2_set_default_dpm_table()
543 (dpm_table->dpm_levels[dpm_table->count - 1].value > in smu_v14_0_2_set_default_dpm_table()
545 dpm_table->dpm_levels[dpm_table->count - 1].value = in smu_v14_0_2_set_default_dpm_table()
551 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v14_0_2_set_default_dpm_table()
552 dpm_table->dpm_levels[0].enabled = true; in smu_v14_0_2_set_default_dpm_table()
553 dpm_table->min = dpm_table->dpm_levels[0].value; in smu_v14_0_2_set_default_dpm_table()
554 dpm_table->max = dpm_table->dpm_levels[0].value; in smu_v14_0_2_set_default_dpm_table()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
986 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
987 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
988 dpm_table->max = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in navi10_set_default_dpm_table()
1004 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
1005 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
1006 dpm_table->max = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in navi10_set_default_dpm_table()
1022 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
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| D | arcturus_ppt.c | 380 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
381 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
382 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
383 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
398 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in arcturus_set_default_dpm_table()
399 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
400 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
401 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
416 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
417 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
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| D | sienna_cichlid_ppt.c | 975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
976 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
977 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
978 dpm_table->max = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in sienna_cichlid_set_default_dpm_table()
994 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
995 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
996 dpm_table->max = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
1012 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
[all …]
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| D | arcturus_ppt.h | 49 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2514 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2515 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2573 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2591 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2593 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
3247 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3293 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3296 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3338 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3344 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
[all …]
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| D | ci_dpm.h | 65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | fiji_smumgr.c | 838 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level()
840 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1239 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
1536 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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| D | polaris10_smumgr.c | 827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1228 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1764 data->dpm_table.mclk_table.dpm_levels[i].value, in iceland_convert_mc_reg_table_to_smc()
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| D | vegam_smumgr.c | 581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1054 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1291 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
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| D | ci_smumgr.c | 488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
1007 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
1009 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
1317 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1319 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1663 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1664 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1799 data->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| D | smu_v14_0.h | 80 struct smu_14_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
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| D | smu_v11_0.h | 93 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
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| D | smu_v13_0.h | 81 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
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